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authorRocco Marco Guglielmi <roccomarco.guglielmi@live.com>2017-08-09 21:36:51 +0000
committerRocco Marco Guglielmi <roccomarco.guglielmi@live.com>2017-08-09 21:36:51 +0000
commitf9ec8eaed614de52e2877308dd1a7800d4b2637f (patch)
treeeb3b742ac7a5f2269b2b19bac6900fdbece7b454 /os
parentd815243fa40a9b9496a14ed54a101ff90bc060b6 (diff)
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Added sama_pmc and improved clock init
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10379 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
-rw-r--r--os/hal/ports/SAMA/SAMA5D2x/hal_lld.c6
-rw-r--r--os/hal/ports/SAMA/SAMA5D2x/hal_lld.h17
-rw-r--r--os/hal/ports/SAMA/SAMA5D2x/sama_pmc.h160
3 files changed, 173 insertions, 10 deletions
diff --git a/os/hal/ports/SAMA/SAMA5D2x/hal_lld.c b/os/hal/ports/SAMA/SAMA5D2x/hal_lld.c
index 114c7dc4a..c852d44b6 100644
--- a/os/hal/ports/SAMA/SAMA5D2x/hal_lld.c
+++ b/os/hal/ports/SAMA/SAMA5D2x/hal_lld.c
@@ -75,7 +75,7 @@ void sama_clock_init(void) {
#if !SAMA_NO_INIT
uint32_t mor, pllar, mckr;
/* Disabling PMC write protection. */
- PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD;
+ pmcDisableWP();
/* Enforces the reset default configuration of clock tree. */
{
@@ -178,8 +178,8 @@ void sama_clock_init(void) {
SCKC->SCKC_CR = SAMA_OSC_SEL;
}
-/* Enabling write protection. */
-PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD | PMC_WPMR_WPEN;
+ /* Enabling write protection. */
+ pmcEnableWP();
#endif /* !SAMA_NO_INIT */
}
diff --git a/os/hal/ports/SAMA/SAMA5D2x/hal_lld.h b/os/hal/ports/SAMA/SAMA5D2x/hal_lld.h
index ac3f7bc3b..bab9e45a1 100644
--- a/os/hal/ports/SAMA/SAMA5D2x/hal_lld.h
+++ b/os/hal/ports/SAMA/SAMA5D2x/hal_lld.h
@@ -409,14 +409,14 @@
* @brief Processor Clock frequency.
*/
#if (SAMA_MCK_SEL == SAMA_MCK_SLOW_CLK) || defined(__DOXYGEN__)
-#define SAMA_PCKOUT (SAMA_SLOW_CLK / SAMA_MCK_PRES_VALUE)
+#define SAMA_PCK (SAMA_SLOW_CLK / SAMA_MCK_PRES_VALUE)
#elif (SAMA_MCK_SEL == SAMA_MCK_MAIN_CLK)
-#define SAMA_PCKOUT (SAMA_MAIN_CLK / SAMA_MCK_PRES_VALUE)
+#define SAMA_PCK (SAMA_MAIN_CLK / SAMA_MCK_PRES_VALUE)
#elif (SAMA_MCK_SEL == SAMA_MCK_PLLA_CLK)
#if SAMA_PLLADIV2_EN
-#define SAMA_PCKOUT (SAMA_PLLACLKOUT / SAMA_MCK_PRES_VALUE / 2)
+#define SAMA_PCK (SAMA_PLLACLKOUT / SAMA_MCK_PRES_VALUE / 2)
#else
-#define SAMA_PCKOUT (SAMA_PLLACLKOUT / SAMA_MCK_PRES_VALUE)
+#define SAMA_PCK (SAMA_PLLACLKOUT / SAMA_MCK_PRES_VALUE)
#endif
#elif (SAMA_MCK_SEL == SAMA_MCK_UPLL_CLK)
#error "UPLL still unsupported"
@@ -427,15 +427,15 @@
/**
* @brief Master Clock frequency.
*/
-#define SAMA_MCKOUT (SAMA_PCKOUT / SAMA_MCK_MDIV_VALUE)
+#define SAMA_MCK (SAMA_PCK / SAMA_MCK_MDIV_VALUE)
/* Checks on Processor Clock crystal range. */
-#if (SAMA_PCKOUT > SAMA_PCK_MAX) || (SAMA_PCKOUT < SAMA_PCK_MIN)
+#if (SAMA_PCK > SAMA_PCK_MAX) || (SAMA_PCK < SAMA_PCK_MIN)
#error "Processor clock frequency out of range."
#endif
/* Checks on Master Clock crystal range. */
-#if (SAMA_MCKOUT > SAMA_MCK_MAX) || (SAMA_MCKOUT < SAMA_MCK_MIN)
+#if (SAMA_MCK > SAMA_MCK_MAX) || (SAMA_MCK < SAMA_MCK_MIN)
#error "Master clock frequency out of range."
#endif
/*===========================================================================*/
@@ -450,6 +450,9 @@
/* External declarations. */
/*===========================================================================*/
+/* Various helpers.*/
+#include "sama_pmc.h"
+
#ifdef __cplusplus
extern "C" {
#endif
diff --git a/os/hal/ports/SAMA/SAMA5D2x/sama_pmc.h b/os/hal/ports/SAMA/SAMA5D2x/sama_pmc.h
new file mode 100644
index 000000000..9e31ea579
--- /dev/null
+++ b/os/hal/ports/SAMA/SAMA5D2x/sama_pmc.h
@@ -0,0 +1,160 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SAMA5D2x/sama_pmc.h
+ * @brief PMC helper driver header.
+ *
+ * @addtogroup SAMA5D2x_PMC
+ * @{
+ */
+
+#ifndef _SAMA_PMC_
+#define _SAMA_PMC_
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name Generic PMC operations
+ * @{
+ */
+/**
+ * @brief Enable write protection on PMC registers block.
+ *
+ * @api
+ */
+#define pmcEnableWP() { \
+ PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD | PMC_WPMR_WPEN; \
+}
+
+/**
+ * @brief Disable write protection on PMC registers block.
+ *
+ * @api
+ */
+#define pmcDisableWP() { \
+ PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD; \
+}
+
+/**
+ * @brief Enables the clock of one or more peripheral having ID from 2 to
+ * 31.
+ *
+ * @param[in] mask PCER0 peripherals mask
+ *
+ * @api
+ */
+#define pmcEnablePidLow(mask) { \
+ pmcDisableWP(); \
+ PMC->PMC_PCER0 |= (mask); \
+ pmcDisableWP(); \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral having ID from 2 to
+ * 31.
+ *
+ * @param[in] mask PCDR0 peripherals mask
+ *
+ * @api
+ */
+#define pmcDisablePidLow(mask) { \
+ pmcDisableWP(); \
+ PMC->PMC_PCDR0 |= (mask); \
+ pmcDisableWP(); \
+}
+
+/**
+ * @brief Enables the clock of one or more peripheral having ID from 32 to
+ * 63.
+ *
+ * @param[in] mask PCER1 peripherals mask
+ *
+ * @api
+ */
+#define pmcEnablePidHigh(mask) { \
+ pmcDisableWP(); \
+ PMC->PMC_PCER1 |= (mask); \
+ pmcDisableWP(); \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral having ID from 32 to
+ * 63.
+ *
+ * @param[in] mask PCDR1 peripherals mask
+ *
+ * @api
+ */
+#define pmcDisablePidHigh(mask) { \
+ pmcDisableWP(); \
+ PMC->PMC_PCDR1 |= (mask); \
+ pmcDisableWP(); \
+}
+/** @} */
+
+/**
+ * @name ADC peripherals specific PMC operations
+ * @{
+ */
+/**
+ * @brief Enables the PIT peripheral clock.
+ *
+ * @api
+ */
+#define pmcEnablePIT() pmcEnablePidLow(SAMA_PID_PIT)
+
+/**
+ * @brief Disables the PIT peripheral clock.
+ *
+ * @api
+ */
+#define pmcDisablePIT() pmcDisablePidLow(SAMA_PID_PIT)
+
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SAMA_PMC_ */
+
+/** @} */