git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2850 35acf78f-673a-0410-8e92-d51de3d6d3f4

24 files changed, 383 insertions, 91 deletions

diff --git a/os/hal/hal.mk b/os/hal/hal.mk
index 49561ee8d..52b9fab81 100644
--- a/os/hal/hal.mk
+++ b/os/hal/hal.mk
@@ -5,6 +5,7 @@ HALSRC = ${CHIBIOS}/os/hal/src/hal.c \
          ${CHIBIOS}/os/hal/src/can.c \

          ${CHIBIOS}/os/hal/src/gpt.c \

          ${CHIBIOS}/os/hal/src/i2c.c \

+         ${CHIBIOS}/os/hal/src/icu.c \

          ${CHIBIOS}/os/hal/src/mac.c \

          ${CHIBIOS}/os/hal/src/pal.c \

          ${CHIBIOS}/os/hal/src/pwm.c \

diff --git a/os/hal/include/hal.h b/os/hal/include/hal.h
index bd234a494..400aec17f 100644
--- a/os/hal/include/hal.h
+++ b/os/hal/include/hal.h
@@ -39,6 +39,7 @@
 #include "can.h"

 #include "gpt.h"

 #include "i2c.h"

+#include "icu.h"

 #include "mac.h"

 #include "pwm.h"

 #include "serial.h"

diff --git a/os/hal/platforms/STM32/gpt_lld.c b/os/hal/platforms/STM32/gpt_lld.c
index 0c84b6a0a..ffbfe475c 100644
--- a/os/hal/platforms/STM32/gpt_lld.c
+++ b/os/hal/platforms/STM32/gpt_lld.c
@@ -48,40 +48,40 @@
 /*===========================================================================*/

 

 /**

- * @brief   GPT1 driver identifier.

- * @note    The driver GPT1 allocates the complex timer TIM1 when enabled.

+ * @brief   GPTD1 driver identifier.

+ * @note    The driver GPTD1 allocates the complex timer TIM1 when enabled.

  */

 #if STM32_GPT_USE_TIM1 || defined(__DOXYGEN__)

 GPTDriver GPTD1;

 #endif

 

 /**

- * @brief   GPT2 driver identifier.

- * @note    The driver GPT2 allocates the timer TIM2 when enabled.

+ * @brief   GPTD2 driver identifier.

+ * @note    The driver GPTD2 allocates the timer TIM2 when enabled.

  */

 #if STM32_GPT_USE_TIM2 || defined(__DOXYGEN__)

 GPTDriver GPTD2;

 #endif

 

 /**

- * @brief   GPT3 driver identifier.

- * @note    The driver GPT3 allocates the timer TIM3 when enabled.

+ * @brief   GPTD3 driver identifier.

+ * @note    The driver GPTD3 allocates the timer TIM3 when enabled.

  */

 #if STM32_GPT_USE_TIM3 || defined(__DOXYGEN__)

 GPTDriver GPTD3;

 #endif

 

 /**

- * @brief   GPT4 driver identifier.

- * @note    The driver GPT4 allocates the timer TIM4 when enabled.

+ * @brief   GPTD4 driver identifier.

+ * @note    The driver GPTD4 allocates the timer TIM4 when enabled.

  */

 #if STM32_GPT_USE_TIM4 || defined(__DOXYGEN__)

 GPTDriver GPTD4;

 #endif

 

 /**

- * @brief   GPT5 driver identifier.

- * @note    The driver GPT5 allocates the timer TIM5 when enabled.

+ * @brief   GPTD5 driver identifier.

+ * @note    The driver GPTD5 allocates the timer TIM5 when enabled.

  */

 #if STM32_GPT_USE_TIM5 || defined(__DOXYGEN__)

 GPTDriver GPTD5;

diff --git a/os/hal/platforms/STM32/gpt_lld.h b/os/hal/platforms/STM32/gpt_lld.h
index 37836ddab..2d7fd13f1 100644
--- a/os/hal/platforms/STM32/gpt_lld.h
+++ b/os/hal/platforms/STM32/gpt_lld.h
@@ -40,8 +40,8 @@
 /*===========================================================================*/

 

 /**

- * @brief   GPT1 driver enable switch.

- * @details If set to @p TRUE the support for GPT1 is included.

+ * @brief   GPTD1 driver enable switch.

+ * @details If set to @p TRUE the support for GPTD1 is included.

  * @note    The default is @p TRUE.

  */

 #if !defined(STM32_GPT_USE_TIM1) || defined(__DOXYGEN__)

@@ -49,8 +49,8 @@
 #endif

 

 /**

- * @brief   GPT2 driver enable switch.

- * @details If set to @p TRUE the support for GPT2 is included.

+ * @brief   GPTD2 driver enable switch.

+ * @details If set to @p TRUE the support for GPTD2 is included.

  * @note    The default is @p TRUE.

  */

 #if !defined(STM32_GPT_USE_TIM2) || defined(__DOXYGEN__)

@@ -58,8 +58,8 @@
 #endif

 

 /**

- * @brief   GPT3 driver enable switch.

- * @details If set to @p TRUE the support for GPT3 is included.

+ * @brief   GPTD3 driver enable switch.

+ * @details If set to @p TRUE the support for GPTD3 is included.

  * @note    The default is @p TRUE.

  */

 #if !defined(STM32_GPT_USE_TIM3) || defined(__DOXYGEN__)

@@ -67,8 +67,8 @@
 #endif

 

 /**

- * @brief   GPT4 driver enable switch.

- * @details If set to @p TRUE the support for GPT4 is included.

+ * @brief   GPTD4 driver enable switch.

+ * @details If set to @p TRUE the support for GPTD4 is included.

  * @note    The default is @p TRUE.

  */

 #if !defined(STM32_GPT_USE_TIM4) || defined(__DOXYGEN__)

@@ -76,8 +76,8 @@
 #endif

 

 /**

- * @brief   GPT5 driver enable switch.

- * @details If set to @p TRUE the support for GPT5 is included.

+ * @brief   GPTD5 driver enable switch.

+ * @details If set to @p TRUE the support for GPTD5 is included.

  * @note    The default is @p TRUE.

  */

 #if !defined(STM32_GPT_USE_TIM5) || defined(__DOXYGEN__)

@@ -85,35 +85,35 @@
 #endif

 

 /**

- * @brief   GPT1 interrupt priority level setting.

+ * @brief   GPTD1 interrupt priority level setting.

  */

 #if !defined(STM32_GPT_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__)

 #define STM32_GPT_TIM1_IRQ_PRIORITY         7

 #endif

 

 /**

- * @brief   GPT2 interrupt priority level setting.

+ * @brief   GPTD2 interrupt priority level setting.

  */

 #if !defined(STM32_GPT_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__)

 #define STM32_GPT_TIM2_IRQ_PRIORITY         7

 #endif

 

 /**

- * @brief   GPT3 interrupt priority level setting.

+ * @brief   GPTD3 interrupt priority level setting.

  */

 #if !defined(STM32_GPT_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__)

 #define STM32_GPT_TIM3_IRQ_PRIORITY         7

 #endif

 

 /**

- * @brief   GPT4 interrupt priority level setting.

+ * @brief   GPTD4 interrupt priority level setting.

  */

 #if !defined(STM32_GPT_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__)

 #define STM32_GPT_TIM4_IRQ_PRIORITY         7

 #endif

 

 /**

- * @brief   GPT5 interrupt priority level setting.

+ * @brief   GPTD5 interrupt priority level setting.

  */

 #if !defined(STM32_GPT_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__)

 #define STM32_GPT_TIM5_IRQ_PRIORITY         7

@@ -206,6 +206,9 @@ struct GPTDriver {
    * @brief Current configuration data.

    */

   const GPTConfig           *config;

+#if defined(GPT_DRIVER_EXT_FIELDS)

+  GPT_DRIVER_EXT_FIELDS

+#endif

   /* End of the mandatory fields.*/

   /**

    * @brief Timer base clock.

diff --git a/os/hal/platforms/STM32/icu_lld.c b/os/hal/platforms/STM32/icu_lld.c
index 6877b2d72..04c2f6372 100644
--- a/os/hal/platforms/STM32/icu_lld.c
+++ b/os/hal/platforms/STM32/icu_lld.c
@@ -36,13 +36,45 @@
 /*===========================================================================*/

 

 /**

- * @brief   ICU1 driver identifier.

+ * @brief   ICUD1 driver identifier.

  * @note    The driver ICUD1 allocates the complex timer TIM1 when enabled.

  */

 #if STM32_ICU_USE_TIM1 || defined(__DOXYGEN__)

 ICUDriver ICUD1;

 #endif

 

+/**

+ * @brief   ICUD2 driver identifier.

+ * @note    The driver ICUD1 allocates the timer TIM2 when enabled.

+ */

+#if STM32_ICU_USE_TIM2 || defined(__DOXYGEN__)

+ICUDriver ICUD2;

+#endif

+

+/**

+ * @brief   ICUD3 driver identifier.

+ * @note    The driver ICUD1 allocates the timer TIM3 when enabled.

+ */

+#if STM32_ICU_USE_TIM3 || defined(__DOXYGEN__)

+ICUDriver ICUD3;

+#endif

+

+/**

+ * @brief   ICUD4 driver identifier.

+ * @note    The driver ICUD4 allocates the timer TIM4 when enabled.

+ */

+#if STM32_ICU_USE_TIM4 || defined(__DOXYGEN__)

+ICUDriver ICUD4;

+#endif

+

+/**

+ * @brief   ICUD5 driver identifier.

+ * @note    The driver ICUD5 allocates the timer TIM5 when enabled.

+ */

+#if STM32_ICU_USE_TIM5 || defined(__DOXYGEN__)

+ICUDriver ICUD5;

+#endif

+

 /*===========================================================================*/

 /* Driver local variables.                                                   */

 /*===========================================================================*/

@@ -51,52 +83,120 @@ ICUDriver ICUD1;
 /* Driver local functions.                                                   */

 /*===========================================================================*/

 

+/**

+ * @brief   Shared IRQ handler.

+ *

+ * @param[in] icup      pointer to the @p ICUDriver object

+ */

+static void icu_lld_serve_interrupt(ICUDriver *icup) {

+  uint16_t sr;

+

+  sr = TIM1->SR & TIM1->DIER;

+  icup->tim->SR = 0;

+  if ((sr & TIM_SR_CC1IF) != 0)

+    icup->config->period_cb(icup);

+  if ((sr & TIM_SR_CC2IF) != 0)

+    icup->config->width_cb(icup);

+}

+

 /*===========================================================================*/

 /* Driver interrupt handlers.                                                */

 /*===========================================================================*/

 

 #if STM32_ICU_USE_TIM1

 /**

- * @brief   TIM1 update interrupt handler.

- * @note    It is assumed that this interrupt is only activated if the callback

- *          pointer is not equal to @p NULL in order to not perform an extra

- *          check in a potentially critical interrupt handler.

+ * @brief   TIM1 compare interrupt handler.

+ * @note    It is assumed that the various sources are only activated if the

+ *          associated callback pointer is not equal to @p NULL in order to not

+ *          perform an extra check in a potentially critical interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(TIM1_CC_IRQHandler) {

+

+  CH_IRQ_PROLOGUE();

+

+  icu_lld_serve_interrupt(&ICUD1);

+

+  CH_IRQ_EPILOGUE();

+}

+#endif /* STM32_ICU_USE_TIM1 */

+

+#if STM32_ICU_USE_TIM2

+/**

+ * @brief   TIM2 compare interrupt handler.

+ * @note    It is assumed that the various sources are only activated if the

+ *          associated callback pointer is not equal to @p NULL in order to not

+ *          perform an extra check in a potentially critical interrupt handler.

  *

  * @isr

  */

-CH_IRQ_HANDLER(TIM1_UP_IRQHandler) {

+CH_IRQ_HANDLER(TIM2_IRQHandler) {

 

   CH_IRQ_PROLOGUE();

 

-  TIM1->SR = ~TIM_SR_UIF;

-  ICUD1.config->callback(&ICUD1);

+  icu_lld_serve_interrupt(&ICUD2);

 

   CH_IRQ_EPILOGUE();

 }

+#endif /* STM32_ICU_USE_TIM2 */

 

+#if STM32_ICU_USE_TIM3

 /**

- * @brief   TIM1 compare interrupt handler.

+ * @brief   TIM3 compare interrupt handler.

  * @note    It is assumed that the various sources are only activated if the

  *          associated callback pointer is not equal to @p NULL in order to not

  *          perform an extra check in a potentially critical interrupt handler.

  *

  * @isr

  */

-CH_IRQ_HANDLER(TIM1_CC_IRQHandler) {

-  uint16_t sr;

+CH_IRQ_HANDLER(TIM3_IRQHandler) {

 

   CH_IRQ_PROLOGUE();

 

-  sr = TIM1->SR & TIM1->DIER;

-  TIM1->SR = ~(TIM_SR_CC1IF | TIM_SR_CC2IF | TIM_SR_CC3IF | TIM_SR_CC4IF);

-  if ((sr & TIM_SR_CC1IF) != 0)

-    ICUD1.config->channels[0].callback(&ICUD1);

-  if ((sr & TIM_SR_CC2IF) != 0)

-    ICUD1.config->channels[1].callback(&ICUD1);

+  icu_lld_serve_interrupt(&ICUD3);

 

   CH_IRQ_EPILOGUE();

 }

-#endif /* STM32_ICU_USE_TIM1 */

+#endif /* STM32_ICU_USE_TIM3 */

+

+#if STM32_ICU_USE_TIM4

+/**

+ * @brief   TIM4 compare interrupt handler.

+ * @note    It is assumed that the various sources are only activated if the

+ *          associated callback pointer is not equal to @p NULL in order to not

+ *          perform an extra check in a potentially critical interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(TIM4_IRQHandler) {

+

+  CH_IRQ_PROLOGUE();

+

+  icu_lld_serve_interrupt(&ICUD4);

+

+  CH_IRQ_EPILOGUE();

+}

+#endif /* STM32_ICU_USE_TIM4 */

+

+#if STM32_ICU_USE_TIM5

+/**

+ * @brief   TIM5 compare interrupt handler.

+ * @note    It is assumed that the various sources are only activated if the

+ *          associated callback pointer is not equal to @p NULL in order to not

+ *          perform an extra check in a potentially critical interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(TIM5_IRQHandler) {

+

+  CH_IRQ_PROLOGUE();

+

+  icu_lld_serve_interrupt(&ICUD5);

+

+  CH_IRQ_EPILOGUE();

+}

+#endif /* STM32_ICU_USE_TIM5 */

 

 /*===========================================================================*/

 /* Driver exported functions.                                                */

@@ -114,6 +214,30 @@ void icu_lld_init(void) {
   icuObjectInit(&ICUD1);

   ICUD1.tim = TIM1;

 #endif

+

+#if STM32_ICU_USE_TIM2

+  /* Driver initialization.*/

+  icuObjectInit(&ICUD2);

+  ICUD2.tim = TIM2;

+#endif

+

+#if STM32_ICU_USE_TIM3

+  /* Driver initialization.*/

+  icuObjectInit(&ICUD3);

+  ICUD3.tim = TIM3;

+#endif

+

+#if STM32_ICU_USE_TIM4

+  /* Driver initialization.*/

+  icuObjectInit(&ICUD4);

+  ICUD4.tim = TIM4;

+#endif

+

+#if STM32_ICU_USE_TIM5

+  /* Driver initialization.*/

+  icuObjectInit(&ICUD5);

+  ICUD5.tim = TIM5;

+#endif

 }

 

 /**

@@ -132,12 +256,47 @@ void icu_lld_start(ICUDriver *icup) {
       RCC->APB2ENR |= RCC_APB2ENR_TIM1EN;

       RCC->APB2RSTR = RCC_APB2RSTR_TIM1RST;

       RCC->APB2RSTR = 0;

-      NVICEnableVector(TIM1_UP_IRQn,

-                       CORTEX_PRIORITY_MASK(STM32_ICU_TIM1_IRQ_PRIORITY));

       NVICEnableVector(TIM1_CC_IRQn,

                        CORTEX_PRIORITY_MASK(STM32_ICU_TIM1_IRQ_PRIORITY));

     }

 #endif

+#if STM32_ICU_USE_TIM2

+    if (&ICUD2 == icup) {

+      RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;

+      RCC->APB1RSTR = RCC_APB1RSTR_TIM2RST;

+      RCC->APB1RSTR = 0;

+      NVICEnableVector(TIM2_IRQn,

+                       CORTEX_PRIORITY_MASK(STM32_ICU_TIM2_IRQ_PRIORITY));

+    }

+#endif

+#if STM32_ICU_USE_TIM3

+    if (&ICUD3 == icup) {

+      RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;

+      RCC->APB1RSTR = RCC_APB1RSTR_TIM3RST;

+      RCC->APB1RSTR = 0;

+      NVICEnableVector(TIM3_IRQn,

+                       CORTEX_PRIORITY_MASK(STM32_ICU_TIM3_IRQ_PRIORITY));

+    }

+#endif

+#if STM32_ICU_USE_TIM4

+    if (&ICUD4 == icup) {

+      RCC->APB1ENR |= RCC_APB1ENR_TIM4EN;

+      RCC->APB1RSTR = RCC_APB1RSTR_TIM4RST;

+      RCC->APB1RSTR = 0;

+      NVICEnableVector(TIM4_IRQn,

+                       CORTEX_PRIORITY_MASK(STM32_ICU_TIM4_IRQ_PRIORITY));

+    }

+#endif

+

+#if STM32_ICU_USE_TIM5

+    if (&ICUD5 == icup) {

+      RCC->APB1ENR |= RCC_APB1ENR_TIM5EN;

+      RCC->APB1RSTR = RCC_APB1RSTR_TIM5RST;

+      RCC->APB1RSTR = 0;

+      NVICEnableVector(TIM5_IRQn,

+                       CORTEX_PRIORITY_MASK(STM32_ICU_TIM5_IRQ_PRIORITY));

+    }

+#endif

   }

 

   /* Timer configuration, PWM input mode.*/

@@ -153,7 +312,7 @@ void icu_lld_start(ICUDriver *icup) {
   /* SMCR_TS  = 101, input is TI1FP1.

      SMCR_SMS = 100, reset on rising edge.*/

   icup->tim->SMCR  = TIM_SMCR_TS_2 | TIM_SMCR_TS_0 |

-                     TIM_SMCR_SMS_2.

+                     TIM_SMCR_SMS_2;

   /* The CCER settings depend on the selected trigger mode.

      ICU_INPUT_ACTIVE_HIGH: Active on rising edge, idle on falling edge.

      ICU_INPUT_ACTIVE_LOW:  Active on falling edge, idle on rising edge.*/

@@ -161,7 +320,7 @@ void icu_lld_start(ICUDriver *icup) {
     icup->tim->CCER = TIM_CCER_CC1E |

                       TIM_CCER_CC2E | TIM_CCER_CC2P;

   else

-    icup->tim->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P

+    icup->tim->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P |

                       TIM_CCER_CC2E;

 }

 

@@ -181,11 +340,35 @@ void icu_lld_stop(ICUDriver *icup) {
 

 #if STM32_ICU_USE_TIM1

     if (&ICUD1 == icup) {

-      NVICDisableVector(TIM1_UP_IRQn);

+      NVICDisableVector(TIM1_CC_IRQn);

       RCC->APB2ENR &= ~RCC_APB2ENR_TIM1EN;

     }

 #endif

   }

+#if STM32_ICU_USE_TIM2

+    if (&ICUD2 == icup) {

+      NVICDisableVector(TIM2_IRQn);

+      RCC->APB1ENR &= ~RCC_APB1ENR_TIM2EN;

+    }

+#endif

+#if STM32_ICU_USE_TIM3

+    if (&ICUD3 == icup) {

+      NVICDisableVector(TIM3_IRQn);

+      RCC->APB1ENR &= ~RCC_APB1ENR_TIM3EN;

+    }

+#endif

+#if STM32_ICU_USE_TIM4

+    if (&ICUD4 == icup) {

+      NVICDisableVector(TIM4_IRQn);

+      RCC->APB1ENR &= ~RCC_APB1ENR_TIM4EN;

+    }

+#endif

+#if STM32_ICU_USE_TIM5

+    if (&ICUD5 == icup) {

+      NVICDisableVector(TIM5_IRQn);

+      RCC->APB1ENR &= ~RCC_APB1ENR_TIM5EN;

+    }

+#endif

 }

 

 /**

@@ -198,7 +381,10 @@ void icu_lld_stop(ICUDriver *icup) {
 void icu_lld_enable(ICUDriver *icup) {

 

   icup->tim->SR   = 0;                      /* Clear pending IRQs (if any). */

-  icup->tim->DIER = TIM_DIER_CC1IE | TIM_DIER_CC2IE;

+  if (icup->config->period_cb != NULL)

+    icup->tim->DIER |= TIM_DIER_CC1IE;

+  if (icup->config->width_cb != NULL)

+    icup->tim->DIER |= TIM_DIER_CC2IE;

   icup->tim->CR1  = TIM_CR1_URS | TIM_CR1_CEN;

 }

 

diff --git a/os/hal/platforms/STM32/icu_lld.h b/os/hal/platforms/STM32/icu_lld.h
index 78efa9765..758b9c352 100644
--- a/os/hal/platforms/STM32/icu_lld.h
+++ b/os/hal/platforms/STM32/icu_lld.h
@@ -48,6 +48,77 @@
 #define STM32_ICU_USE_TIM1                  TRUE

 #endif

 

+/**

+ * @brief   ICUD2 driver enable switch.

+ * @details If set to @p TRUE the support for ICUD2 is included.

+ * @note    The default is @p TRUE.

+ */

+#if !defined(STM32_ICU_USE_TIM2) || defined(__DOXYGEN__)

+#define STM32_ICU_USE_TIM2                  TRUE

+#endif

+

+/**

+ * @brief   ICUD3 driver enable switch.

+ * @details If set to @p TRUE the support for ICUD3 is included.

+ * @note    The default is @p TRUE.

+ */

+#if !defined(STM32_ICU_USE_TIM3) || defined(__DOXYGEN__)

+#define STM32_ICU_USE_TIM3                  TRUE

+#endif

+

+/**

+ * @brief   ICUD4 driver enable switch.

+ * @details If set to @p TRUE the support for ICUD4 is included.

+ * @note    The default is @p TRUE.

+ */

+#if !defined(STM32_ICU_USE_TIM4) || defined(__DOXYGEN__)

+#define STM32_ICU_USE_TIM4                  TRUE

+#endif

+

+/**

+ * @brief   ICUD5 driver enable switch.

+ * @details If set to @p TRUE the support for ICUD5 is included.

+ * @note    The default is @p TRUE.

+ */

+#if !defined(STM32_ICU_USE_TIM5) || defined(__DOXYGEN__)

+#define STM32_ICU_USE_TIM5                  TRUE

+#endif

+

+/**

+ * @brief   ICUD1 interrupt priority level setting.

+ */

+#if !defined(STM32_ICU_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_ICU_TIM1_IRQ_PRIORITY         7

+#endif

+

+/**

+ * @brief   ICUD2 interrupt priority level setting.

+ */

+#if !defined(STM32_ICU_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_ICU_TIM2_IRQ_PRIORITY         7

+#endif

+

+/**

+ * @brief   ICUD3 interrupt priority level setting.

+ */

+#if !defined(STM32_ICU_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_ICU_TIM3_IRQ_PRIORITY         7

+#endif

+

+/**

+ * @brief   ICUD4 interrupt priority level setting.

+ */

+#if !defined(STM32_ICU_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_ICU_TIM4_IRQ_PRIORITY         7

+#endif

+

+/**

+ * @brief   ICUD5 interrupt priority level setting.

+ */

+#if !defined(STM32_ICU_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_ICU_TIM5_IRQ_PRIORITY         7

+#endif

+

 /*===========================================================================*/

 /* Derived constants and error checks.                                       */

 /*===========================================================================*/

@@ -143,6 +214,9 @@ struct ICUDriver {
    * @brief Current configuration data.

    */

   const ICUConfig           *config;

+#if defined(ICU_DRIVER_EXT_FIELDS)

+  ICU_DRIVER_EXT_FIELDS

+#endif

   /* End of the mandatory fields.*/

   /**

    * @brief Pointer to the TIMx registers block.

@@ -209,6 +283,22 @@ struct ICUDriver {
 extern ICUDriver ICUD1;

 #endif

 

+#if STM32_ICU_USE_TIM2 && !defined(__DOXYGEN__)

+extern ICUDriver ICUD2;

+#endif

+

+#if STM32_ICU_USE_TIM3 && !defined(__DOXYGEN__)

+extern ICUDriver ICUD3;

+#endif

+

+#if STM32_ICU_USE_TIM4 && !defined(__DOXYGEN__)

+extern ICUDriver ICUD4;

+#endif

+

+#if STM32_ICU_USE_TIM5 && !defined(__DOXYGEN__)

+extern ICUDriver ICUD5;

+#endif

+

 #ifdef __cplusplus

 extern "C" {

 #endif

@@ -217,8 +307,6 @@ extern "C" {
   void icu_lld_stop(ICUDriver *icup);

   void icu_lld_enable(ICUDriver *icup);

   void icu_lld_disable(ICUDriver *icup);

-  icucnt_t icu_lld_get_width(ICUDriver *icup);

-  icucnt_t icu_lld_get_period(ICUDriver *icup);

 #ifdef __cplusplus

 }

 #endif

diff --git a/os/hal/platforms/STM32/platform.mk b/os/hal/platforms/STM32/platform.mk
index 469b85c79..48e19ace6 100644
--- a/os/hal/platforms/STM32/platform.mk
+++ b/os/hal/platforms/STM32/platform.mk
@@ -3,6 +3,7 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32/hal_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/adc_lld.c \

               ${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \

               ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \

+              ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \

               ${CHIBIOS}/os/hal/platforms/STM32/pal_lld.c \

               ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \

               ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \

diff --git a/os/hal/platforms/STM32/pwm_lld.c b/os/hal/platforms/STM32/pwm_lld.c
index ac41edbfd..eaf83bd90 100644
--- a/os/hal/platforms/STM32/pwm_lld.c
+++ b/os/hal/platforms/STM32/pwm_lld.c
@@ -48,40 +48,40 @@
 /*===========================================================================*/

 

 /**

- * @brief   PWM1 driver identifier.

- * @note    The driver PWM1 allocates the complex timer TIM1 when enabled.

+ * @brief   PWMD1 driver identifier.

+ * @note    The driver PWMD1 allocates the complex timer TIM1 when enabled.

  */

 #if STM32_PWM_USE_TIM1 || defined(__DOXYGEN__)

 PWMDriver PWMD1;

 #endif

 

 /**

- * @brief   PWM2 driver identifier.

- * @note    The driver PWM2 allocates the timer TIM2 when enabled.

+ * @brief   PWMD2 driver identifier.

+ * @note    The driver PWMD2 allocates the timer TIM2 when enabled.

  */

 #if STM32_PWM_USE_TIM2 || defined(__DOXYGEN__)

 PWMDriver PWMD2;

 #endif

 

 /**

- * @brief   PWM3 driver identifier.

- * @note    The driver PWM3 allocates the timer TIM3 when enabled.

+ * @brief   PWMD3 driver identifier.

+ * @note    The driver PWMD3 allocates the timer TIM3 when enabled.

  */

 #if STM32_PWM_USE_TIM3 || defined(__DOXYGEN__)

 PWMDriver PWMD3;

 #endif

 

 /**

- * @brief   PWM4 driver identifier.

- * @note    The driver PWM4 allocates the timer TIM4 when enabled.

+ * @brief   PWMD4 driver identifier.

+ * @note    The driver PWMD4 allocates the timer TIM4 when enabled.

  */

 #if STM32_PWM_USE_TIM4 || defined(__DOXYGEN__)

 PWMDriver PWMD4;

 #endif

 

 /**

- * @brief   PWM5 driver identifier.

- * @note    The driver PWM5 allocates the timer TIM5 when enabled.

+ * @brief   PWMD5 driver identifier.

+ * @note    The driver PWMD5 allocates the timer TIM5 when enabled.

  */

 #if STM32_PWM_USE_TIM5 || defined(__DOXYGEN__)

 PWMDriver PWMD5;

diff --git a/os/hal/platforms/STM32/pwm_lld.h b/os/hal/platforms/STM32/pwm_lld.h
index 9e251eb78..8c15a3c6f 100644
--- a/os/hal/platforms/STM32/pwm_lld.h
+++ b/os/hal/platforms/STM32/pwm_lld.h
@@ -45,8 +45,8 @@
 /*===========================================================================*/

 

 /**

- * @brief   PWM1 driver enable switch.

- * @details If set to @p TRUE the support for PWM1 is included.

+ * @brief   PWMD1 driver enable switch.

+ * @details If set to @p TRUE the support for PWMD1 is included.

  * @note    The default is @p TRUE.

  */

 #if !defined(STM32_PWM_USE_TIM1) || defined(__DOXYGEN__)

@@ -54,8 +54,8 @@
 #endif

 

 /**

- * @brief   PWM2 driver enable switch.

- * @details If set to @p TRUE the support for PWM2 is included.

+ * @brief   PWMD2 driver enable switch.

+ * @details If set to @p TRUE the support for PWMD2 is included.

  * @note    The default is @p TRUE.

  */

 #if !defined(STM32_PWM_USE_TIM2) || defined(__DOXYGEN__)

@@ -63,8 +63,8 @@
 #endif

 

 /**

- * @brief   PWM3 driver enable switch.

- * @details If set to @p TRUE the support for PWM3 is included.

+ * @brief   PWMD3 driver enable switch.

+ * @details If set to @p TRUE the support for PWMD3 is included.

  * @note    The default is @p TRUE.

  */

 #if !defined(STM32_PWM_USE_TIM3) || defined(__DOXYGEN__)

@@ -72,8 +72,8 @@
 #endif

 

 /**

- * @brief   PWM4 driver enable switch.

- * @details If set to @p TRUE the support for PWM4 is included.

+ * @brief   PWMD4 driver enable switch.

+ * @details If set to @p TRUE the support for PWMD4 is included.

  * @note    The default is @p TRUE.

  */

 #if !defined(STM32_PWM_USE_TIM4) || defined(__DOXYGEN__)

@@ -81,8 +81,8 @@
 #endif

 

 /**

- * @brief   PWM5 driver enable switch.

- * @details If set to @p TRUE the support for PWM5 is included.

+ * @brief   PWMD5 driver enable switch.

+ * @details If set to @p TRUE the support for PWMD5 is included.

  * @note    The default is @p TRUE.

  */

 #if !defined(STM32_PWM_USE_TIM5) || defined(__DOXYGEN__)

@@ -90,35 +90,35 @@
 #endif

 

 /**

- * @brief   PWM1 interrupt priority level setting.

+ * @brief   PWMD1 interrupt priority level setting.

  */

 #if !defined(STM32_PWM_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__)

 #define STM32_PWM_TIM1_IRQ_PRIORITY         7

 #endif

 

 /**

- * @brief   PWM2 interrupt priority level setting.

+ * @brief   PWMD2 interrupt priority level setting.

  */

 #if !defined(STM32_PWM_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__)

 #define STM32_PWM_TIM2_IRQ_PRIORITY         7

 #endif

 

 /**

- * @brief   PWM3 interrupt priority level setting.

+ * @brief   PWMD3 interrupt priority level setting.

  */

 #if !defined(STM32_PWM_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__)

 #define STM32_PWM_TIM3_IRQ_PRIORITY         7

 #endif

 

 /**

- * @brief   PWM4 interrupt priority level setting.

+ * @brief   PWMD4 interrupt priority level setting.

  */

 #if !defined(STM32_PWM_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__)

 #define STM32_PWM_TIM4_IRQ_PRIORITY         7

 #endif

 

 /**

- * @brief   PWM5 interrupt priority level setting.

+ * @brief   PWMD5 interrupt priority level setting.

  */

 #if !defined(STM32_PWM_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__)

 #define STM32_PWM_TIM5_IRQ_PRIORITY         7

diff --git a/os/hal/platforms/STM32/usb_lld.h b/os/hal/platforms/STM32/usb_lld.h
index 8cbbc8d6e..9b5e9dad2 100644
--- a/os/hal/platforms/STM32/usb_lld.h
+++ b/os/hal/platforms/STM32/usb_lld.h
@@ -290,6 +290,9 @@ struct USBDriver {
    * @brief   Current USB device configuration.

    */

   uint8_t                       configuration;

+#if defined(USB_DRIVER_EXT_FIELDS)

+  USB_DRIVER_EXT_FIELDS

+#endif

   /* End of the mandatory fields.*/

   /**

    * @brief   Pointer to the next address in the packet memory.

diff --git a/os/hal/templates/gpt_lld.h b/os/hal/templates/gpt_lld.h
index fa1e7e478..4053c9b7a 100644
--- a/os/hal/templates/gpt_lld.h
+++ b/os/hal/templates/gpt_lld.h
@@ -100,6 +100,9 @@ struct GPTDriver {
    * @brief Current configuration data.

    */

   const GPTConfig           *config;

+#if defined(GPT_DRIVER_EXT_FIELDS)

+  GPT_DRIVER_EXT_FIELDS

+#endif

   /* End of the mandatory fields.*/

 };

 

diff --git a/os/hal/templates/icu_lld.h b/os/hal/templates/icu_lld.h
index b0debb2b9..68ec93df6 100644
--- a/os/hal/templates/icu_lld.h
+++ b/os/hal/templates/icu_lld.h
@@ -104,6 +104,9 @@ struct ICUDriver {
    * @brief Current configuration data.

    */

   const ICUConfig           *config;

+#if defined(ICU_DRIVER_EXT_FIELDS)

+  ICU_DRIVER_EXT_FIELDS

+#endif

   /* End of the mandatory fields.*/

 };

 

diff --git a/os/hal/templates/usb_lld.h b/os/hal/templates/usb_lld.h
index 225f3ab9f..5a41c1c05 100644
--- a/os/hal/templates/usb_lld.h
+++ b/os/hal/templates/usb_lld.h
@@ -212,6 +212,9 @@ struct USBDriver {
    * @brief   Current USB device configuration.

    */

   uint8_t                       configuration;

+#if defined(USB_DRIVER_EXT_FIELDS)

+  USB_DRIVER_EXT_FIELDS

+#endif

   /* End of the mandatory fields.*/

 };

 

diff --git a/os/kernel/include/chdebug.h b/os/kernel/include/chdebug.h
index 5d6b455fe..471da5532 100644
--- a/os/kernel/include/chdebug.h
+++ b/os/kernel/include/chdebug.h
@@ -151,7 +151,7 @@ extern "C" {
 #endif

 #if CH_DBG_ENABLE_TRACE || defined(__DOXYGEN__)

   extern TraceBuffer trace_buffer;

-  void trace_init(void);

+  void _trace_init(void);

   void chDbgTrace(Thread *otp);

 #endif

 #if CH_DBG_ENABLE_ASSERTS || CH_DBG_ENABLE_CHECKS || CH_DBG_ENABLE_STACK_CHECK

diff --git a/os/kernel/include/chheap.h b/os/kernel/include/chheap.h
index ed5fa252a..eb642cd18 100644
--- a/os/kernel/include/chheap.h
+++ b/os/kernel/include/chheap.h
@@ -75,7 +75,7 @@ struct memory_heap {
 #ifdef __cplusplus

 extern "C" {

 #endif

-  void heap_init(void);

+  void _heap_init(void);

   void chHeapInit(MemoryHeap *heapp, void *buf, size_t size);

   void *chHeapAlloc(MemoryHeap *heapp, size_t size);

   void chHeapFree(void *p);

diff --git a/os/kernel/include/chmemcore.h b/os/kernel/include/chmemcore.h
index bc0654a6d..cf608c4e8 100644
--- a/os/kernel/include/chmemcore.h
+++ b/os/kernel/include/chmemcore.h
@@ -67,7 +67,7 @@ typedef void *(*memgetfunc_t)(size_t size);
 #ifdef __cplusplus

 extern "C" {

 #endif

-  void core_init(void);

+  void _core_init(void);

   void *chCoreAlloc(size_t size);

   void *chCoreAllocI(size_t size);

   size_t chCoreStatus(void);

diff --git a/os/kernel/include/chschd.h b/os/kernel/include/chschd.h
index 5dda6d00a..1cd8e0664 100644
--- a/os/kernel/include/chschd.h
+++ b/os/kernel/include/chschd.h
@@ -127,7 +127,7 @@ register Thread *currp asm(CH_CURRP_REGISTER_CACHE);
 #ifdef __cplusplus

 extern "C" {

 #endif

-  void scheduler_init(void);

+  void _scheduler_init(void);

 #if !defined(PORT_OPTIMIZED_READYI)

   Thread *chSchReadyI(Thread *tp);

 #endif

diff --git a/os/kernel/include/chvt.h b/os/kernel/include/chvt.h
index 9203b974d..e75e966d5 100644
--- a/os/kernel/include/chvt.h
+++ b/os/kernel/include/chvt.h
@@ -121,7 +121,7 @@ extern VTList vtlist;
 #ifdef __cplusplus

 extern "C" {

 #endif

-  void vt_init(void);

+  void _vt_init(void);

   void chVTSetI(VirtualTimer *vtp, systime_t time, vtfunc_t vtfunc, void *par);

   void chVTResetI(VirtualTimer *vtp);

   bool_t chTimeIsWithin(systime_t start, systime_t end);

diff --git a/os/kernel/src/chdebug.c b/os/kernel/src/chdebug.c
index be98cd40b..3c3c34c70 100644
--- a/os/kernel/src/chdebug.c
+++ b/os/kernel/src/chdebug.c
@@ -46,7 +46,7 @@ TraceBuffer trace_buffer;
  * @brief   Trace circular buffer subsystem initialization.

  * @note    Internal use only.

  */

-void trace_init(void) {

+void _trace_init(void) {

 

   trace_buffer.tb_size = TRACE_BUFFER_SIZE;

   trace_buffer.tb_ptr = &trace_buffer.tb_buffer[0];

diff --git a/os/kernel/src/chheap.c b/os/kernel/src/chheap.c
index a04646bcf..bcfca9b77 100644
--- a/os/kernel/src/chheap.c
+++ b/os/kernel/src/chheap.c
@@ -65,7 +65,7 @@ static MemoryHeap default_heap;
  *

  * @notapi

  */

-void heap_init(void) {

+void _heap_init(void) {

   default_heap.h_provider = chCoreAlloc;

   default_heap.h_free.h.u.next = (union heap_header *)NULL;

   default_heap.h_free.h.size = 0;

diff --git a/os/kernel/src/chmemcore.c b/os/kernel/src/chmemcore.c
index d66ef5f1c..311d170c5 100644
--- a/os/kernel/src/chmemcore.c
+++ b/os/kernel/src/chmemcore.c
@@ -56,7 +56,7 @@ static uint8_t *endmem;
  *

  * @notapi

  */

-void core_init(void) {

+void _core_init(void) {

 #if CH_MEMCORE_SIZE == 0

   extern uint8_t __heap_base__[];

   extern uint8_t __heap_end__[];

diff --git a/os/kernel/src/chschd.c b/os/kernel/src/chschd.c
index 210dbfdc1..54e7918b1 100644
--- a/os/kernel/src/chschd.c
+++ b/os/kernel/src/chschd.c
@@ -45,7 +45,7 @@ ReadyList rlist;
  *

  * @notapi

  */

-void scheduler_init(void) {

+void _scheduler_init(void) {

 

   queue_init(&rlist.r_queue);

   rlist.r_prio = NOPRIO;

diff --git a/os/kernel/src/chsys.c b/os/kernel/src/chsys.c
index db6521b87..29f4bdc7e 100644
--- a/os/kernel/src/chsys.c
+++ b/os/kernel/src/chsys.c
@@ -76,16 +76,16 @@ void chSysInit(void) {
   static Thread mainthread;

 

   port_init();

-  scheduler_init();

-  vt_init();

+  _scheduler_init();

+  _vt_init();

 #if CH_USE_MEMCORE

-  core_init();

+  _core_init();

 #endif

 #if CH_USE_HEAP

-  heap_init();

+  _heap_init();

 #endif

 #if CH_DBG_ENABLE_TRACE

-  trace_init();

+  _trace_init();

 #endif

 

   /* Now this instructions flow becomes the main thread.*/

diff --git a/os/kernel/src/chvt.c b/os/kernel/src/chvt.c
index b98396a3a..4674c728e 100644
--- a/os/kernel/src/chvt.c
+++ b/os/kernel/src/chvt.c
@@ -40,7 +40,7 @@ VTList vtlist;
  *

  * @notapi

  */

-void vt_init(void) {

+void _vt_init(void) {

 

   vtlist.vt_next = vtlist.vt_prev = (void *)&vtlist;

   vtlist.vt_time = (systime_t)-1;