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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-12-10 14:19:45 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-12-10 14:19:45 +0000 |
| commit | f33a1bf19353699427726edc6004454484ca7b70 (patch) | |
| tree | d6e2853b62987e85e31dcfe12a37a3c345797893 /os | |
| parent | 3842ff446c4012d26cf02009c89e1c0be426dbbf (diff) | |
| download | ChibiOS-f33a1bf19353699427726edc6004454484ca7b70.tar.gz ChibiOS-f33a1bf19353699427726edc6004454484ca7b70.tar.bz2 ChibiOS-f33a1bf19353699427726edc6004454484ca7b70.zip | |
Fixed bug #680.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8573 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
| -rw-r--r-- | os/hal/ports/STM32/STM32F3xx/adc_lld.c | 3 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32L4xx/stm32_rcc.h | 13 |
2 files changed, 8 insertions, 8 deletions
diff --git a/os/hal/ports/STM32/STM32F3xx/adc_lld.c b/os/hal/ports/STM32/STM32F3xx/adc_lld.c index 35f79b20a..b2685d37c 100644 --- a/os/hal/ports/STM32/STM32F3xx/adc_lld.c +++ b/os/hal/ports/STM32/STM32F3xx/adc_lld.c @@ -358,7 +358,7 @@ void adc_lld_init(void) { #endif
ADCD3.dmastp = STM32_DMA2_STREAM5;
ADCD3.dmamode = ADC_DMA_SIZE |
- STM32_DMA_CR_PL(STM32_ADC_ADC12_DMA_PRIORITY) |
+ STM32_DMA_CR_PL(STM32_ADC_ADC34_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
@@ -419,7 +419,6 @@ void adc_lld_start(ADCDriver *adcp) { /* Clock source setting.*/
adcp->adcc->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
-
/* Differential channels setting.*/
#if STM32_ADC_DUAL_MODE
adcp->adcm->DIFSEL = adcp->config->difsel;
diff --git a/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h b/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h index c45341540..4982b03df 100644 --- a/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h @@ -267,34 +267,35 @@ }
/** @} */
+
/**
* @name ADC peripherals specific RCC operations
* @{
*/
/**
- * @brief Enables ADC peripherals clock.
+ * @brief Enables the ADC1/ADC2/ADC3 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableADC(lp) rccEnableAHB2(RCC_AHB2ENR_ADCEN, lp)
+#define rccEnableADC123(lp) rccEnableAHB2(RCC_AHB2ENR_ADCEN, lp)
/**
- * @brief Disables ADC peripherals clock.
+ * @brief Disables the ADC1/ADC2/ADC3 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableADC(lp) rccDisableAHB2(RCC_AHB2ENR_ADCEN, lp)
+#define rccDisableADC123(lp) rccDisableAHB2(RCC_AHB2ENR_ADCEN, lp)
/**
- * @brief Resets ADC peripherals.
+ * @brief Resets the ADC1/ADC2/ADC3 peripheral.
*
* @api
*/
-#define rccResetADC() rccResetAHB2(RCC_AHB2RSTR_ADCRST)
+#define rccResetADC123() rccResetAHB2(RCC_AHB2RSTR_ADCRST)
/** @} */
/**
|