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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-08-07 09:34:04 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-08-07 09:34:04 +0000 |
| commit | ee22351c3f3f376376a10d6e4d69ba288b675559 (patch) | |
| tree | b402e233bf7d1202fd34e18734ec3d0852f28214 /os | |
| parent | 4e935e11dd3d8adaf01db8c5a1a0e242343bd496 (diff) | |
| download | ChibiOS-ee22351c3f3f376376a10d6e4d69ba288b675559.tar.gz ChibiOS-ee22351c3f3f376376a10d6e4d69ba288b675559.tar.bz2 ChibiOS-ee22351c3f3f376376a10d6e4d69ba288b675559.zip | |
Fixed bug #628.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8175 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
| -rw-r--r-- | os/hal/ports/STM32/STM32F0xx/hal_lld.c | 7 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F0xx/hal_lld.h | 3 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F7xx/hal_lld.c | 20 |
3 files changed, 25 insertions, 5 deletions
diff --git a/os/hal/ports/STM32/STM32F0xx/hal_lld.c b/os/hal/ports/STM32/STM32F0xx/hal_lld.c index bb230edcd..2250a031a 100644 --- a/os/hal/ports/STM32/STM32F0xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32F0xx/hal_lld.c @@ -191,8 +191,11 @@ void stm32_clock_init(void) { RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLSRC |
STM32_PPRE | STM32_HPRE;
RCC->CFGR2 = STM32_PREDIV;
- RCC->CFGR3 = STM32_USBSW | STM32_CECSW |
- STM32_I2C1SW | STM32_USART1SW;
+#if STM32_CECSW == STM32_CECSW_OFF
+ RCC->CFGR3 = STM32_USBSW | STM32_I2C1SW | STM32_USART1SW;
+#else
+ RCC->CFGR3 = STM32_USBSW | STM32_CECSW | STM32_I2C1SW | STM32_USART1SW;
+#endif
#if STM32_ACTIVATE_PLL
/* PLL activation.*/
diff --git a/os/hal/ports/STM32/STM32F0xx/hal_lld.h b/os/hal/ports/STM32/STM32F0xx/hal_lld.h index d376efe95..a2f8662de 100644 --- a/os/hal/ports/STM32/STM32F0xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F0xx/hal_lld.h @@ -252,6 +252,7 @@ #define STM32_CECSW_MASK (1 << 6) /**< CEC clock source mask. */
#define STM32_CECSW_HSI (0 << 6) /**< CEC clock is HSI/244. */
#define STM32_CECSW_LSE (1 << 6) /**< CEC clock is LSE. */
+#define STM32_CECSW_OFF 0xFFFFFFFF /**< CEC clock is not required. */
#define STM32_USBSW_MASK (1 << 7) /**< USB clock source mask. */
#define STM32_USBSW_HSI48 (0 << 7) /**< USB clock is HSI48. */
#define STM32_USBSW_PCLK (1 << 7) /**< USB clock is PCLK. */
@@ -767,6 +768,8 @@ #define STM32_CECCLK STM32_HSICLK
#elif STM32_CECSW == STM32_CECSW_LSE
#define STM32_CECCLK STM32_LSECLK
+#elif STM32_CECSW == STM32_CECSW_OFF
+#define STM32_CECCLK 0
#else
#error "invalid source selected for CEC clock"
#endif
diff --git a/os/hal/ports/STM32/STM32F7xx/hal_lld.c b/os/hal/ports/STM32/STM32F7xx/hal_lld.c index 06c29ad2b..5357f1629 100644 --- a/os/hal/ports/STM32/STM32F7xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32F7xx/hal_lld.c @@ -230,9 +230,7 @@ void stm32_clock_init(void) { /* PLLSAI activation.*/
RCC->PLLSAICFGR = STM32_PLLSAIR | STM32_PLLSAIQ | STM32_PLLSAIP |
STM32_PLLSAIN;
- RCC->DCKCFGR1 = /*STM32_TIMPRE | */STM32_SAI2SEL | STM32_SAI1SEL |
- STM32_PLLSAIDIVR;
- RCC->CR |= RCC_CR_PLLSAION;
+ RCC->CR |= RCC_CR_PLLSAION;
/* Waiting for PLL lock.*/
while (!(RCC->CR & RCC_CR_PLLSAIRDY))
@@ -244,6 +242,22 @@ void stm32_clock_init(void) { STM32_MCO1SEL | STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 |
STM32_HPRE;
+ /* DCKCFGR1 register initialization, note, must take care of the _OFF
+ pseudo settings.*/
+ {
+ uint32_t dckcfgr1 = 0;
+#if STM32_SAI2SEL != STM32_SAI2SEL_OFF
+ dckcfgr1 |= STM32_SAI2SEL;
+#endif
+#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
+ dckcfgr1 |= STM32_SAI1SEL;
+#endif
+#if STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF
+ dckcfgr1 |= STM32_PLLSAIDIVR;
+#endif
+ RCC->DCKCFGR1 = dckcfgr1;
+ }
+
/* Peripheral clock sources.*/
RCC->DCKCFGR2 = STM32_SDMMCSEL | STM32_CK48MSEL | STM32_CECSEL |
STM32_LPTIM1SEL | STM32_I2C4SEL | STM32_I2C4SEL |
|