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authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2015-09-01 08:58:14 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2015-09-01 08:58:14 +0000
commitebde485b9efa736792b0c436e7a8a31c47eeb4b6 (patch)
tree52be73399b9f09deede5902ba12a3c071508b07e /os
parentc83eac2f289ffe50b7910c383e081fd461e688d1 (diff)
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Fixed DWT unlock on CM7 ports.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8264 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
-rw-r--r--os/nil/ports/ARMCMx/nilcore_v7m.h3
-rw-r--r--os/rt/ports/ARMCMx/chcore_v7m.h5
2 files changed, 7 insertions, 1 deletions
diff --git a/os/nil/ports/ARMCMx/nilcore_v7m.h b/os/nil/ports/ARMCMx/nilcore_v7m.h
index 4ae692d7d..41c038fcc 100644
--- a/os/nil/ports/ARMCMx/nilcore_v7m.h
+++ b/os/nil/ports/ARMCMx/nilcore_v7m.h
@@ -389,6 +389,9 @@ static inline void port_init(void) {
/* DWT cycle counter enable.*/
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+#if CORTEX_MODEL == 7
+ DWT->LAR = 0xC5ACCE55;
+#endif
DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
/* Initialization of the system vectors used by the port.*/
diff --git a/os/rt/ports/ARMCMx/chcore_v7m.h b/os/rt/ports/ARMCMx/chcore_v7m.h
index 7898e4e74..ab6cf28b9 100644
--- a/os/rt/ports/ARMCMx/chcore_v7m.h
+++ b/os/rt/ports/ARMCMx/chcore_v7m.h
@@ -388,8 +388,11 @@ static inline void port_init(void) {
/* Initializing priority grouping.*/
NVIC_SetPriorityGrouping(CORTEX_PRIGROUP_INIT);
- /* DWT cycle counter enable.*/
+ /* DWT cycle counter enable, note, the M7 requires DWT unlocking.*/
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+#if CORTEX_MODEL == 7
+ DWT->LAR = 0xC5ACCE55;
+#endif
DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
/* Initialization of the system vectors used by the port.*/