git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6459 35acf78f-673a-0410-8e92-d51de3d6d3f4

2 files changed, 51 insertions, 13 deletions

diff --git a/os/hal/ports/STM32/USARTv1/uart_lld.c b/os/hal/ports/STM32/USARTv1/uart_lld.c
index 8f1bcfb13..b1856366c 100644
--- a/os/hal/ports/STM32/USARTv1/uart_lld.c
+++ b/os/hal/ports/STM32/USARTv1/uart_lld.c
@@ -78,6 +78,14 @@
   STM32_DMA_GETCHANNEL(STM32_UART_USART6_TX_DMA_STREAM,                     \

                        STM32_USART6_TX_DMA_CHN)

 

+#define STM32_UART45_CR2_CHECK_MASK                                         \

+  (USART_CR2_STOP_0 | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA |   \

+   USART_CR2_LBCL)

+

+#define STM32_UART45_CR3_CHECK_MASK                                         \

+  (USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_SCEN |     \

+   USART_CR3_NACK)

+

 /*===========================================================================*/

 /* Driver exported variables.                                                */

 /*===========================================================================*/

@@ -571,6 +579,12 @@ void uart_lld_start(UARTDriver *uartp) {
 #if STM32_UART_USE_UART4

     if (&UARTD4 == uartp) {

       bool b;

+

+      chDbgAssert((uartp->config->cr2 & STM32_UART45_CR2_CHECK_MASK) == 0,

+                  "specified invalid bits in UART4 CR2 register settings");

+      chDbgAssert((uartp->config->cr3 & STM32_UART45_CR3_CHECK_MASK) == 0,

+                  "specified invalid bits in UART4 CR3 register settings");

+

       b = dmaStreamAllocate(uartp->dmarx,

                             STM32_UART_UART4_IRQ_PRIORITY,

                             (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,

@@ -591,6 +605,12 @@ void uart_lld_start(UARTDriver *uartp) {
 #if STM32_UART_USE_UART5

     if (&UARTD5 == uartp) {

       bool b;

+

+      chDbgAssert((uartp->config->cr2 & STM32_UART45_CR2_CHECK_MASK) == 0,

+                  "specified invalid bits in UART5 CR2 register settings");

+      chDbgAssert((uartp->config->cr3 & STM32_UART45_CR3_CHECK_MASK) == 0,

+                  "specified invalid bits in UART5 CR3 register settings");

+

       b = dmaStreamAllocate(uartp->dmarx,

                             STM32_UART_UART5_IRQ_PRIORITY,

                             (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,

diff --git a/os/hal/ports/STM32/USARTv1/uart_lld.h b/os/hal/ports/STM32/USARTv1/uart_lld.h
index 12ecd0923..b5992b340 100644
--- a/os/hal/ports/STM32/USARTv1/uart_lld.h
+++ b/os/hal/ports/STM32/USARTv1/uart_lld.h
@@ -80,7 +80,7 @@
  * @details If set to @p TRUE the support for UART5 is included.

  * @note    The default is @p FALSE.

  */

-#if !defined(STM32_UART_USE_UART4) || defined(__DOXYGEN__)

+#if !defined(STM32_UART_USE_UART5) || defined(__DOXYGEN__)

 #define STM32_UART_USE_UART5                FALSE

 #endif

 

@@ -222,24 +222,24 @@
 #endif

 

 #if STM32_UART_USE_UART4 

-  #if !STM32_HAS_UART4

-  #error "UART4 not present in the selected device"

-  #endif

+#if !STM32_HAS_UART4

+#error "UART4 not present in the selected device"

+#endif

 

-  #if !defined(STM32F2XX) && !defined(STM32F4XX)

-  #error "UART4 DMA access not supported in this platform"

-  #endif

+#if !defined(STM32F2XX) && !defined(STM32F4XX)

+#error "UART4 DMA access not supported in this platform"

 #endif

+#endif /* STM32_UART_USE_UART4 */

 

 #if STM32_UART_USE_UART5

-  #if !STM32_HAS_UART5

-  #error "UART5 not present in the selected device"

-  #endif

+#if !STM32_HAS_UART5

+#error "UART5 not present in the selected device"

+#endif

 

-  #if !defined(STM32F2XX) && !defined(STM32F4XX)

-  #error "UART5 DMA access not supported in this platform"

-  #endif

+#if !defined(STM32F2XX) && !defined(STM32F4XX)

+#error "UART5 DMA access not supported in this platform"

 #endif

+#endif /* STM32_UART_USE_UART5 */

 

 #if STM32_UART_USE_USART6 && !STM32_HAS_USART6

 #error "USART6 not present in the selected device"

@@ -383,18 +383,36 @@
 #endif

 

 #if STM32_UART_USE_UART4 &&                                                 \

+    !STM32_DMA_IS_VALID_ID(STM32_UART_UART4_RX_DMA_STREAM,                  \

+                           STM32_UART4_RX_DMA_MSK)

+#error "invalid DMA stream associated to UART4 RX"

+#endif

+

+#if STM32_UART_USE_UART4 &&                                                 \

     !STM32_DMA_IS_VALID_ID(STM32_UART_UART4_TX_DMA_STREAM,                  \

                            STM32_UART4_TX_DMA_MSK)

 #error "invalid DMA stream associated to UART4 TX"

 #endif

 

 #if STM32_UART_USE_UART5 &&                                                 \

+    !STM32_DMA_IS_VALID_ID(STM32_UART_UART5_RX_DMA_STREAM,                  \

+                           STM32_UART5_RX_DMA_MSK)

+#error "invalid DMA stream associated to UART5 RX"

+#endif

+

+#if STM32_UART_USE_UART5 &&                                                 \

     !STM32_DMA_IS_VALID_ID(STM32_UART_UART5_TX_DMA_STREAM,                  \

                            STM32_UART5_TX_DMA_MSK)

 #error "invalid DMA stream associated to UART5 TX"

 #endif

 

 #if STM32_UART_USE_USART6 &&                                                \

+    !STM32_DMA_IS_VALID_ID(STM32_UART_USART6_RX_DMA_STREAM,                 \

+                           STM32_USART6_RX_DMA_MSK)

+#error "invalid DMA stream associated to USART6 RX"

+#endif

+

+#if STM32_UART_USE_USART6 &&                                                \

     !STM32_DMA_IS_VALID_ID(STM32_UART_USART6_TX_DMA_STREAM,                 \

                            STM32_USART6_TX_DMA_MSK)

 #error "invalid DMA stream associated to USART6 TX"