git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2378 35acf78f-673a-0410-8e92-d51de3d6d3f4

12 files changed, 1511 insertions, 0 deletions

diff --git a/os/ports/GCC/ARM/AT91SAM7/vectors.s b/os/ports/GCC/ARM/AT91SAM7/vectors.s
new file mode 100644
index 000000000..ee0c01a19
--- /dev/null
+++ b/os/ports/GCC/ARM/AT91SAM7/vectors.s
@@ -0,0 +1,74 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+.section vectors

+.code 32

+.balign 4

+/*

+ * System entry points.

+ */

+_start:

+        ldr     pc, _reset

+        ldr     pc, _undefined

+        ldr     pc, _swi

+        ldr     pc, _prefetch

+        ldr     pc, _abort

+        nop

+        ldr     pc, [pc,#-0xF20]        /* AIC - AIC_IVR */

+        ldr     pc, [pc,#-0xF20]        /* AIC - AIC_FVR */

+

+_reset:

+        .word   ResetHandler            /* In crt0.s */

+_undefined:

+        .word   UndHandler

+_swi:

+        .word   SwiHandler

+_prefetch:

+        .word   PrefetchHandler

+_abort:

+        .word   AbortHandler

+        .word   0

+        .word   0

+        .word   0

+

+.text

+.code 32

+.balign 4

+

+/*

+ * Default exceptions handlers. The handlers are declared weak in order to be

+ * replaced by the real handling code. Everything is defaulted to an infinite

+ * loop.

+ */

+.weak UndHandler

+UndHandler:

+

+.weak SwiHandler

+SwiHandler:

+

+.weak PrefetchHandler

+PrefetchHandler:

+

+.weak AbortHandler

+AbortHandler:

+

+.weak FiqHandler

+FiqHandler:

+

+.loop:  b       .loop

diff --git a/os/ports/GCC/ARM/AT91SAM7/wfi.h b/os/ports/GCC/ARM/AT91SAM7/wfi.h
new file mode 100644
index 000000000..76390d407
--- /dev/null
+++ b/os/ports/GCC/ARM/AT91SAM7/wfi.h
@@ -0,0 +1,35 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+#ifndef _WFI_H_

+#define _WFI_H_

+

+#include "board.h"

+

+#ifndef port_wait_for_interrupt

+#if ENABLE_WFI_IDLE != 0

+#define port_wait_for_interrupt() {                                     \

+  AT91C_BASE_SYS->PMC_SCDR = AT91C_PMC_PCK;                             \

+}

+#else

+#define port_wait_for_interrupt()

+#endif

+#endif

+

+#endif /* _WFI_H_ */

diff --git a/os/ports/GCC/ARM/LPC214x/vectors.s b/os/ports/GCC/ARM/LPC214x/vectors.s
new file mode 100644
index 000000000..9f904ead9
--- /dev/null
+++ b/os/ports/GCC/ARM/LPC214x/vectors.s
@@ -0,0 +1,71 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+.section vectors

+.code 32

+.balign 4

+/*

+ * System entry points.

+ */

+_start:

+        ldr     pc, _reset

+        ldr     pc, _undefined

+        ldr     pc, _swi

+        ldr     pc, _prefetch

+        ldr     pc, _abort

+        nop

+        ldr     pc, [pc,#-0xFF0]        /* VIC - IRQ Vector Register */

+        ldr     pc, _fiq

+

+_reset:

+        .word   ResetHandler            /* In crt0.s */

+_undefined:

+        .word   UndHandler

+_swi:

+        .word   SwiHandler

+_prefetch:

+        .word   PrefetchHandler

+_abort:

+        .word   AbortHandler

+_fiq:

+        .word   FiqHandler

+        .word   0

+        .word   0

+

+/*

+ * Default exceptions handlers. The handlers are declared weak in order to be

+ * replaced by the real handling code. Everything is defaulted to an infinite

+ * loop.

+ */

+.weak UndHandler

+UndHandler:

+

+.weak SwiHandler

+SwiHandler:

+

+.weak PrefetchHandler

+PrefetchHandler:

+

+.weak AbortHandler

+AbortHandler:

+

+.weak FiqHandler

+FiqHandler:

+

+.loop:  b       .loop

diff --git a/os/ports/GCC/ARM/LPC214x/wfi.h b/os/ports/GCC/ARM/LPC214x/wfi.h
new file mode 100644
index 000000000..1688c33f8
--- /dev/null
+++ b/os/ports/GCC/ARM/LPC214x/wfi.h
@@ -0,0 +1,35 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+#ifndef _WFI_H_

+#define _WFI_H_

+

+#include "lpc214x.h"

+

+#ifndef port_wait_for_interrupt

+#if ENABLE_WFI_IDLE != 0

+#define port_wait_for_interrupt() {                                     \

+  PCON = 1;                                                             \

+}

+#else

+#define port_wait_for_interrupt()

+#endif

+#endif

+

+#endif /* _WFI_H_ */

diff --git a/os/ports/GCC/ARM/chcore.c b/os/ports/GCC/ARM/chcore.c
new file mode 100644
index 000000000..51ed31fc3
--- /dev/null
+++ b/os/ports/GCC/ARM/chcore.c
@@ -0,0 +1,43 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/**

+ * @file    ARM7/chcore.c

+ * @brief   ARM7 architecture port code.

+ *

+ * @addtogroup ARM7_CORE

+ * @{

+ */

+

+#include "ch.h"

+

+/**

+ * Halts the system.

+ */

+#if !defined(__DOXYGEN__)

+__attribute__((weak))

+#endif

+void port_halt(void) {

+

+  port_disable();

+  while (TRUE) {

+  }

+}

+

+/** @} */

diff --git a/os/ports/GCC/ARM/chcore.h b/os/ports/GCC/ARM/chcore.h
new file mode 100644
index 000000000..cd88cf0cc
--- /dev/null
+++ b/os/ports/GCC/ARM/chcore.h
@@ -0,0 +1,384 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/**

+ * @file    ARM7/chcore.h

+ * @brief   ARM7 architecture port macros and structures.

+ *

+ * @addtogroup ARM7_CORE

+ * @{

+ */

+

+#ifndef _CHCORE_H_

+#define _CHCORE_H_

+

+/**

+ * @brief   If enabled allows the idle thread to enter a low power mode.

+ */

+#ifndef ENABLE_WFI_IDLE

+#define ENABLE_WFI_IDLE 0

+#endif

+#include <wfi.h>

+

+/**

+ * @brief   Macro defining the ARM7 architecture.

+ */

+#define CH_ARCHITECTURE_ARM7

+

+/**

+ * @brief   Name of the implemented architecture.

+ */

+#define CH_ARCHITECTURE_NAME "ARM"

+

+/**

+ * @brief   Name of the architecture variant (optional).

+ */

+#define CH_CORE_VARIANT_NAME "ARM7TDMI"

+

+/**

+ * @brief   32 bits stack and memory alignment enforcement.

+ */

+typedef uint32_t stkalign_t;

+

+/**

+ * @brief   Generic ARM register.

+ */

+typedef void *regarm_t;

+

+/**

+ * @brief   Interrupt saved context.

+ * @details This structure represents the stack frame saved during a

+ *          preemption-capable interrupt handler.

+ */

+struct extctx {

+  regarm_t      spsr_irq;

+  regarm_t      lr_irq;

+  regarm_t      r0;

+  regarm_t      r1;

+  regarm_t      r2;

+  regarm_t      r3;

+  regarm_t      r12;

+  regarm_t      lr_usr;

+};

+

+/**

+ * @brief   System saved context.

+ * @details This structure represents the inner stack frame during a context

+ *          switching.

+ */

+struct intctx {

+  regarm_t      r4;

+  regarm_t      r5;

+  regarm_t      r6;

+#ifndef CH_CURRP_REGISTER_CACHE

+  regarm_t      r7;

+#endif

+  regarm_t      r8;

+  regarm_t      r9;

+  regarm_t      r10;

+  regarm_t      r11;

+  regarm_t      lr;

+};

+

+/**

+ * @brief   Platform dependent part of the @p Thread structure.

+ * @details In this port the structure just holds a pointer to the @p intctx

+ *          structure representing the stack pointer at context switch time.

+ */

+struct context {

+  struct intctx *r13;

+};

+

+/**

+ * @brief   Platform dependent part of the @p chThdInit() API.

+ * @details This code usually setup the context switching frame represented

+ *          by an @p intctx structure.

+ */

+#define SETUP_CONTEXT(workspace, wsize, pf, arg) {                          \

+  tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace +                  \

+                                     wsize -                                \

+                                     sizeof(struct intctx));                \

+  tp->p_ctx.r13->r4 = pf;                                                   \

+  tp->p_ctx.r13->r5 = arg;                                                  \

+  tp->p_ctx.r13->lr = _port_thread_start;                                   \

+}

+

+/**

+ * @brief   Stack size for the system idle thread.

+ * @details This size depends on the idle thread implementation, usually

+ *          the idle thread should take no more space than those reserved

+ *          by @p INT_REQUIRED_STACK.

+ * @note    In this port it is set to 4 because the idle thread does have

+ *          a stack frame when compiling without optimizations.

+ */

+#ifndef IDLE_THREAD_STACK_SIZE

+#define IDLE_THREAD_STACK_SIZE      4

+#endif

+

+/**

+ * @brief   Per-thread stack overhead for interrupts servicing.

+ * @details This constant is used in the calculation of the correct working

+ *          area size.

+ *          This value can be zero on those architecture where there is a

+ *          separate interrupt stack and the stack space between @p intctx and

+ *          @p extctx is known to be zero.

+ * @note    In this port 0x10 is a safe value, it can be reduced after careful

+ *          analysis of the generated code.

+ */

+#ifndef INT_REQUIRED_STACK

+#define INT_REQUIRED_STACK          0x10

+#endif

+

+/**

+ * @brief   Enforces a correct alignment for a stack area size value.

+ */

+#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)

+

+/**

+ * @brief   Computes the thread working area global size.

+ */

+#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) +                         \

+                                   sizeof(struct intctx) +                  \

+                                   sizeof(struct extctx) +                  \

+                                  (n) + (INT_REQUIRED_STACK))

+

+/**

+ * @brief   Static working area allocation.

+ * @details This macro is used to allocate a static thread working area

+ *          aligned as both position and size.

+ */

+#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]

+

+/**

+ * @brief   IRQ prologue code.

+ * @details This macro must be inserted at the start of all IRQ handlers

+ *          enabled to invoke system APIs.

+ * @note    This macro has a different implementation depending if compiled in

+ *          ARM or THUMB mode.

+ * @note    The THUMB implementation starts with ARM code because interrupt

+ *          vectors are always invoked in ARM mode regardless the bit 0

+ *          value. The switch in THUMB mode is done in the function prologue so

+ *          it is transparent to the user code.

+ */

+#ifdef THUMB

+#define PORT_IRQ_PROLOGUE() {                                               \

+  asm volatile (".code 32                               \n\t"               \

+                "stmfd   sp!, {r0-r3, r12, lr}          \n\t"               \

+                "add     r0, pc, #1                     \n\t"               \

+                "bx      r0                             \n\t"               \

+                ".code 16" : : : "memory");                                 \

+}

+#else /* !THUMB */

+#define PORT_IRQ_PROLOGUE() {                                               \

+  asm volatile ("stmfd    sp!, {r0-r3, r12, lr}" : : : "memory");           \

+}

+#endif /* !THUMB */

+

+/**

+ * @brief   IRQ epilogue code.

+ * @details This macro must be inserted at the end of all IRQ handlers

+ *          enabled to invoke system APIs.

+ * @note    This macro has a different implementation depending if compiled in

+ *          ARM or THUMB mode.

+ */

+#ifdef THUMB

+#define PORT_IRQ_EPILOGUE() {                                               \

+  asm volatile ("ldr     r0, =_port_irq_common          \n\t"               \

+                "bx      r0" : : : "memory");                               \

+}

+#else /* !THUMB */

+#define PORT_IRQ_EPILOGUE() {                                               \

+  asm volatile ("b       _port_irq_common" : : : "memory");                 \

+}

+#endif /* !THUMB */

+

+/**

+ * @brief   IRQ handler function declaration.

+ * @note    @p id can be a function name or a vector number depending on the

+ *          port implementation.

+ */

+#define PORT_IRQ_HANDLER(id) __attribute__((naked)) void id(void)

+

+/**

+ * @brief   Fast IRQ handler function declaration.

+ * @note    @p id can be a function name or a vector number depending on the

+ *          port implementation.

+ */

+#define PORT_FAST_IRQ_HANDLER(id)                                           \

+  __attribute__((interrupt("FIQ"))) void id(void)

+

+/**

+ * @brief   Port-related initialization code.

+ * @note    This function is empty in this port.

+ */

+#define port_init()

+

+/**

+ * @brief   Kernel-lock action.

+ * @details Usually this function just disables interrupts but may perform

+ *          more actions.

+ * @note    In this port it disables the IRQ sources and keeps FIQ sources

+ *          enabled.

+ */

+#ifdef THUMB

+#define port_lock() {                                                       \

+  asm volatile ("bl     _port_lock_thumb" : : : "r3", "lr", "memory");      \

+}

+#else /* !THUMB */

+#define port_lock() asm volatile ("msr     CPSR_c, #0x9F" : : : "memory")

+#endif /* !THUMB */

+

+/**

+ * @brief   Kernel-unlock action.

+ * @details Usually this function just disables interrupts but may perform

+ *          more actions.

+ * @note    In this port it enables both the IRQ and FIQ sources.

+ */

+#ifdef THUMB

+#define port_unlock() {                                                     \

+  asm volatile ("bl     _port_unlock_thumb" : : : "r3", "lr", "memory");    \

+}

+#else /* !THUMB */

+#define port_unlock() asm volatile ("msr     CPSR_c, #0x1F" : : : "memory")

+#endif /* !THUMB */

+

+/**

+ * @brief   Kernel-lock action from an interrupt handler.

+ * @details This function is invoked before invoking I-class APIs from

+ *          interrupt handlers. The implementation is architecture dependent,

+ *          in its simplest form it is void.

+ * @note    Empty in this port.

+ */

+#define port_lock_from_isr()

+

+/**

+ * @brief   Kernel-unlock action from an interrupt handler.

+ * @details This function is invoked after invoking I-class APIs from interrupt

+ *          handlers. The implementation is architecture dependent, in its

+ *          simplest form it is void.

+ * @note    Empty in this port.

+ */

+#define port_unlock_from_isr()

+

+/**

+ * @brief   Disables all the interrupt sources.

+ * @note    Of course non maskable interrupt sources are not included.

+ * @note    In this port it disables both the IRQ and FIQ sources.

+ * @note    Implements a workaround for spurious interrupts taken from the NXP

+ *          LPC214x datasheet.

+ */

+#ifdef THUMB

+#define port_disable() {                                                    \

+  asm volatile ("bl     _port_disable_thumb" : : : "r3", "lr", "memory");   \

+}

+#else /* !THUMB */

+#define port_disable() {                                                    \

+  asm volatile ("mrs     r3, CPSR                       \n\t"               \

+                "orr     r3, #0x80                      \n\t"               \

+                "msr     CPSR_c, r3                     \n\t"               \

+                "orr     r3, #0x40                      \n\t"               \

+                "msr     CPSR_c, r3" : : : "r3", "memory");                 \

+}

+#endif /* !THUMB */

+

+/**

+ * @brief   Disables the interrupt sources below kernel-level priority.

+ * @note    Interrupt sources above kernel level remains enabled.

+ * @note    In this port it disables the IRQ sources and enables the

+ *          FIQ sources.

+ */

+#ifdef THUMB

+#define port_suspend() {                                                    \

+  asm volatile ("bl     _port_suspend_thumb" : : : "r3", "lr", "memory");   \

+}

+#else /* !THUMB */

+#define port_suspend() asm volatile ("msr     CPSR_c, #0x9F" : : : "memory")

+#endif /* !THUMB */

+

+/**

+ * @brief   Enables all the interrupt sources.

+ * @note    In this port it enables both the IRQ and FIQ sources.

+ */

+#ifdef THUMB

+#define port_enable() {                                                     \

+  asm volatile ("bl     _port_enable_thumb" : : : "r3", "lr", "memory");    \

+}

+#else /* !THUMB */

+#define port_enable() asm volatile ("msr     CPSR_c, #0x1F" : : : "memory")

+#endif /* !THUMB */

+

+/**

+ * @brief   Performs a context switch between two threads.

+ * @details This is the most critical code in any port, this function

+ *          is responsible for the context switch between 2 threads.

+ * @note    The implementation of this code affects <b>directly</b> the context

+ *          switch performance so optimize here as much as you can.

+ * @note    Implemented as inlined code for performance reasons.

+ *

+ * @param[in] ntp       the thread to be switched in

+ * @param[in] otp       the thread to be switched out

+ */

+#ifdef THUMB

+#if CH_DBG_ENABLE_STACK_CHECK

+#define port_switch(ntp, otp) {                                             \

+  register Thread *_ntp asm ("r0") = (ntp);                                 \

+  register Thread *_otp asm ("r1") = (otp);                                 \

+  register char *sp asm ("sp");                                             \

+  if (sp - sizeof(struct intctx) - sizeof(Thread) < (char *)_otp)           \

+    asm volatile ("mov     r0, #0                               \n\t"       \

+                  "ldr     r1, =chDbgPanic                      \n\t"       \

+                  "bx      r1");                                            \

+    _port_switch_thumb(_ntp, _otp);                                         \

+}

+#else /* !CH_DBG_ENABLE_STACK_CHECK */

+#define port_switch(ntp, otp) _port_switch_thumb(ntp, otp)

+#endif /* !CH_DBG_ENABLE_STACK_CHECK */

+#else /* !THUMB */

+#if CH_DBG_ENABLE_STACK_CHECK

+#define port_switch(ntp, otp) {                                             \

+  register Thread *_ntp asm ("r0") = (ntp);                                 \

+  register Thread *_otp asm ("r1") = (otp);                                 \

+  register char *sp asm ("sp");                                             \

+  if (sp - sizeof(struct intctx) - sizeof(Thread) < (char *)_otp)           \

+    asm volatile ("mov     r0, #0                               \n\t"       \

+                  "b       chDbgPanic");                                    \

+  _port_switch_arm(_ntp, _otp);                                             \

+}

+#else /* !CH_DBG_ENABLE_STACK_CHECK */

+#define port_switch(ntp, otp) _port_switch_arm(ntp, otp)

+#endif /* !CH_DBG_ENABLE_STACK_CHECK */

+#endif /* !THUMB */

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+  void port_halt(void);

+#ifdef THUMB

+  void _port_switch_thumb(Thread *ntp, Thread *otp);

+#else /* !THUMB */

+  void _port_switch_arm(Thread *ntp, Thread *otp);

+#endif /* !THUMB */

+  void _port_thread_start(void);

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* _CHCORE_H_ */

+

+/** @} */

diff --git a/os/ports/GCC/ARM/chcoreasm.s b/os/ports/GCC/ARM/chcoreasm.s
new file mode 100644
index 000000000..e7d68a061
--- /dev/null
+++ b/os/ports/GCC/ARM/chcoreasm.s
@@ -0,0 +1,237 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/**

+ * @file    ARM7/chcoreasm.s

+ * @brief   ARM7 architecture port low level code.

+ *

+ * @addtogroup ARM7_CORE

+ * @{

+ */

+

+#include "chconf.h"

+

+#if !defined(__DOXYGEN__)

+

+.set    MODE_USR, 0x10

+.set    MODE_FIQ, 0x11

+.set    MODE_IRQ, 0x12

+.set    MODE_SVC, 0x13

+.set    MODE_ABT, 0x17

+.set    MODE_UND, 0x1B

+.set    MODE_SYS, 0x1F

+

+.equ    I_BIT, 0x80

+.equ    F_BIT, 0x40

+

+.text

+

+/*

+ * Interrupt enable/disable functions, only present if there is THUMB code in

+ * the system because those are inlined in ARM code.

+ */

+#ifdef THUMB_PRESENT

+.balign 16

+.code 16

+.thumb_func

+.global _port_disable_thumb

+_port_disable_thumb:

+        mov     r3, pc

+        bx      r3

+.code 32

+        mrs     r3, CPSR

+        orr     r3, #I_BIT

+        msr     CPSR_c, r3

+        orr     r3, #F_BIT

+        msr     CPSR_c, r3

+        bx      lr

+

+.balign 16

+.code 16

+.thumb_func

+.global _port_suspend_thumb

+_port_suspend_thumb:

+.thumb_func

+.global _port_lock_thumb

+_port_lock_thumb:

+        mov     r3, pc

+        bx      r3

+.code 32

+        msr     CPSR_c, #MODE_SYS | I_BIT

+        bx      lr

+

+.balign 16

+.code 16

+.thumb_func

+.global _port_enable_thumb

+_port_enable_thumb:

+.thumb_func

+.global _port_unlock_thumb

+_port_unlock_thumb:

+        mov     r3, pc

+        bx      r3

+.code 32

+        msr     CPSR_c, #MODE_SYS

+        bx      lr

+

+#endif

+

+.balign 16

+#ifdef THUMB_PRESENT

+.code 16

+.thumb_func

+.global _port_switch_thumb

+_port_switch_thumb:

+        mov     r2, pc

+        bx      r2

+        // Jumps into _port_switch_arm in ARM mode

+#endif

+.code 32

+.global _port_switch_arm

+_port_switch_arm:

+#ifdef CH_CURRP_REGISTER_CACHE

+        stmfd   sp!, {r4, r5, r6, r8, r9, r10, r11, lr}

+        str     sp, [r1, #12]

+        ldr     sp, [r0, #12]

+#ifdef THUMB_PRESENT

+        ldmfd   sp!, {r4, r5, r6, r8, r9, r10, r11, lr}

+        bx      lr

+#else /* !THUMB_PRESENT */

+        ldmfd   sp!, {r4, r5, r6, r8, r9, r10, r11, pc}

+#endif /* !THUMB_PRESENT */

+#else /* !CH_CURRP_REGISTER_CACHE */

+        stmfd   sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr}

+        str     sp, [r1, #12]

+        ldr     sp, [r0, #12]

+#ifdef THUMB_PRESENT

+        ldmfd   sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr}

+        bx      lr

+#else /* !THUMB_PRESENT */

+        ldmfd   sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc}

+#endif /* !THUMB_PRESENT */

+#endif /* !CH_CURRP_REGISTER_CACHE */

+

+/*

+ * Common exit point for all IRQ routines, it performs the rescheduling if

+ * required.

+ * System stack frame structure after a context switch in the

+ * interrupt handler:

+ *

+ * High +------------+

+ *      |   LR_USR   | -+

+ *      |     R12    |  |

+ *      |     R3     |  |

+ *      |     R2     |  | External context: IRQ handler frame

+ *      |     R1     |  |

+ *      |     R0     |  |

+ *      |     PC     |  |   (user code return address)

+ *      |   PSR_USR  | -+   (user code status)

+ *      |    ....    | <- mk_DoRescheduleI() stack frame, optimize it for space

+ *      |     LR     | -+   (system code return address)

+ *      |     R11    |  |

+ *      |     R10    |  |

+ *      |     R9     |  |

+ *      |     R8     |  | Internal context: mk_SwitchI() frame

+ *      |    (R7)    |  |   (optional, see CH_CURRP_REGISTER_CACHE)

+ *      |     R6     |  |

+ *      |     R5     |  |

+ * SP-> |     R4     | -+

+ * Low  +------------+

+ */

+.balign 16

+#ifdef THUMB_NO_INTERWORKING

+.code 16

+.thumb_func

+.globl _port_irq_common

+_port_irq_common:

+        bl      chSchIsRescRequiredExI

+        mov     lr, pc

+        bx      lr

+.code 32

+#else /* !THUMB_NO_INTERWORKING */

+.code 32

+.globl _port_irq_common

+_port_irq_common:

+        bl      chSchIsRescRequiredExI

+#endif /* !THUMB_NO_INTERWORKING */

+        cmp     r0, #0                          // Simply returns if a

+        ldmeqfd sp!, {r0-r3, r12, lr}           // reschedule is not

+        subeqs  pc, lr, #4                      // required.

+

+        // Saves the IRQ mode registers in the system stack.

+        ldmfd   sp!, {r0-r3, r12, lr}           // IRQ stack now empty.

+        msr     CPSR_c, #MODE_SYS | I_BIT

+        stmfd   sp!, {r0-r3, r12, lr}           // Registers on System Stack.

+        msr     CPSR_c, #MODE_IRQ | I_BIT

+        mrs     r0, SPSR

+        mov     r1, lr

+        msr     CPSR_c, #MODE_SYS | I_BIT

+        stmfd   sp!, {r0, r1}                   // Push R0=SPSR, R1=LR_IRQ.

+

+        // Context switch.

+#ifdef THUMB_NO_INTERWORKING

+        add     r0, pc, #1

+        bx      r0

+.code 16

+        bl      chSchDoRescheduleI

+        mov     lr, pc

+        bx      lr

+.code 32

+#else /* !THUMB_NO_INTERWORKING */

+        bl      chSchDoRescheduleI

+#endif /* !THUMB_NO_INTERWORKING */

+

+        // Re-establish the IRQ conditions again.

+        ldmfd   sp!, {r0, r1}                   // Pop R0=SPSR, R1=LR_IRQ.

+        msr     CPSR_c, #MODE_IRQ | I_BIT

+        msr     SPSR_fsxc, r0

+        mov     lr, r1

+        msr     CPSR_c, #MODE_SYS | I_BIT

+        ldmfd   sp!, {r0-r3, r12, lr}

+        msr     CPSR_c, #MODE_IRQ | I_BIT

+        subs    pc, lr, #4

+

+/*

+ * Threads trampoline code.

+ * NOTE: The threads always start in ARM mode then switch to the thread-function mode.

+ */

+.balign 16

+.code 32

+.globl _port_thread_start

+_port_thread_start:

+        msr     CPSR_c, #MODE_SYS

+#ifndef THUMB_NO_INTERWORKING

+        mov     r0, r5

+        mov     lr, pc

+        bx      r4

+        bl      chThdExit

+#else /* !THUMB_NO_INTERWORKING */

+        add     r0, pc, #1

+        bx      r0

+.code 16

+        mov     r0, r5

+        bl      jmpr4

+        bl      chThdExit

+jmpr4:

+        bx      r4

+#endif /* !THUMB_NO_INTERWORKING */

+

+#endif /* !defined(__DOXYGEN__) */

+

+/** @} */

diff --git a/os/ports/GCC/ARM/chtypes.h b/os/ports/GCC/ARM/chtypes.h
new file mode 100644
index 000000000..6fcfe1af0
--- /dev/null
+++ b/os/ports/GCC/ARM/chtypes.h
@@ -0,0 +1,82 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/**

+ * @file    ARM7/chtypes.h

+ * @brief   ARM7 architecture port system types.

+ *

+ * @addtogroup ARM7_CORE

+ * @{

+ */

+

+#ifndef _CHTYPES_H_

+#define _CHTYPES_H_

+

+#define __need_NULL

+#define __need_size_t

+#define __need_ptrdiff_t

+#include <stddef.h>

+

+#if !defined(_STDINT_H) && !defined(__STDINT_H_)

+#include <stdint.h>

+#endif

+

+typedef int32_t         bool_t;         /**< Fast boolean type.             */

+typedef uint8_t         tmode_t;        /**< Thread flags.                  */

+typedef uint8_t         tstate_t;       /**< Thread state.                  */

+typedef uint8_t         trefs_t;        /**< Thread references counter.     */

+typedef uint32_t        tprio_t;        /**< Thread priority.               */

+typedef int32_t         msg_t;          /**< Inter-thread message.          */

+typedef int32_t         eventid_t;      /**< Event Id.                      */

+typedef uint32_t        eventmask_t;    /**< Events mask.                   */

+typedef uint32_t        systime_t;      /**< System time.                   */

+typedef int32_t         cnt_t;          /**< Resources counter.             */

+

+/**

+ * @brief   Inline function modifier.

+ */

+#define INLINE inline

+

+/**

+ * @brief   ROM constant modifier.

+ * @note    It is set to use the "const" keyword in this port.

+ */

+#define ROMCONST const

+

+/**

+ * @brief   Packed structure modifier (within).

+ * @note    It uses the "packed" GCC attribute.

+ */

+#define PACK_STRUCT_STRUCT __attribute__((packed))

+

+/**

+ * @brief   Packed structure modifier (before).

+ * @note    Empty in this port.

+ */

+#define PACK_STRUCT_BEGIN

+

+/**

+ * @brief   Packed structure modifier (after).

+ * @note    Empty in this port.

+ */

+#define PACK_STRUCT_END

+

+#endif /* _CHTYPES_H_ */

+

+/** @} */

diff --git a/os/ports/GCC/ARM/crt0.s b/os/ports/GCC/ARM/crt0.s
new file mode 100644
index 000000000..e5a39b520
--- /dev/null
+++ b/os/ports/GCC/ARM/crt0.s
@@ -0,0 +1,184 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/**

+ * @file    ARM7/crt0.s

+ * @brief   Generic ARM7 startup file for ChibiOS/RT.

+ *

+ * @addtogroup ARM7_CORE

+ * @{

+ */

+

+#if !defined(__DOXYGEN__)

+

+.set    MODE_USR, 0x10

+.set    MODE_FIQ, 0x11

+.set    MODE_IRQ, 0x12

+.set    MODE_SVC, 0x13

+.set    MODE_ABT, 0x17

+.set    MODE_UND, 0x1B

+.set    MODE_SYS, 0x1F

+

+.equ    I_BIT, 0x80

+.equ    F_BIT, 0x40

+

+.text

+.code 32

+.balign 4

+

+/*

+ * Reset handler.

+ */

+.global ResetHandler

+ResetHandler:

+        /*

+         * Stack pointers initialization.

+         */

+        ldr     r0, =__ram_end__

+        /* Undefined */

+        msr     CPSR_c, #MODE_UND | I_BIT | F_BIT

+        mov     sp, r0

+        ldr     r1, =__und_stack_size__

+        sub     r0, r0, r1

+        /* Abort */

+        msr     CPSR_c, #MODE_ABT | I_BIT | F_BIT

+        mov     sp, r0

+        ldr     r1, =__abt_stack_size__

+        sub     r0, r0, r1

+        /* FIQ */

+        msr     CPSR_c, #MODE_FIQ | I_BIT | F_BIT

+        mov     sp, r0

+        ldr     r1, =__fiq_stack_size__

+        sub     r0, r0, r1

+        /* IRQ */

+        msr     CPSR_c, #MODE_IRQ | I_BIT | F_BIT

+        mov     sp, r0

+        ldr     r1, =__irq_stack_size__

+        sub     r0, r0, r1

+        /* Supervisor */

+        msr     CPSR_c, #MODE_SVC | I_BIT | F_BIT

+        mov     sp, r0

+        ldr     r1, =__svc_stack_size__

+        sub     r0, r0, r1

+        /* System */

+        msr     CPSR_c, #MODE_SYS | I_BIT | F_BIT

+        mov     sp, r0

+//        ldr     r1, =__sys_stack_size__

+//        sub     r0, r0, r1

+        /*

+         * Early initialization.

+         */

+#ifndef THUMB_NO_INTERWORKING

+        bl      hwinit0

+#else

+        add     r0, pc, #1

+        bx      r0

+.code 16

+        bl      hwinit0

+        mov     r0, pc

+        bx      r0

+.code 32

+#endif

+        /*

+         * Data initialization.

+         * NOTE: It assumes that the DATA size is a multiple of 4.

+         */

+        ldr     r1, =_textdata

+        ldr     r2, =_data

+        ldr     r3, =_edata

+dataloop:

+        cmp     r2, r3

+        ldrlo   r0, [r1], #4

+        strlo   r0, [r2], #4

+        blo     dataloop

+        /*

+         * BSS initialization.

+         * NOTE: It assumes that the BSS size is a multiple of 4.

+         */

+        mov     r0, #0

+        ldr     r1, =_bss_start

+        ldr     r2, =_bss_end

+bssloop:

+        cmp     r1, r2

+        strlo   r0, [r1], #4

+        blo     bssloop

+        /*

+         * Late initialization.

+         */

+#ifdef THUMB_NO_INTERWORKING

+        add     r0, pc, #1

+        bx      r0

+.code 16

+        bl      hwinit1

+        mov     r0, #0

+        mov     r1, r0

+        bl      main

+        ldr     r1, =MainExitHandler

+        bx      r1

+.code 32

+#else

+        bl      hwinit1

+        mov     r0, #0

+        mov     r1, r0

+        bl      main

+        b       MainExitHandler

+#endif

+

+/*

+ * Default main function exit handler.

+ */

+.weak MainExitHandler

+.globl MainExitHandler

+MainExitHandler:

+

+.loop:  b       .loop

+

+/*

+ * Default early initialization code. It is declared weak in order to be

+ * replaced by the real initialization code.

+ * Early initialization is performed just after reset before BSS and DATA

+ * segments initialization.

+ */

+#ifdef THUMB_NO_INTERWORKING

+.thumb_func

+.code 16

+#endif

+.weak hwinit0

+hwinit0:

+        bx      lr

+.code 32

+

+/*

+ * Default late initialization code. It is declared weak in order to be

+ * replaced by the real initialization code.

+ * Late initialization is performed after BSS and DATA segments initialization

+ * and before invoking the main() function.

+ */

+#ifdef THUMB_NO_INTERWORKING

+.thumb_func

+.code 16

+#endif

+.weak hwinit1

+hwinit1:

+        bx      lr

+.code 32

+

+#endif

+

+/** @} */

diff --git a/os/ports/GCC/ARM/port.dox b/os/ports/GCC/ARM/port.dox
new file mode 100644
index 000000000..f72f3c435
--- /dev/null
+++ b/os/ports/GCC/ARM/port.dox
@@ -0,0 +1,213 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/**

+ * @defgroup ARM7 ARM7

+ * @details ARM7 port for the GCC compiler.

+ *

+ * @section ARM7_INTRO Introduction

+ * The ARM7-GCC port supports the ARM7 code in the following three modes:

+ * - Pure ARM mode, this is the preferred mode for code speed. The code size

+ *   is larger however. This mode is enabled when all the modules are compiled

+ *   in ARM mode, see the Makefiles.

+ * - Pure THUMB mode, this is the preferred mode for code size. In this mode

+ *   the execution speed is slower than the ARM mode. This mode is enabled

+ *   when all the modules are compiled in THUMB mode, see the Makefiles.

+ * - Interworking mode, when in the system there are ARM modules mixed with

+ *   THUMB modules then the interworking compiler option is enabled. This is

+ *   usually the slowest mode and the code size is not as good as in pure

+ *   THUMB mode.

+ * .

+ * @section ARM7_STATES Mapping of the System States in the ARM7 port

+ * The ChibiOS/RT logical system states are mapped as follow in the ARM7

+ * port:

+ * - <b>Init</b>. This state is represented by the startup code and the

+ *   initialization code before @p chSysInit() is executed. It has not a

+ *   special hardware state associated, usually the CPU goes through several

+ *   hardware states during the startup phase.

+ * - <b>Normal</b>. This is the state the system has after executing

+ *   @p chSysInit(). In this state the ARM7TDMI has both the interrupt sources

+ *   (IRQ and FIQ) enabled and is running in ARM System Mode.

+ * - <b>Suspended</b>. In this state the IRQ sources are disabled but the FIQ

+ *   sources are served, the core is running in ARM System Mode.

+ * - <b>Disabled</b>. Both the IRQ and FIQ sources are disabled, the core is

+ *   running in ARM System Mode.

+ * - <b>Sleep</b>. The ARM7 code does not have any built-in low power mode but

+ *   there are clock stop modes implemented in custom ways by the various

+ *   silicon vendors. This state is implemented in each microcontroller support

+ *   code in a different way, the core is running (or freezed...) in ARM

+ *   System Mode.

+ * - <b>S-Locked</b>. IRQ sources disabled, core running in ARM System Mode.

+ * - <b>I-Locked</b>. IRQ sources disabled, core running in ARM IRQ Mode. Note

+ *   that this state is not different from the SRI state in this port, the

+ *   @p chSysLockI() and @p chSysUnlockI() APIs do nothing (still use them in

+ *   order to formally change state because this may change).

+ * - <b>Serving Regular Interrupt</b>. IRQ sources disabled, core running in

+ *   ARM IRQ Mode. See also the I-Locked state.

+ * - <b>Serving Fast Interrupt</b>. IRQ and FIQ sources disabled, core running

+ *   in ARM FIQ Mode.

+ * - <b>Serving Non-Maskable Interrupt</b>. There are no asynchronous NMI

+ *   sources in ARM7 architecture but synchronous SVC, ABT and UND exception

+ *   handlers can be seen as belonging to this category.

+ * - <b>Halted</b>. Implemented as an infinite loop after disabling both IRQ

+ *   and FIQ sources. The ARM state is whatever the processor was running when

+ *   @p chSysHalt() was invoked.

+ * .

+ * @section ARM7_NOTES The ARM7 port notes

+ * The ARM7 port is organized as follow:

+ * - The @p main() function is invoked in system mode.

+ * - Each thread has a private user/system stack, the system has a single

+ *   interrupt stack where all the interrupts are processed.

+ * - The threads are started in system mode.

+ * - The threads code can run in system mode or user mode, however the

+ *   code running in user mode cannot invoke the ChibiOS/RT APIs directly

+ *   because privileged instructions are used inside.<br>

+ *   The kernel APIs can be eventually invoked by using a SWI entry point

+ *   that handles the switch in system mode and the return in user mode.

+ * - Other modes are not preempt-able because the system code assumes the

+ *   threads running in system mode. When running in supervisor or other

+ *   modes make sure that the interrupts are globally disabled.

+ * - Interrupts nesting is not supported in the ARM7 code because their

+ *   implementation, even if possible, is not really efficient in this

+ *   architecture.

+ * - FIQ sources can preempt the kernel (by design) so it is not possible to

+ *   invoke the kernel APIs from inside a FIQ handler. FIQ handlers are not

+ *   affected by the kernel activity so there is not added jitter.

+ * .

+ * @section ARM7_IH ARM7 Interrupt Handlers

+ * ARM7 Interrupt handlers do not save function-saved registers so you need to

+ * make sure your code saves them or does not use them (this happens

+ * because in the ARM7 port all the OS interrupt handler functions are declared

+ * naked).<br>

+ * Function-trashed registers (R0-R3, R12, LR, SR) are saved/restored by the

+ * system macros @p CH_IRQ_PROLOGUE() and @p CH_IRQ_EPILOGUE().<br>

+ * The easiest way to ensure this is to just invoke a normal function from

+ * within the interrupt handler, the function code will save all the required

+ * registers.<br>

+ * Example:

+ * @code

+ * CH_IRQ_HANDLER(irq_handler) {

+ *   CH_IRQ_PROLOGUE();

+ *

+ *   serve_interrupt();

+ *

+ *   VICVectAddr = 0; // This is LPC214x-specific.

+ *   CH_IRQ_EPILOGUE();

+ * }

+ * @endcode

+ * This is not a bug but an implementation choice, this solution allows to

+ * have interrupt handlers compiled in thumb mode without have to use an

+ * interworking mode (the mode switch is hidden in the macros), this

+ * greatly improves code efficiency and size. You can look at the serial

+ * driver for real examples of interrupt handlers.<br>

+ * It is important that the serve_interrupt() interrupt function is not

+ * inlined by the compiler into the ISR or the code could still modify

+ * the unsaved registers, this can be accomplished using GCC by adding

+ * the attribute "noinline" to the function:

+ * @code

+ * #if defined(__GNUC__)

+ * __attribute__((noinline))

+ * #endif

+ * static void serve_interrupt(void) {

+ * }

+ * @endcode

+ * Note that several commercial compilers support a GNU-like functions

+ * attribute mechanism.<br>

+ * Alternative ways are to use an appropriate pragma directive or disable

+ * inlining optimizations in the modules containing the interrupt handlers.

+ *

+ * @ingroup gcc

+ */

+

+/**

+ * @defgroup ARM7_CONF Configuration Options

+ * @details ARM7 specific configuration options. The ARM7 port allows some

+ * architecture-specific configurations settings that can be overridden by

+ * redefining them in @p chconf.h. Usually there is no need to change the

+ * default values.

+ * - @p INT_REQUIRED_STACK, this value represent the amount of stack space used

+ *   by an interrupt handler between the @p extctx and @p intctx

+ *   structures.<br>

+ *   In practice this value is the stack space used by the chSchDoReschedule()

+ *   stack frame.<br>

+ *   This value can be affected by a variety of external things like compiler

+ *   version, compiler options, kernel settings (speed/size) and so on.<br>

+ *   The default for this value is @p 0x10 which should be a safe value, you

+ *   can trim this down by defining the macro externally. This would save

+ *   some valuable RAM space for each thread present in the system.<br>

+ *   The default value is set into <b>./os/ports/GCC/ARM7/chcore.h</b>.

+ * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE

+ *   thread. Usually there is no need to change this value unless inserting

+ *   code in the IDLE thread hook macro.

+ * .

+ * @ingroup ARM7

+ */

+

+/**

+ * @defgroup ARM7_CORE Core Port Implementation

+ * @details ARM7 specific port code, structures and macros.

+ *

+ * @ingroup ARM7

+ */

+

+/**

+ * @defgroup ARM7_STARTUP Startup Support

+ * @details ARM7 startup code support. ChibiOS/RT provides its own generic

+ * startup file for the ARM7 port. Of course it is not mandatory to use it

+ * but care should be taken about the startup phase details.

+ *

+ * @section ARM7_STARTUP_1 Startup Process

+ * The startup process, as implemented, is the following:

+ * -# The stacks are initialized by assigning them the sizes defined in the

+ *    linker script (usually named @p ch.ld). Stack areas are allocated from

+ *    the highest RAM location downward.

+ * -# The ARM state is switched to System with both IRQ and FIQ sources

+ *    disabled.

+ * -# An early initialization routine @p hwinit0 is invoked, if the symbol is

+ *    not defined then an empty default routine is executed (weak symbol).

+ * -# DATA and BSS segments are initialized.

+ * -# A late initialization routine @p hwinit1 is invoked, if the symbol not

+ *    defined then an empty default routine is executed (weak symbol).<br>

+ *    This late initialization function is also the proper place for a

+ *    @a bootloader, if your application requires one.

+ * -# The @p main() function is invoked with the parameters @p argc and @p argv

+ *    set to zero.

+ * -# Should the @p main() function return a branch is performed to the weak

+ *    symbol MainExitHandler. The default code is an endless empty loop.

+ * .

+ * @section ARM7_STARTUP_2 Expected linker symbols

+ * The startup code starts at the symbol @p ResetHandler and expects the

+ * following symbols to be defined in the linker script:

+ * - @p __ram_end__ RAM end location +1.

+ * - @p __und_stack_size__ Undefined Instruction stack size.

+ * - @p __abt_stack_size__ Memory Abort stack size.

+ * - @p __fiq_stack_size__ FIQ service stack size.

+ * - @p __irq_stack_size__ IRQ service stack size.

+ * - @p __svc_stack_size__ SVC service stack size.

+ * - @p __sys_stack_size__ System/User stack size. This is the stack area used

+ *      by the @p main() function.

+ * - @p _textdata address of the data segment source read only data.

+ * - @p _data data segment start location.

+ * - @p _edata data segment end location +1.

+ * - @p _bss_start BSS start location.

+ * - @p _bss_end BSS end location +1.

+ * .

+ * @ingroup ARM7

+ * @file ARM7/crt0.s Startup code.

+ */

diff --git a/os/ports/GCC/ARM/port.mk b/os/ports/GCC/ARM/port.mk
new file mode 100644
index 000000000..fdad5f5e6
--- /dev/null
+++ b/os/ports/GCC/ARM/port.mk
@@ -0,0 +1,7 @@
+# List of the ChibiOS/RT ARM7/9 port files.

+PORTSRC = ${CHIBIOS}/os/ports/GCC/ARM/chcore.c

+

+PORTASM = ${CHIBIOS}/os/ports/GCC/ARM/crt0.s \

+          ${CHIBIOS}/os/ports/GCC/ARM/chcoreasm.s

+

+PORTINC = ${CHIBIOS}/os/ports/GCC/ARM

diff --git a/os/ports/GCC/ARM/rules.mk b/os/ports/GCC/ARM/rules.mk
new file mode 100644
index 000000000..81d9d54fa
--- /dev/null
+++ b/os/ports/GCC/ARM/rules.mk
@@ -0,0 +1,146 @@
+# ARM7/9 common makefile scripts and rules.

+

+# Output

+OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex $(BUILDDIR)/$(PROJECT).bin $(BUILDDIR)/$(PROJECT).dmp

+ifeq ($(BUILDDIR),)

+  BUILDDIR = .

+  CLEANDIR =

+else

+  CLEANDIR = $(BUILDDIR)

+endif

+ENSUREBUILDDIR = $(shell test -d $(BUILDDIR) || mkdir $(BUILDDIR))

+

+# Automatic compiler options

+OPT = $(USE_OPT)

+CPPOPT = $(USE_CPPOPT)

+ifeq ($(USE_CURRP_CACHING),yes)

+  OPT += -ffixed-r7 -DCH_CURRP_REGISTER_CACHE='"r7"'

+endif

+ifeq ($(USE_LINK_GC),yes)

+  OPT += -ffunction-sections -fdata-sections

+endif

+

+# Source files groups

+ifeq ($(USE_THUMB),yes)

+  TCSRC += $(CSRC)

+  TCPPSRC += $(CPPSRC)

+else

+  ACSRC += $(CSRC)

+  ACPPSRC += $(CPPSRC)

+endif

+ASRC	 = $(ACSRC)$(ACPPSRC)

+TSRC	 = $(TCSRC)$(TCPPSRC)

+SRC	     = $(ASRC)$(TSRC)

+

+# Object files groups

+ACOBJS   = $(ACSRC:.c=.o)

+ACPPOBJS = $(ACPPSRC:.cpp=.o)

+TCOBJS   = $(TCSRC:.c=.o)

+TCPPOBJS = $(TCPPSRC:.cpp=.o)

+ASMOBJS  = $(ASMSRC:.s=.o)

+OBJS	 = $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS)

+

+# Paths

+IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR))

+LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))

+

+# Macros

+DEFS    = $(DDEFS) $(UDEFS)

+ADEFS   = $(DADEFS) $(UADEFS)

+

+# Libs

+LIBS    = $(DLIBS) $(ULIBS)

+

+# Various settings

+MCFLAGS = -mcpu=$(MCU)

+ODFLAGS	= -x --syms

+ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS)

+CFLAGS   = $(MCFLAGS) $(OPT) $(CWARN) -Wa,-alms=$(<:.c=.lst) $(DEFS)

+CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(<:.cpp=.lst) $(DEFS)

+ifeq ($(USE_LINK_GC),yes)

+  LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LLIBDIR)

+else

+  LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch $(LLIBDIR)

+endif

+

+# Thumb interwork enabled only if needed because it kills performance.

+ifneq ($(TSRC),)

+  CFLAGS += -DTHUMB_PRESENT

+  CPPFLAGS += -DTHUMB_PRESENT

+  ASFLAGS += -DTHUMB_PRESENT

+  ifneq ($(ASRC),)

+    # Mixed ARM and THUMB mode.

+    CFLAGS += -mthumb-interwork

+    CPPFLAGS += -mthumb-interwork

+    ASFLAGS += -mthumb-interwork

+    LDFLAGS += -mthumb-interwork

+  else

+    # Pure THUMB mode, THUMB C code cannot be called by ARM asm code directly.

+    CFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING

+    CPPFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING

+    ASFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb

+    LDFLAGS += -mno-thumb-interwork -mthumb

+  endif

+else

+  # Pure ARM mode

+  CFLAGS += -mno-thumb-interwork

+  CPPFLAGS += -mno-thumb-interwork

+  ASFLAGS += -mno-thumb-interwork

+  LDFLAGS += -mno-thumb-interwork

+endif

+

+# Generate dependency information

+CFLAGS += -MD -MP -MF .dep/$(@F).d

+CPPFLAGS += -MD -MP -MF .dep/$(@F).d

+

+#

+# Makefile rules

+#

+

+all: $(ENSUREBUILDDIR) $(OBJS) $(OUTFILES)

+

+$(ACPPOBJS) : %.o : %.cpp

+	@echo

+	$(CPPC) -c $(CPPFLAGS) $(AOPT) -I . $(IINCDIR) $< -o $@

+

+$(TCPPOBJS) : %.o : %.cpp

+	@echo

+	$(CPPC) -c $(CPPFLAGS) $(TOPT) -I . $(IINCDIR) $< -o $@

+

+$(ACOBJS) : %.o : %.c

+	@echo

+	$(CC) -c $(CFLAGS) $(AOPT) -I . $(IINCDIR) $< -o $@

+

+$(TCOBJS) : %.o : %.c

+	@echo

+	$(CC) -c $(CFLAGS) $(TOPT) -I . $(IINCDIR) $< -o $@

+

+$(ASMOBJS) : %.o : %.s

+	@echo

+	$(AS) -c $(ASFLAGS) -I . $(IINCDIR) $< -o $@

+

+%elf: $(OBJS)

+	@echo

+	$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@

+

+%hex: %elf

+	$(HEX) $< $@

+

+%bin: %elf

+	$(BIN) $< $@

+

+%dmp: %elf

+	$(OD) $(ODFLAGS) $< > $@

+

+clean:

+	-rm -f $(OBJS)

+	-rm -f $(ACSRC:.c=.lst) $(TCSRC:.c=.lst) $(ACPPSRC:.cpp=.lst) $(TCPPSRC:.cpp=.lst) $(ASMSRC:.s=.lst)

+	-rm -f $(OUTFILES) $(BUILDDIR)/$(PROJECT).map

+	-rm -fR .dep $(CLEANDIR)

+

+#

+# Include the dependency files, should be the last of the makefile

+#

+-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)

+

+# *** EOF ***