diff options
author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2010-03-30 12:43:18 +0000 |
---|---|---|
committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2010-03-30 12:43:18 +0000 |
commit | cb53a3d67adbce8c84203d93d6895b52daa56c7e (patch) | |
tree | ec48fbce35df7eb084002622ca12841dc351e14b /os | |
parent | e475309b5c1e6ccb76c59e19b04085526a6e8e5e (diff) | |
download | ChibiOS-cb53a3d67adbce8c84203d93d6895b52daa56c7e.tar.gz ChibiOS-cb53a3d67adbce8c84203d93d6895b52daa56c7e.tar.bz2 ChibiOS-cb53a3d67adbce8c84203d93d6895b52daa56c7e.zip |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1811 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
-rw-r--r-- | os/ports/GCC/ARMCM3/chcore.h | 25 | ||||
-rw-r--r-- | os/ports/GCC/ARMCMx/LPC11xx/cmparams.h | 25 | ||||
-rw-r--r-- | os/ports/GCC/ARMCMx/LPC11xx/port.mk | 2 | ||||
-rw-r--r-- | os/ports/GCC/ARMCMx/STM32F10x/cmparams.h | 56 | ||||
-rw-r--r-- | os/ports/GCC/ARMCMx/STM32F10x/port.mk | 10 | ||||
-rw-r--r-- | os/ports/GCC/ARMCMx/STM32F10x/vectors.s | 363 | ||||
-rw-r--r-- | os/ports/GCC/ARMCMx/chcore.h | 128 |
7 files changed, 563 insertions, 46 deletions
diff --git a/os/ports/GCC/ARMCM3/chcore.h b/os/ports/GCC/ARMCM3/chcore.h index 1808e8b26..8c7c5fd69 100644 --- a/os/ports/GCC/ARMCM3/chcore.h +++ b/os/ports/GCC/ARMCM3/chcore.h @@ -28,17 +28,32 @@ #ifndef _CHCORE_H_
#define _CHCORE_H_
-/*
- * Port-related configuration parameters.
+/*===========================================================================*/
+/* Port constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Port implementing a exception mode context switching.
+ * @details This macro can be used to differentiate this port from the other
+ * Cortex-Mx port which defines @p CORTEX_PORT_MODE_EXOSWITCH.
*/
+#define CORTEX_PORT_MODE_ENDOSWITCH
+
+/*===========================================================================*/
+/* Port configurable parameters. */
+/*===========================================================================*/
/**
* @brief Enables the use of the WFI ins.
*/
-#ifndef ENABLE_WFI_IDLE
-#define ENABLE_WFI_IDLE 0
+#ifndef CORTEX_ENABLE_WFI_IDLE
+#define CORTEX_ENABLE_WFI_IDLE FALSE
#endif
+/*===========================================================================*/
+/* Port exported info. */
+/*===========================================================================*/
+
/**
* @brief Name of the implemented architecture.
*/
@@ -309,7 +324,7 @@ struct context { * modes.
* @note Implemented as an inlined @p WFI instruction.
*/
-#if ENABLE_WFI_IDLE || defined(__DOXYGEN__)
+#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__)
#define port_wait_for_interrupt() { \
asm volatile ("wfi"); \
}
diff --git a/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h b/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h index 0b55670d3..33de7b0f8 100644 --- a/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h +++ b/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h @@ -31,13 +31,6 @@ #ifndef _CMPARAMS_H_
#define _CMPARAMS_H_
-/*===========================================================================*/
-/* Constants parameters. */
-/*===========================================================================*/
-
-#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */
-#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */
-
/**
* @brief Cortex core model.
*/
@@ -55,27 +48,9 @@ /**
* @brief Number of bits in priority masks.
- * @details The available number of priority levels is equal to
- * (1 << @p CORTEX_PRIORITY_BITS).
*/
#define CORTEX_PRIORITY_BITS 2
-/**
- * @brief Priority to priority mask conversion macro.
- */
-#define CORTEX_PRIORITY(n) ((n) << (8 - CORTEX_PRIORITY_BITS))
-
-/*===========================================================================*/
-/* Configurable parameters. */
-/*===========================================================================*/
-
-/**
- * @brief SYSTICK handler priority.
- */
-#ifndef CORTEX_PRIORITY_SYSTICK
-#define CORTEX_PRIORITY_SYSTICK CORTEX_PRIORITY(2)
-#endif
-
#endif /* _CMPARAMS_H_ */
/** @} */
diff --git a/os/ports/GCC/ARMCMx/LPC11xx/port.mk b/os/ports/GCC/ARMCMx/LPC11xx/port.mk index 0d82384fb..dfbb01b16 100644 --- a/os/ports/GCC/ARMCMx/LPC11xx/port.mk +++ b/os/ports/GCC/ARMCMx/LPC11xx/port.mk @@ -1,4 +1,4 @@ -# List of the ChibiOS/RT Cortex-M0 LPC11xx port files.
+# List of the ChibiOS/RT Cortex-M0 LPC111x port files.
PORTSRC = ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
${CHIBIOS}/os/ports/GCC/ARMCMx/nvic.c
# ${CHIBIOS}/os/ports/GCC/ARMCMx/cmsis/core_cm0.c
diff --git a/os/ports/GCC/ARMCMx/STM32F10x/cmparams.h b/os/ports/GCC/ARMCMx/STM32F10x/cmparams.h new file mode 100644 index 000000000..902753f83 --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F10x/cmparams.h @@ -0,0 +1,56 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file ARMCMx/STM32F10x/cmparams.h
+ * @brief ARM Cortex-M3 STM32F10x specific parameters.
+ *
+ * @defgroup ARMCMx_STM32F10x STM32F10x specific parameters
+ * @ingroup ARMCMx
+ * @details This file contains the Cortex-M3 specific parameters for the
+ * STM32F10x platform.
+ * @{
+ */
+
+#ifndef _CMPARAMS_H_
+#define _CMPARAMS_H_
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL CORTEX_M3
+
+/**
+ * @brief Systick unit presence.
+ */
+#define CORTEX_HAS_ST TRUE
+
+/**
+ * @brief Memory Protection unit presence.
+ */
+#define CORTEX_HAS_MPU FALSE
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 4
+
+#endif /* _CMPARAMS_H_ */
+
+/** @} */
diff --git a/os/ports/GCC/ARMCMx/STM32F10x/port.mk b/os/ports/GCC/ARMCMx/STM32F10x/port.mk new file mode 100644 index 000000000..739f031f8 --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F10x/port.mk @@ -0,0 +1,10 @@ +# List of the ChibiOS/RT Cortex-M3 STM32 port files.
+PORTSRC = ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
+ ${CHIBIOS}/os/ports/GCC/ARMCMx/nvic.c \
+ ${CHIBIOS}/os/ports/GCC/ARMCMx/cmsis/core_cm3.c
+
+PORTASM = ${CHIBIOS}/os/ports/GCC/ARMCMx/crt0.s
+
+PORTINC = ${CHIBIOS}/os/ports/GCC/ARMCMx \
+ ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F10x \
+ ${CHIBIOS}/os/ports/GCC/ARMCMx/cmsis
diff --git a/os/ports/GCC/ARMCMx/STM32F10x/vectors.s b/os/ports/GCC/ARMCMx/STM32F10x/vectors.s new file mode 100644 index 000000000..58b0f8aea --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F10x/vectors.s @@ -0,0 +1,363 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+.syntax unified
+.thumb
+
+.section vectors
+_vectors:
+ .word __ram_end__
+ .word ResetHandler
+ .word NMIVector
+ .word HardFaultVector
+ .word MemManageVector
+ .word BusFaultVector
+ .word UsageFaultVector
+ .word Vector1C
+ .word Vector20
+ .word Vector24
+ .word Vector28
+ .word SVCallVector
+ .word DebugMonitorVector
+ .word Vector34
+ .word PendSVVector
+ .word SysTickVector
+ .word Vector40
+ .word Vector44
+ .word Vector48
+ .word Vector4C
+ .word Vector50
+ .word Vector54
+ .word Vector58
+ .word Vector5C
+ .word Vector60
+ .word Vector64
+ .word Vector68
+ .word Vector6C
+ .word Vector70
+ .word Vector74
+ .word Vector78
+ .word Vector7C
+ .word Vector80
+ .word Vector84
+ .word Vector88
+ .word Vector8C
+ .word Vector90
+ .word Vector94
+ .word Vector98
+ .word Vector9C
+ .word VectorA0
+ .word VectorA4
+ .word VectorA8
+ .word VectorAC
+ .word VectorB0
+ .word VectorB4
+ .word VectorB8
+ .word VectorBC
+ .word VectorC0
+ .word VectorC4
+ .word VectorC8
+ .word VectorCC
+ .word VectorD0
+ .word VectorD4
+ .word VectorD8
+ .word VectorDC
+ .word VectorE0
+ .word VectorE4
+ .word VectorE8
+#if defined(STM32F10X_HD) || defined(STM32F10X_CL)
+ .word VectorEC
+ .word VectorF0
+ .word VectorF4
+ .word VectorF8
+ .word VectorFC
+ .word Vector100
+ .word Vector104
+ .word Vector108
+ .word Vector10C
+ .word Vector110
+ .word Vector114
+ .word Vector118
+ .word Vector11C
+ .word Vector120
+ .word Vector124
+ .word Vector128
+ .word Vector12C
+#endif
+#if defined(STM32F10X_CL)
+ .word Vector130
+ .word Vector134
+ .word Vector138
+ .word Vector13C
+ .word Vector140
+ .word Vector144
+ .word Vector148
+ .word Vector14C
+#endif
+
+.weak NMIVector
+NMIVector:
+
+.weak HardFaultVector
+HardFaultVector:
+
+.weak MemManageVector
+MemManageVector:
+
+.weak BusFaultVector
+BusFaultVector:
+
+.weak UsageFaultVector
+UsageFaultVector:
+
+.weak Vector1C
+Vector1C:
+
+.weak Vector20
+Vector20:
+
+.weak Vector24
+Vector24:
+
+.weak Vector28
+Vector28:
+
+.weak SVCallVector
+SVCallVector:
+
+.weak DebugMonitorVector
+DebugMonitorVector:
+
+.weak Vector34
+Vector34:
+
+.weak PendSVVector
+PendSVVector:
+
+.weak SysTickVector
+SysTickVector:
+
+.weak Vector40
+Vector40:
+
+.weak Vector44
+Vector44:
+
+.weak Vector48
+Vector48:
+
+.weak Vector4C
+Vector4C:
+
+.weak Vector50
+Vector50:
+
+.weak Vector54
+Vector54:
+
+.weak Vector58
+Vector58:
+
+.weak Vector5C
+Vector5C:
+
+.weak Vector60
+Vector60:
+
+.weak Vector64
+Vector64:
+
+.weak Vector68
+Vector68:
+
+.weak Vector6C
+Vector6C:
+
+.weak Vector70
+Vector70:
+
+.weak Vector74
+Vector74:
+
+.weak Vector78
+Vector78:
+
+.weak Vector7C
+Vector7C:
+
+.weak Vector80
+Vector80:
+
+.weak Vector84
+Vector84:
+
+.weak Vector88
+Vector88:
+
+.weak Vector8C
+Vector8C:
+
+.weak Vector90
+Vector90:
+
+.weak Vector94
+Vector94:
+
+.weak Vector98
+Vector98:
+
+.weak Vector9C
+Vector9C:
+
+.weak VectorA0
+VectorA0:
+
+.weak VectorA4
+VectorA4:
+
+.weak VectorA8
+VectorA8:
+
+.weak VectorAC
+VectorAC:
+
+.weak VectorB0
+VectorB0:
+
+.weak VectorB4
+VectorB4:
+
+.weak VectorB8
+VectorB8:
+
+.weak VectorBC
+VectorBC:
+
+.weak VectorC0
+VectorC0:
+
+.weak VectorC4
+VectorC4:
+
+.weak VectorC8
+VectorC8:
+
+.weak VectorCC
+VectorCC:
+
+.weak VectorD0
+VectorD0:
+
+.weak VectorD4
+VectorD4:
+
+.weak VectorD8
+VectorD8:
+
+.weak VectorDC
+VectorDC:
+
+.weak VectorE0
+VectorE0:
+
+.weak VectorE4
+VectorE4:
+
+.weak VectorE8
+VectorE8:
+
+#if defined(STM32F10X_HD) || defined(STM32F10X_CL)
+.weak VectorEC
+VectorEC:
+
+.weak VectorF0
+VectorF0:
+
+.weak VectorF4
+VectorF4:
+
+.weak VectorF8
+VectorF8:
+
+.weak VectorFC
+VectorFC:
+
+.weak Vector100
+Vector100:
+
+.weak Vector104
+Vector104:
+
+.weak Vector108
+Vector108:
+
+.weak Vector10C
+Vector10C:
+
+.weak Vector110
+Vector110:
+
+.weak Vector114
+Vector114:
+
+.weak Vector118
+Vector118:
+
+.weak Vector11C
+Vector11C:
+
+.weak Vector120
+Vector120:
+
+.weak Vector124
+Vector124:
+
+.weak Vector128
+Vector128:
+
+.weak Vector12C
+Vector12C:
+#endif
+#if defined(STM32F10X_CL)
+.weak Vector130
+Vector130:
+
+.weak Vector134
+Vector134:
+
+.weak Vector138
+Vector138:
+
+.weak Vector13C
+Vector13C:
+
+.weak Vector140
+Vector140:
+
+.weak Vector144
+Vector144:
+
+.weak Vector148
+Vector148:
+
+.weak Vector14C
+Vector14C:
+#endif
+
+here: b here
diff --git a/os/ports/GCC/ARMCMx/chcore.h b/os/ports/GCC/ARMCMx/chcore.h index 80266c79b..93f3cf4b8 100644 --- a/os/ports/GCC/ARMCMx/chcore.h +++ b/os/ports/GCC/ARMCMx/chcore.h @@ -28,43 +28,141 @@ #ifndef _CHCORE_H_
#define _CHCORE_H_
-/*
- * Port-related configuration parameters.
+/*===========================================================================*/
+/* Port constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Port implementing a process mode context switching.
+ * @details This macro can be used to differentiate this port from the other
+ * Cortex-Mx port which defines @p CORTEX_PORT_MODE_ENDOSWITCH.
*/
+#define CORTEX_PORT_MODE_EXOSWITCH
+
+#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */
+#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */
+#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */
+#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */
+
+/* Inclusion of the Cortex-Mx implementation specific parameters.*/
+#include "cmparams.h"
+
+/* Cortex model check, only M0 and M3 right now.*/
+#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M3)
+#else
+#error "unknown or unsupported Cortex-M model"
+#endif
+
+/*===========================================================================*/
+/* Port derived parameters. */
+/*===========================================================================*/
/**
- * @brief Enables the use of the WFI ins.
+ * @brief Priority masking support.
*/
-#ifndef ENABLE_WFI_IDLE
-#define ENABLE_WFI_IDLE 0
+#if (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4) || \
+ defined(__DOXYGEN__)
+#define CORTEX_SUPPORT_BASEPRI TRUE
+#else
+#define CORTEX_SUPPORT_BASEPRI FALSE
#endif
/**
- * @brief Name of the implemented architecture.
+ * @brief Total priority levels.
*/
-#define CH_ARCHITECTURE_NAME "ARM"
+#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS)
-/* Inclusion of the Cortex-Mx implementation specific parameters.*/
-#include "cmparams.h"
+/**
+ * @brief Minimum priority level.
+ * @details This minimum priority level is calculated from the number of
+ * priority bits supported by the specific Cortex-Mx implementation.
+ */
+#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1)
+
+/**
+ * @brief Maximum priority level.
+ * @details The maximum allowed priority level is always zero.
+ */
+#define CORTEX_MAXIMUM_PRIORITY 0
+
+#if
+/*===========================================================================*/
+/* Port macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Priority level verification macro.
+ */
+#define CORTEX_IS_VALID_PRIORITY(n) \
+ (((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS))
-/* Generating model-dependent info.*/
-#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)
+/**
+ * @brief Priority level to priority mask conversion macro.
+ */
+#define CORTEX_PRIORITY_MASK(n) ((n) << (8 - CORTEX_PRIORITY_BITS))
+
+/*===========================================================================*/
+/* Port configurable parameters. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the use of the WFI instruction in the idle thread loop.
+ */
+#ifndef CORTEX_ENABLE_WFI_IDLE
+#define CORTEX_ENABLE_WFI_IDLE FALSE
+#endif
+
+/**
+ * @brief SYSTICK handler priority.
+ * @note The default is calculated as the priority level in the middle
+ * of the priority range.
+ */
+#ifndef CORTEX_PRIORITY_SYSTICK
+#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1)
+#else
+/* If it is externally redefined then better perform a validity check on it.*/
+#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK)
+#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK"
+#endif
+#endif
+
+/*===========================================================================*/
+/* Port exported info. */
+/*===========================================================================*/
+
+/**
+ * @brief Name of the implemented architecture.
+ */
+#define CH_ARCHITECTURE_NAME "ARM"
+
+#if defined(__DOXYGEN__)
/**
* @brief Macro defining the ARM Cortex-M3 architecture.
*/
-#define CH_ARCHITECTURE_ARMCM3
+#define CH_ARCHITECTURE_ARMCMx
/**
* @brief Name of the architecture variant (optional).
*/
+#define CH_CORE_VARIANT_NAME "Cortex-Mx"
+#elif CORTEX_MODEL == CORTEX_M4
+#define CH_ARCHITECTURE_ARMCM4
+#define CH_CORE_VARIANT_NAME "Cortex-M4"
+#elif CORTEX_MODEL == CORTEX_M3
+#define CH_ARCHITECTURE_ARMCM3
#define CH_CORE_VARIANT_NAME "Cortex-M3"
+#elif CORTEX_MODEL == CORTEX_M1
+#define CH_ARCHITECTURE_ARMCM1
+#define CH_CORE_VARIANT_NAME "Cortex-M1"
#elif CORTEX_MODEL == CORTEX_M0
#define CH_ARCHITECTURE_ARMCM0
#define CH_CORE_VARIANT_NAME "Cortex-M0"
-#else
-#error "unknown or unsupported Cortex-M model"
#endif
+/*===========================================================================*/
+/* Port implementation part. */
+/*===========================================================================*/
+
/**
* @brief 32 bits stack and memory alignment enforcement.
*/
@@ -302,7 +400,7 @@ struct context { * modes.
* @note Implemented as an inlined @p WFI instruction.
*/
-#if ENABLE_WFI_IDLE || defined(__DOXYGEN__)
+#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__)
#define port_wait_for_interrupt() asm volatile ("wfi")
#else
#define port_wait_for_interrupt()
|