git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3578 35acf78f-673a-0410-8e92-d51de3d6d3f4

5 files changed, 105 insertions, 59 deletions

diff --git a/os/hal/include/i2c.h b/os/hal/include/i2c.h
index 5ee4887e9..f412e8a97 100644
--- a/os/hal/include/i2c.h
+++ b/os/hal/include/i2c.h
@@ -43,16 +43,16 @@
  * @name    I2C bus error conditions

  * @{

  */

-#define  I2CD_NO_ERROR              0x00    /**< @brief No error.           */

-#define  I2CD_BUS_ERROR             0x01    /**< @brief Bus Error.          */

-#define  I2CD_ARBITRATION_LOST      0x02    /**< @brief Arbitration Lost

-                                                 (master mode).             */

-#define  I2CD_ACK_FAILURE           0x04    /**< @brief Acknowledge Failure.*/

-#define  I2CD_OVERRUN               0x08    /**< @brief Overrun/Underrun.   */

-#define  I2CD_PEC_ERROR             0x10    /**< @brief PEC Error in

-                                                 reception.                 */

-#define  I2CD_TIMEOUT               0x20    /**< @brief Timeout Error.      */

-#define  I2CD_SMB_ALERT             0x40    /**< @brief SMBus Alert.        */

+#define I2CD_NO_ERROR               0x00   /**< @brief No error.            */

+#define I2CD_BUS_ERROR              0x01   /**< @brief Bus Error.           */

+#define I2CD_ARBITRATION_LOST       0x02   /**< @brief Arbitration Lost

+                                                (master mode).              */

+#define I2CD_ACK_FAILURE            0x04   /**< @brief Acknowledge Failure. */

+#define I2CD_OVERRUN                0x08   /**< @brief Overrun/Underrun.    */

+#define I2CD_PEC_ERROR              0x10   /**< @brief PEC Error in

+                                                reception.                  */

+#define I2CD_TIMEOUT                0x20   /**< @brief Timeout Error.       */

+#define I2CD_SMB_ALERT              0x40   /**< @brief SMBus Alert.         */

 /** @} */

 

 /*===========================================================================*/

@@ -187,8 +187,6 @@ extern "C" {
                          uint8_t *rxbuf, size_t rxbytes);

   i2cflags_t i2cMasterReceive(I2CDriver *i2cp,

                         uint8_t slave_addr, uint8_t *rxbuf, size_t rxbytes);

-  void i2cMasterStart(I2CDriver *i2cp);

-  void i2cMasterStop(I2CDriver *i2cp);

   void i2cAddFlagsI(I2CDriver *i2cp, i2cflags_t mask);

   i2cflags_t i2cGetAndClearFlags(I2CDriver *i2cp);

 

diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/os/hal/platforms/STM32F1xx/hal_lld_f100.h
index 96f5a7f33..16bb84cbf 100644
--- a/os/hal/platforms/STM32F1xx/hal_lld_f100.h
+++ b/os/hal/platforms/STM32F1xx/hal_lld_f100.h
@@ -164,8 +164,22 @@
 

 /* I2C attributes.*/

 #define STM32_HAS_I2C1          TRUE

+#define STM32_I2C1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 7))

+#define STM32_I2C1_RX_DMA_CHN   0x00000000

+#define STM32_I2C1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 6))

+#define STM32_I2C1_TX_DMA_CHN   0x00000000

+

 #define STM32_HAS_I2C2          FALSE

+#define STM32_I2C2_RX_DMA_MSK   0

+#define STM32_I2C2_RX_DMA_CHN   0x00000000

+#define STM32_I2C2_TX_DMA_MSK   0

+#define STM32_I2C2_TX_DMA_CHN   0x00000000

+

 #define STM32_HAS_I2C3          FALSE

+#define STM32_SPI3_RX_DMA_MSK   0

+#define STM32_SPI3_RX_DMA_CHN   0x00000000

+#define STM32_SPI3_TX_DMA_MSK   0

+#define STM32_SPI3_TX_DMA_CHN   0x00000000

 

 #define STM32_HAS_RTC           TRUE

 

diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f103.h b/os/hal/platforms/STM32F1xx/hal_lld_f103.h
index d251e6a5d..108854ff7 100644
--- a/os/hal/platforms/STM32F1xx/hal_lld_f103.h
+++ b/os/hal/platforms/STM32F1xx/hal_lld_f103.h
@@ -174,8 +174,22 @@
 

 /* I2C attributes.*/

 #define STM32_HAS_I2C1          TRUE

+#define STM32_I2C1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 7))

+#define STM32_I2C1_RX_DMA_CHN   0x00000000

+#define STM32_I2C1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 6))

+#define STM32_I2C1_TX_DMA_CHN   0x00000000

+

 #define STM32_HAS_I2C2          FALSE

+#define STM32_I2C2_RX_DMA_MSK   0

+#define STM32_I2C2_RX_DMA_CHN   0x00000000

+#define STM32_I2C2_TX_DMA_MSK   0

+#define STM32_I2C2_TX_DMA_CHN   0x00000000

+

 #define STM32_HAS_I2C3          FALSE

+#define STM32_SPI3_RX_DMA_MSK   0

+#define STM32_SPI3_RX_DMA_CHN   0x00000000

+#define STM32_SPI3_TX_DMA_MSK   0

+#define STM32_SPI3_TX_DMA_CHN   0x00000000

 

 /* RTC attributes.*/

 #define STM32_HAS_RTC           TRUE

@@ -323,8 +337,6 @@
 #define STM32_I2C3_TX_DMA_MSK   0

 #define STM32_I2C3_TX_DMA_CHN   0x00000000

 

-

-

 /* RTC attributes.*/

 #define STM32_HAS_RTC           TRUE

 

@@ -454,8 +466,22 @@
 

 /* I2C attributes.*/

 #define STM32_HAS_I2C1          TRUE

+#define STM32_I2C1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 7))

+#define STM32_I2C1_RX_DMA_CHN   0x00000000

+#define STM32_I2C1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 6))

+#define STM32_I2C1_TX_DMA_CHN   0x00000000

+

 #define STM32_HAS_I2C2          TRUE

+#define STM32_I2C2_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 5))

+#define STM32_I2C2_RX_DMA_CHN   0x00000000

+#define STM32_I2C2_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 4))

+#define STM32_I2C2_TX_DMA_CHN   0x00000000

+

 #define STM32_HAS_I2C3          FALSE

+#define STM32_I2C3_RX_DMA_MSK   0

+#define STM32_I2C3_RX_DMA_CHN   0x00000000

+#define STM32_I2C3_TX_DMA_MSK   0

+#define STM32_I2C3_TX_DMA_CHN   0x00000000

 

 /* RTC attributes.*/

 #define STM32_HAS_RTC           TRUE

@@ -586,8 +612,22 @@
 

 /* I2C attributes.*/

 #define STM32_HAS_I2C1          TRUE

+#define STM32_I2C1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 7))

+#define STM32_I2C1_RX_DMA_CHN   0x00000000

+#define STM32_I2C1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 6))

+#define STM32_I2C1_TX_DMA_CHN   0x00000000

+

 #define STM32_HAS_I2C2          TRUE

+#define STM32_I2C2_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 5))

+#define STM32_I2C2_RX_DMA_CHN   0x00000000

+#define STM32_I2C2_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 4))

+#define STM32_I2C2_TX_DMA_CHN   0x00000000

+

 #define STM32_HAS_I2C3          FALSE

+#define STM32_I2C3_RX_DMA_MSK   0

+#define STM32_I2C3_RX_DMA_CHN   0x00000000

+#define STM32_I2C3_TX_DMA_MSK   0

+#define STM32_I2C3_TX_DMA_CHN   0x00000000

 

 /* RTC attributes.*/

 #define STM32_HAS_RTC           TRUE

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h
index 061ce1304..1bb69958e 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.h
+++ b/os/hal/platforms/STM32F4xx/hal_lld.h
@@ -292,25 +292,25 @@
 

 /* I2C attributes.*/

 #define STM32_HAS_I2C1          TRUE

-#define STM32_I2C1_RX_DMA_MSK ((STM32_DMA_STREAM_ID_MSK(1, 0) |             \

-                               STM32_DMA_STREAM_ID_MSK(1, 5)))

-#define STM32_I2C1_RX_DMA_CHN 0x00100001

-#define STM32_I2C1_TX_DMA_MSK ((STM32_DMA_STREAM_ID_MSK(1, 7)) |            \

-                              (STM32_DMA_STREAM_ID_MSK(1, 6)))

-#define STM32_I2C1_TX_DMA_CHN 0x10000000

+#define STM32_I2C1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 0) |            \

+                                 STM32_DMA_STREAM_ID_MSK(1, 5))

+#define STM32_I2C1_RX_DMA_CHN   0x00100001

+#define STM32_I2C1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 7)) |           \

+                                 (STM32_DMA_STREAM_ID_MSK(1, 6))

+#define STM32_I2C1_TX_DMA_CHN   0x10000000

 

 #define STM32_HAS_I2C2          TRUE

-#define STM32_I2C2_RX_DMA_MSK ((STM32_DMA_STREAM_ID_MSK(1, 2) |             \

-                               STM32_DMA_STREAM_ID_MSK(1, 3)))

-#define STM32_I2C2_RX_DMA_CHN 0x00007700

-#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))

-#define STM32_I2C2_TX_DMA_CHN 0x70000000

+#define STM32_I2C2_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 2) |            \

+                                 STM32_DMA_STREAM_ID_MSK(1, 3))

+#define STM32_I2C2_RX_DMA_CHN   0x00007700

+#define STM32_I2C2_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 7))

+#define STM32_I2C2_TX_DMA_CHN   0x70000000

 

 #define STM32_HAS_I2C3          TRUE

-#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))

-#define STM32_I2C3_RX_DMA_CHN 0x00000300

-#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))

-#define STM32_I2C3_TX_DMA_CHN 0x00030000

+#define STM32_I2C3_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 2))

+#define STM32_I2C3_RX_DMA_CHN   0x00000300

+#define STM32_I2C3_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 4))

+#define STM32_I2C3_TX_DMA_CHN   0x00030000

 

 /* RTC attributes.*/

 #define STM32_HAS_RTC           TRUE

diff --git a/os/hal/src/i2c.c b/os/hal/src/i2c.c
index f20932ef3..ae5f9f7a8 100644
--- a/os/hal/src/i2c.c
+++ b/os/hal/src/i2c.c
@@ -133,13 +133,11 @@ void i2cStop(I2CDriver *i2cp) {
 }

 

 /**

- * @brief Sends data via the I2C bus.

- *

+ * @brief   Sends data via the I2C bus.

  * @details Function designed to realize "read-through-write" transfer

  *          paradigm. If you want transmit data without any further read,

  *          than set @b rxbytes field to 0.

- *

- * @details Number of receiving byts must be 0 or more than 1 because of stm32

+ *          Number of receiving byts must be 0 or more than 1 because of stm32

  *          hardware restrictions.

  *

  * @param[in] i2cp        pointer to the @p I2CDriver object

@@ -153,22 +151,21 @@ void i2cStop(I2CDriver *i2cp) {
  * @return                Zero if no errors, otherwise return error code.

  */

 i2cflags_t i2cMasterTransmit(I2CDriver *i2cp,

-                      uint8_t slave_addr,

-                      uint8_t *txbuf,

-                      size_t txbytes,

-                      uint8_t *rxbuf,

-                      size_t rxbytes) {

-

-  chDbgCheck((i2cp != NULL) &&\

-  		(slave_addr != 0) &&\

-  		(txbytes > 0) &&\

-  		(txbuf != NULL) &&\

-  		((rxbytes == 0) || ((rxbytes > 1) && (rxbuf != NULL))),

-  		"i2cMasterTransmit");

+                             uint8_t slave_addr,

+                             uint8_t *txbuf,

+                             size_t txbytes,

+                             uint8_t *rxbuf,

+                             size_t rxbytes) {

+

+  chDbgCheck((i2cp != NULL) && (slave_addr != 0) &&

+             (txbytes > 0) && (txbuf != NULL) &&

+             ((rxbytes == 0) || ((rxbytes > 1) && (rxbuf != NULL))),

+             "i2cMasterTransmit");

 

   i2c_lld_wait_bus_free(i2cp);

-  chDbgAssert(!(i2c_lld_bus_is_busy(i2cp)), "i2cMasterReceive(), #1", "time is out");

 

+  chDbgAssert(!(i2c_lld_bus_is_busy(i2cp)),

+              "i2cMasterReceive(), #1", "time is out");

   chDbgAssert(i2cp->id_state == I2C_READY,

               "i2cMasterTransmit(), #1", "not ready");

 

@@ -180,8 +177,8 @@ i2cflags_t i2cMasterTransmit(I2CDriver *i2cp,
 }

 

 /**

- * @brief Receives data from the I2C bus.

- * @details Number of receiving byts must be more than 1 because of stm32

+ * @brief   Receives data from the I2C bus.

+ *          Number of receiving byts must be more than 1 because of stm32

  *          hardware restrictions.

  *

  * @param[in] i2cp        pointer to the @p I2CDriver object

@@ -192,19 +189,18 @@ i2cflags_t i2cMasterTransmit(I2CDriver *i2cp,
  * @return                Zero if no errors, otherwise return error code.

  */

 i2cflags_t i2cMasterReceive(I2CDriver *i2cp,

-                      uint8_t slave_addr,

-                      uint8_t *rxbuf,

-                      size_t rxbytes){

+                            uint8_t slave_addr,

+                            uint8_t *rxbuf,

+                            size_t rxbytes){

 

-  chDbgCheck((i2cp != NULL) &&\

-  		(slave_addr != 0) &&\

-  		(rxbytes > 1) && \

-  		(rxbuf != NULL),

-      "i2cMasterReceive");

+  chDbgCheck((i2cp != NULL) && (slave_addr != 0) &&

+             (rxbytes > 1) && (rxbuf != NULL),

+             "i2cMasterReceive");

 

   i2c_lld_wait_bus_free(i2cp);

-  chDbgAssert(!(i2c_lld_bus_is_busy(i2cp)), "i2cMasterReceive(), #1", "time is out");

 

+  chDbgAssert(!(i2c_lld_bus_is_busy(i2cp)),

+              "i2cMasterReceive(), #1", "time is out");

   chDbgAssert(i2cp->id_state == I2C_READY,

               "i2cMasterReceive(), #1", "not ready");

 

@@ -253,8 +249,6 @@ i2cflags_t i2cGetAndClearFlags(I2CDriver *i2cp) {
   return mask;

 }

 

-

-

 #if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)

 /**

  * @brief Gains exclusive access to the I2C bus.