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authorGiovanni Di Sirio <gdisirio@gmail.com>2018-01-04 11:13:44 +0000
committerGiovanni Di Sirio <gdisirio@gmail.com>2018-01-04 11:13:44 +0000
commitc2994bdb33024b71f3ac0b4283994715ce6eb563 (patch)
tree34f26281efec0dd928589b61664b1907800bb644 /os
parentccbf09f1a2abad73c81e5e059b7d3f6d370e3293 (diff)
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Various fixes, H7 SPI does not work yet.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11220 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
-rwxr-xr-xos/common/startup/ARMCMx/compilers/GCC/ld/STM32H743xI.ld2
-rw-r--r--os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.c3
2 files changed, 3 insertions, 2 deletions
diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/STM32H743xI.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/STM32H743xI.ld
index 56e1d29ae..a7de36fd0 100755
--- a/os/common/startup/ARMCMx/compilers/GCC/ld/STM32H743xI.ld
+++ b/os/common/startup/ARMCMx/compilers/GCC/ld/STM32H743xI.ld
@@ -82,7 +82,7 @@ REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash0);
/* RAM region to be used for BSS segment.*/
-REGION_ALIAS("BSS_RAM", ram3);
+REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
diff --git a/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.c b/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.c
index 936537337..71dd11702 100644
--- a/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.c
+++ b/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.c
@@ -525,6 +525,7 @@ void spi_lld_start(SPIDriver *spip) {
/* Configuration-specific DMA setup.*/
dsize = (spip->config->cfg2 & SPI_CFG1_DSIZE_Msk) + 1U;
cfg1 = spip->config->cfg1 | SPI_CFG1_RXDMAEN | SPI_CFG1_TXDMAEN;
+ cfg1 &= ~SPI_CFG1_FTHLV_Msk;
if (dsize <= 8U) {
/* Frame width is between 4 and 8 bits.*/
spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) |
@@ -561,7 +562,7 @@ void spi_lld_start(SPIDriver *spip) {
spip->spi->CR1 = SPI_CR1_MASRX;
spip->spi->CR2 = 0U;
spip->spi->CFG1 = cfg1;
- spip->spi->CFG2 = spip->config->cfg2 | SPI_CFG2_MASTER;
+ spip->spi->CFG2 = (spip->config->cfg2 | SPI_CFG2_MASTER) & ~SPI_CFG2_COMM_Msk;
spip->spi->IER = SPI_IER_OVRIE;
spip->spi->IFCR = 0xFFFFFFFFU;
spip->spi->CR1 |= SPI_CR1_SPE;