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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-03-24 08:08:41 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-03-24 08:08:41 +0000 |
| commit | b60ed674132d7a837c503e51fbff2850aad04843 (patch) | |
| tree | f38669a4dc0b5f4e4ac40d095565755332875929 /os | |
| parent | 490a3e13277f7df040e6bfec7a7acc0e87e3c7c4 (diff) | |
| download | ChibiOS-b60ed674132d7a837c503e51fbff2850aad04843.tar.gz ChibiOS-b60ed674132d7a837c503e51fbff2850aad04843.tar.bz2 ChibiOS-b60ed674132d7a837c503e51fbff2850aad04843.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5496 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
| -rw-r--r-- | os/hal/platforms/STM32F37x/adc_lld.c | 5 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F37x/adc_lld.h | 60 |
2 files changed, 62 insertions, 3 deletions
diff --git a/os/hal/platforms/STM32F37x/adc_lld.c b/os/hal/platforms/STM32F37x/adc_lld.c index 7c420326b..c8dfc378b 100644 --- a/os/hal/platforms/STM32F37x/adc_lld.c +++ b/os/hal/platforms/STM32F37x/adc_lld.c @@ -572,9 +572,10 @@ void adc_lld_stop_conversion(ADCDriver *adcp) { #endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
#if STM32_ADC_USE_ADC
{
+ uint32_t cr2 = adcp->adc->CR2 & ADC_CR2_TSVREFE;
+ adcp->adc->CR2 = cr2;
adcp->adc->CR1 = 0;
- adcp->adc->CR2 = 0;
- adcp->adc->CR2 = ADC_CR2_ADON;
+ adcp->adc->CR2 = cr2 | ADC_CR2_ADON;
}
#endif /* STM32_ADC_USE_ADC */
#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
diff --git a/os/hal/platforms/STM32F37x/adc_lld.h b/os/hal/platforms/STM32F37x/adc_lld.h index 9af0e5b5c..c984dc24a 100644 --- a/os/hal/platforms/STM32F37x/adc_lld.h +++ b/os/hal/platforms/STM32F37x/adc_lld.h @@ -568,7 +568,7 @@ struct ADCDriver { /*===========================================================================*/
/**
- * @name Sequences building helper macros
+ * @name Sequences building helper macros for ADC
* @{
*/
/**
@@ -623,6 +623,64 @@ struct ADCDriver { #define ADC_SMPR1_SMP_VBAT(n) ((n) << 24) /**< @brief VBAT sampling time. */
/** @} */
+/**
+ * @name Sequences building helper macros for SDADC
+ * @{
+ */
+#define SDADC_JCHGR_CH(n) (1U << (n))
+/** @} */
+
+/**
+ * @name Channel configuration number helper macros for SDADC
+ * @{
+ */
+#define SDADC_CONFCHR1_CH0(n) ((n) << 0)
+#define SDADC_CONFCHR1_CH1(n) ((n) << 4)
+#define SDADC_CONFCHR1_CH2(n) ((n) << 8)
+#define SDADC_CONFCHR1_CH3(n) ((n) << 12)
+#define SDADC_CONFCHR1_CH4(n) ((n) << 16)
+#define SDADC_CONFCHR1_CH5(n) ((n) << 20)
+#define SDADC_CONFCHR1_CH6(n) ((n) << 24)
+#define SDADC_CONFCHR1_CH7(n) ((n) << 28)
+#define SDADC_CONFCHR2_CH8(n) ((n) << 0)
+/** @} */
+
+/**
+ * @name Configuration registers helper macros for SDADC
+ * @{
+ */
+#define SDADC_CONFR_OFFSET_MASK (0xFFFU << 0)
+#define SDADC_CONFR_OFFSET(n) ((n) << 0)
+#define SDADC_CONFR_GAIN_MASK (7U << 20)
+#define SDADC_CONFR_GAIN_1X (0U << 20)
+#define SDADC_CONFR_GAIN_2X (1U << 20)
+#define SDADC_CONFR_GAIN_4X (2U << 20)
+#define SDADC_CONFR_GAIN_8X (3U << 20)
+#define SDADC_CONFR_GAIN_16X (4U << 20)
+#define SDADC_CONFR_GAIN_32X (5U << 20)
+#define SDADC_CONFR_GAIN_0P5X (7U << 20)
+#define SDADC_CONFR_SE_MASK (3U << 26)
+#define SDADC_CONFR_SE_DIFF (0U << 26)
+#define SDADC_CONFR_SE_SE_OFF (1U << 26)
+#define SDADC_CONFR_SE_SE_ZV (3U << 26)
+#define SDADC_CONFR_COMMON_MASK (3U << 30)
+#define SDADC_CONFR_COMMON_VSSSD (0U << 30)
+#define SDADC_CONFR_COMMON_VDDSD2 (1U << 30)
+#define SDADC_CONFR_COMMON_VDDSD (2U << 30)
+/** @} */
+
+#define SDADC_CONF1R_OFFSET1 ((uint32_t)0x00000FFF) /*!< 12-bit calibration offset for configuration 1 */
+#define SDADC_CONF1R_GAIN1 ((uint32_t)0x00700000) /*!< Gain setting for configuration 1 */
+#define SDADC_CONF1R_GAIN1_0 ((uint32_t)0x00100000) /*!< Gain setting for configuration 1 Bit 0 */
+#define SDADC_CONF1R_GAIN1_1 ((uint32_t)0x00200000) /*!< Gain setting for configuration 1 Bit 1 */
+#define SDADC_CONF1R_GAIN1_2 ((uint32_t)0x00400000) /*!< Gain setting for configuration 1 Bit 2 */
+#define SDADC_CONF1R_SE1 ((uint32_t)0x0C000000) /*!< Single ended mode for configuration 1 */
+#define SDADC_CONF1R_SE1_0 ((uint32_t)0x04000000) /*!< Single ended mode for configuration 1 Bit 0 */
+#define SDADC_CONF1R_SE1_1 ((uint32_t)0x08000000) /*!< Single ended mode for configuration 1 Bit 1 */
+#define SDADC_CONF1R_COMMON1 ((uint32_t)0xC0000000) /*!< Common mode for configuration 1 */
+#define SDADC_CONF1R_COMMON1_0 ((uint32_t)0x40000000) /*!< Common mode for configuration 1 Bit 0 */
+#define SDADC_CONF1R_COMMON1_1 ((uint32_t)0x40000000) /*!< Common mode for configuration 1 Bit 1 */
+
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
|