diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2009-11-16 16:39:22 +0000 | 
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2009-11-16 16:39:22 +0000 | 
| commit | aa2f5af6f01de0e2083c2c92bc4ae2fedeac847d (patch) | |
| tree | 2e961919bddaa06ec5b876f8ea494078c77e90b5 /os | |
| parent | b488811f14f65a746ac9e0cdd8d392cd011517e6 (diff) | |
| download | ChibiOS-aa2f5af6f01de0e2083c2c92bc4ae2fedeac847d.tar.gz ChibiOS-aa2f5af6f01de0e2083c2c92bc4ae2fedeac847d.tar.bz2 ChibiOS-aa2f5af6f01de0e2083c2c92bc4ae2fedeac847d.zip  | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1309 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
| -rw-r--r-- | os/io/adc.c | 38 | ||||
| -rw-r--r-- | os/io/platforms/STM32/adc_lld.c | 35 | ||||
| -rw-r--r-- | os/io/platforms/STM32/adc_lld.h | 53 | ||||
| -rw-r--r-- | os/io/platforms/STM32/spi_lld.h | 4 | 
4 files changed, 99 insertions, 31 deletions
diff --git a/os/io/adc.c b/os/io/adc.c index d4fb20bab..4072677e0 100644 --- a/os/io/adc.c +++ b/os/io/adc.c @@ -42,9 +42,9 @@ void adcInit(void) {   */
  void adcObjectInit(ADCDriver *adcp) {
 -  adcp->adc_state = ADC_STOP;
 -  adcp->adc_config = NULL;
 -  chSemInit(&adcp->adc_sem, 0);
 +  adcp->ad_state = ADC_STOP;
 +  adcp->ad_config = NULL;
 +  chSemInit(&adcp->ad_sem, 0);
  }
  /**
 @@ -58,12 +58,12 @@ void adcStart(ADCDriver *adcp, const ADCConfig *config) {    chDbgCheck((adcp != NULL) && (config != NULL), "adcStart");
    chSysLock();
 -  chDbgAssert((adcp->adc_state == ADC_STOP) || (adcp->adc_state == ADC_READY),
 +  chDbgAssert((adcp->ad_state == ADC_STOP) || (adcp->ad_state == ADC_READY),
                "adcStart(), #1",
                "invalid state");
 -  adcp->adc_config = config;
 +  adcp->ad_config = config;
    adc_lld_start(adcp);
 -  adcp->adc_state = ADC_READY;
 +  adcp->ad_state = ADC_READY;
    chSysUnlock();
  }
 @@ -77,11 +77,11 @@ void adcStop(ADCDriver *adcp) {    chDbgCheck(adcp != NULL, "adcStop");
    chSysLock();
 -  chDbgAssert((adcp->adc_state == ADC_STOP) || (adcp->adc_state == ADC_READY),
 +  chDbgAssert((adcp->ad_state == ADC_STOP) || (adcp->ad_state == ADC_READY),
                "adcStop(), #1",
                "invalid state");
    adc_lld_stop(adcp);
 -  adcp->adc_state = ADC_STOP;
 +  adcp->ad_state = ADC_STOP;
    chSysUnlock();
  }
 @@ -127,16 +127,16 @@ bool_t adcStartConversion(ADCDriver *adcp,               "adcStartConversion");
    chSysLock();
 -  chDbgAssert((adcp->adc_state == ADC_READY) ||
 -              (adcp->adc_state == ADC_RUNNING),
 +  chDbgAssert((adcp->ad_state == ADC_READY) ||
 +              (adcp->ad_state == ADC_RUNNING),
                "adcStartConversion(), #1",
                "invalid state");
 -  if (adcp->adc_state == ADC_RUNNING) {
 +  if (adcp->ad_state == ADC_RUNNING) {
      chSysUnlock();
      return TRUE;
    }
    adc_lld_start_conversion(adcp, grpp, samples, depth, callback);
 -  adcp->adc_state = ADC_RUNNING;
 +  adcp->ad_state = ADC_RUNNING;
    chSysUnlock();
    return FALSE;
  }
 @@ -151,12 +151,12 @@ void adcStopConversion(ADCDriver *adcp) {    chDbgCheck(adcp != NULL, "adcStopConversion");
    chSysLock();
 -  chDbgAssert((adcp->adc_state == ADC_READY) ||
 -              (adcp->adc_state == ADC_RUNNING),
 +  chDbgAssert((adcp->ad_state == ADC_READY) ||
 +              (adcp->ad_state == ADC_RUNNING),
                "adcStopConversion(), #1",
                "invalid state");
    adc_lld_stop_conversion(adcp);
 -  adcp->adc_state = ADC_READY;
 +  adcp->ad_state = ADC_READY;
    chSysUnlock();
  }
 @@ -176,12 +176,12 @@ void adcStopConversion(ADCDriver *adcp) {  msg_t adcWaitConversion(ADCDriver *adcp, systime_t timeout) {
    chSysLock();
 -  chDbgAssert((adcp->adc_state == ADC_READY) ||
 -              (adcp->adc_state == ADC_RUNNING),
 +  chDbgAssert((adcp->ad_state == ADC_READY) ||
 +              (adcp->ad_state == ADC_RUNNING),
                "adcWaitConversion(), #1",
                "invalid state");
 -  if (adcp->adc_state == ADC_RUNNING) {
 -    if (chSemWaitTimeoutS(&adcp->adc_sem, timeout) == RDY_TIMEOUT) {
 +  if (adcp->ad_state == ADC_RUNNING) {
 +    if (chSemWaitTimeoutS(&adcp->ad_sem, timeout) == RDY_TIMEOUT) {
        chSysUnlock();
        return RDY_TIMEOUT;
      }
 diff --git a/os/io/platforms/STM32/adc_lld.c b/os/io/platforms/STM32/adc_lld.c index 9581574ec..10fd27ec1 100644 --- a/os/io/platforms/STM32/adc_lld.c +++ b/os/io/platforms/STM32/adc_lld.c @@ -26,6 +26,13 @@  #include <ch.h>
  #include <adc.h>
 +#include <stm32_dma.h>
 +#include <nvic.h>
 +
 +#if USE_STM32_ADC1 || defined(__DOXYGEN__)
 +/** @brief ADC1 driver identifier.*/
 +ADCDriver ADCD1;
 +#endif
  /*===========================================================================*/
  /* Low Level Driver local functions.                                         */
 @@ -44,6 +51,12 @@   */
  void adc_lld_init(void) {
 +#if USE_STM32_ADC1
 +  adcObjectInit(&ADCD1);
 +  DMA1_Channel1->CPAR = (uint32_t)ADC1->DR;
 +  ADCD1.ad_adc = ADC1;
 +  ADCD1.ad_dma = DMA1_Channel1;
 +#endif
  }
  /**
 @@ -53,10 +66,16 @@ void adc_lld_init(void) {   */
  void adc_lld_start(ADCDriver *adcp) {
 -  if (adcp->adc_state == ADC_STOP) {
 -    /* Clock activation.*/
 +  /* If in stopped state then enables the ADC and DMA clocks.*/
 +  if (adcp->ad_state == ADC_STOP) {
 +#if USE_STM32_ADC1
 +    if (&ADCD1 == adcp) {
 +      NVICEnableVector(DMA1_Channel1_IRQn, STM32_ADC1_IRQ_PRIORITY);
 +      dmaEnable(DMA1_ID);
 +      RCC->APB2ENR |= RCC_APB2ENR_ADC1EN;
 +    }
 +#endif
    }
 -  /* Configuration.*/
  }
  /**
 @@ -66,6 +85,16 @@ void adc_lld_start(ADCDriver *adcp) {   */
  void adc_lld_stop(ADCDriver *adcp) {
 +  /* If in ready state then disables the SPI clock.*/
 +  if (adcp->ad_state == ADC_READY) {
 +#if USE_STM32_ADC1
 +    if (&ADCD1 == adcp) {
 +      NVICDisableVector(DMA1_Channel1_IRQn);
 +      dmaDisable(DMA1_ID);
 +      RCC->APB2ENR &= ~RCC_APB2ENR_ADC1EN;
 +    }
 +#endif
 +  }
  }
  /**
 diff --git a/os/io/platforms/STM32/adc_lld.h b/os/io/platforms/STM32/adc_lld.h index 7f1fe2065..996cdf12d 100644 --- a/os/io/platforms/STM32/adc_lld.h +++ b/os/io/platforms/STM32/adc_lld.h @@ -27,10 +27,41 @@  #ifndef _ADC_LLD_H_
  #define _ADC_LLD_H_
 +#undef FALSE
 +#undef TRUE
 +#include <stm32f10x.h>
 +#define FALSE 0
 +#define TRUE (!FALSE)
 +
  /*===========================================================================*/
  /* Driver pre-compile time settings.                                         */
  /*===========================================================================*/
 +/**
 + * @brief ADC1 driver enable switch.
 + * @details If set to @p TRUE the support for ADC1 is included.
 + * @note The default is @p TRUE.
 + */
 +#if !defined(USE_STM32_ADC1) || defined(__DOXYGEN__)
 +#define USE_STM32_ADC1              TRUE
 +#endif
 +
 +/**
 + * @brief ADC1 DMA priority (0..3|lowest..highest).
 + */
 +#if !defined(ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
 +#define ADC1_DMA_PRIORITY           1
 +#endif
 +
 +/**
 + * @brief ADC1 interrupt priority level setting.
 + * @note @p BASEPRI_KERNEL >= @p STM32_ADC1_IRQ_PRIORITY > @p PRIORITY_PENDSV.
 + */
 +#if !defined(STM32_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
 +#define STM32_ADC1_IRQ_PRIORITY     0x70
 +#endif
 +
 +
  /*===========================================================================*/
  /* Driver constants.                                                         */
  /*===========================================================================*/
 @@ -69,31 +100,31 @@ typedef struct {    /**
     * @brief ADC CR1 register initialization data.
     */
 -  uint32_t              ac_cr1;
 +  uint32_t              acg_cr1;
    /**
     * @brief ADC CR2 register initialization data.
     */
 -  uint32_t              ac_cr2;
 +  uint32_t              acg_cr2;
    /**
     * @brief ADC SMPR1 register initialization data.
     */
 -  uint32_t              ac_smpr1;
 +  uint32_t              acg_smpr1;
    /**
     * @brief ADC SMPR2 register initialization data.
     */
 -  uint32_t              ac_smpr2;
 +  uint32_t              acg_smpr2;
    /**
     * @brief ADC SQR1 register initialization data.
     */
 -  uint32_t              ac_sqr1;
 +  uint32_t              acg_sqr1;
    /**
     * @brief ADC SQR2 register initialization data.
     */
 -  uint32_t              ac_sqr2;
 +  uint32_t              acg_sqr2;
    /**
     * @brief ADC SQR3 register initialization data.
     */
 -  uint32_t              ac_sqr3;
 +  uint32_t              acg_sqr3;
  } ADCConversionGroup;
  /**
 @@ -119,6 +150,14 @@ typedef struct {     */
    Semaphore             ad_sem;
    /* End of the mandatory fields.*/
 +  /**
 +   * @brief Pointer to the ADCx registers block.
 +   */
 +  ADC_TypeDef           *ad_adc;
 +  /**
 +   * @brief Pointer to the DMA channel registers block.
 +   */
 +  DMA_Channel_TypeDef   *ad_dma;
  } ADCDriver;
  /*===========================================================================*/
 diff --git a/os/io/platforms/STM32/spi_lld.h b/os/io/platforms/STM32/spi_lld.h index a6041f060..2918eaa6c 100644 --- a/os/io/platforms/STM32/spi_lld.h +++ b/os/io/platforms/STM32/spi_lld.h @@ -82,7 +82,7 @@   * @note @p BASEPRI_KERNEL >= @p STM32_SPI1_IRQ_PRIORITY > @p PRIORITY_PENDSV.
   */
  #if !defined(STM32_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
 -#define STM32_SPI1_IRQ_PRIORITY     0xB0
 +#define STM32_SPI1_IRQ_PRIORITY     0x60
  #endif
  /**
 @@ -90,7 +90,7 @@   * @note @p BASEPRI_KERNEL >= @p STM32_SPI2_IRQ_PRIORITY > @p PRIORITY_PENDSV.
   */
  #if !defined(STM32_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
 -#define STM32_SPI2_IRQ_PRIORITY     0xB0
 +#define STM32_SPI2_IRQ_PRIORITY     0x60
  #endif
  /*===========================================================================*/
  | 
