git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5530 35acf78f-673a-0410-8e92-d51de3d6d3f4

9 files changed, 626 insertions, 90 deletions

diff --git a/os/hal/platforms/SPC560BCxx/hal_lld.h b/os/hal/platforms/SPC560BCxx/hal_lld.h
index 8c4a9a3b4..270923045 100644
--- a/os/hal/platforms/SPC560BCxx/hal_lld.h
+++ b/os/hal/platforms/SPC560BCxx/hal_lld.h
@@ -756,6 +756,8 @@ typedef enum {
 /* External declarations.                                                    */

 /*===========================================================================*/

 

+#include "spc5_edma.h"

+

 #ifdef __cplusplus

 extern "C" {

 #endif

diff --git a/os/hal/platforms/SPC560BCxx/spc560bc_registry.h b/os/hal/platforms/SPC560BCxx/spc560bc_registry.h
index ac3e22637..fccd75b53 100644
--- a/os/hal/platforms/SPC560BCxx/spc560bc_registry.h
+++ b/os/hal/platforms/SPC560BCxx/spc560bc_registry.h
@@ -31,6 +31,9 @@
  * @name    SPC560B/Cxx capabilities

  * @{

  */

+/* eDMA attributes.*/

+#define SPC5_HAS_EDMAA                      FALSE

+

 /* LINFlex attributes.*/

 #define SPC5_HAS_LINFLEX0                   TRUE

 #define SPC5_LINFLEX0_PCTL                  48

diff --git a/os/hal/platforms/SPC560Pxx/hal_lld.h b/os/hal/platforms/SPC560Pxx/hal_lld.h
index 4dd5c5f98..27468ff24 100644
--- a/os/hal/platforms/SPC560Pxx/hal_lld.h
+++ b/os/hal/platforms/SPC560Pxx/hal_lld.h
@@ -936,6 +936,8 @@ typedef enum {
 /* External declarations.                                                    */

 /*===========================================================================*/

 

+#include "spc5_edma.h"

+

 #ifdef __cplusplus

 extern "C" {

 #endif

diff --git a/os/hal/platforms/SPC560Pxx/spc560p_registry.h b/os/hal/platforms/SPC560Pxx/spc560p_registry.h
index 7b4953f18..b5917827c 100644
--- a/os/hal/platforms/SPC560Pxx/spc560p_registry.h
+++ b/os/hal/platforms/SPC560Pxx/spc560p_registry.h
@@ -31,6 +31,11 @@
  * @name    SPC560Pxx capabilities

  * @{

  */

+/* eDMA attributes.*/

+#define SPC5_HAS_EDMAA                      TRUE

+#define SPC5_EDMA_NCHANNELS                 16

+#define SPC5_EDMA_HAS_MUX                   TRUE

+

 /* LINFlex attributes.*/

 #define SPC5_HAS_LINFLEX0                   TRUE

 #define SPC5_LINFLEX0_PCTL                  48

diff --git a/os/hal/platforms/SPC56ELxx/hal_lld.h b/os/hal/platforms/SPC56ELxx/hal_lld.h
index 251df538e..fa2e649dc 100644
--- a/os/hal/platforms/SPC56ELxx/hal_lld.h
+++ b/os/hal/platforms/SPC56ELxx/hal_lld.h
@@ -959,6 +959,8 @@ typedef enum {
 /* External declarations.                                                    */

 /*===========================================================================*/

 

+#include "spc5_edma.h"

+

 #ifdef __cplusplus

 extern "C" {

 #endif

diff --git a/os/hal/platforms/SPC56ELxx/spc56el_registry.h b/os/hal/platforms/SPC56ELxx/spc56el_registry.h
index 0718613fb..a5a575bf1 100644
--- a/os/hal/platforms/SPC56ELxx/spc56el_registry.h
+++ b/os/hal/platforms/SPC56ELxx/spc56el_registry.h
@@ -31,6 +31,11 @@
  * @name    SPC56ELxx capabilities

  * @{

  */

+/* eDMA attributes.*/

+#define SPC5_HAS_EDMAA                      TRUE

+#define SPC5_EDMA_NCHANNELS                 16

+#define SPC5_EDMA_HAS_MUX                   TRUE

+

 /* LINFlex attributes.*/

 #define SPC5_HAS_LINFLEX0                   TRUE

 #define SPC5_LINFLEX0_PCTL                  48

diff --git a/os/hal/platforms/SPC5xx/DSPI_v1/spc5_dspi.h b/os/hal/platforms/SPC5xx/DSPI_v1/spc5_dspi.h
index 7403c5550..1b5175a67 100644
--- a/os/hal/platforms/SPC5xx/DSPI_v1/spc5_dspi.h
+++ b/os/hal/platforms/SPC5xx/DSPI_v1/spc5_dspi.h
@@ -254,19 +254,19 @@ struct spc5_dspi {
  * @{

  */

 #if SPC5_HAS_DSPI0 || defined(__DOXYGEN__)

-#define SPC5_DSPI0      (*(struct spc5_dspi *)0xFFF90000UL)

+#define SPC5_DSPI0      (*(struct spc5_dspi *)0xFFF90000U)

 #endif

 

 #if SPC5_HAS_DSPI1 || defined(__DOXYGEN__)

-#define SPC5_DSPI1      (*(struct spc5_dspi *)0xFFF94000UL)

+#define SPC5_DSPI1      (*(struct spc5_dspi *)0xFFF94000U)

 #endif

 

 #if SPC5_HAS_DSPI2 || defined(__DOXYGEN__)

-#define SPC5_DSPI2      (*(struct spc5_dspi *)0xFFF98000UL)

+#define SPC5_DSPI2      (*(struct spc5_dspi *)0xFFF98000U)

 #endif

 

 #if SPC5_HAS_DSPI3 || defined(__DOXYGEN__)

-#define SPC5_DSPI3      (*(struct spc5_dspi *)0xFFF9C000UL)

+#define SPC5_DSPI3      (*(struct spc5_dspi *)0xFFF9C000U)

 #endif

 /** @} */

 

diff --git a/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c b/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c
index dcac0a593..05b7db902 100644
--- a/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c
+++ b/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c
@@ -55,17 +55,17 @@ static const edma_channel_config_t *channels[SPC5_EDMA_NCHANNELS];
  */

 CH_IRQ_HANDLER(vector10) {

   edma_channel_t channel;

-  uint32_t erl, esr = EDMA.ESR.R;

+  uint32_t erl, esr = SPC5_EDMAA.ESR.R;

 

   CH_IRQ_PROLOGUE();

 

   /* Scanning for errors.*/

   channel = 0;

-  while (((erl = EDMA.ERL.R) != 0) &&

+  while (((erl = SPC5_EDMAA.ERL.R) != 0) &&

          (channel < (SPC5_EDMA_NCHANNELS > 32 ? 32 : SPC5_EDMA_NCHANNELS))) {

     if ((erl & (1U << channel)) != 0) {

       /* Error flag cleared.*/

-      EDMA.CER.R = channel;

+      SPC5_EDMAA.CER.R = channel;

 

       /* If the channel is not associated then the error is simply discarded

          else the error callback is invoked.*/

@@ -93,7 +93,7 @@ CH_IRQ_HANDLER(vector11) {
   if (channels[0] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 0;

+  SPC5_EDMAA.CIRQR.R = 0;

   channels[0]->dma_func(0, channels[0]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -111,7 +111,7 @@ CH_IRQ_HANDLER(vector12) {
   if (channels[1] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 1;

+  SPC5_EDMAA.CIRQR.R = 1;

   channels[1]->dma_func(1, channels[1]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -129,7 +129,7 @@ CH_IRQ_HANDLER(vector13) {
   if (channels[2] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 2;

+  SPC5_EDMAA.CIRQR.R = 2;

   channels[2]->dma_func(2, channels[2]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -147,7 +147,7 @@ CH_IRQ_HANDLER(vector14) {
   if (channels[3] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 3;

+  SPC5_EDMAA.CIRQR.R = 3;

   channels[3]->dma_func(3, channels[3]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -165,7 +165,7 @@ CH_IRQ_HANDLER(vector15) {
   if (channels[4] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 4;

+  SPC5_EDMAA.CIRQR.R = 4;

   channels[4]->dma_func(4, channels[4]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -183,7 +183,7 @@ CH_IRQ_HANDLER(vector16) {
   if (channels[5] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 5;

+  SPC5_EDMAA.CIRQR.R = 5;

   channels[5]->dma_func(5, channels[5]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -201,7 +201,7 @@ CH_IRQ_HANDLER(vector17) {
   if (channels[6] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 6;

+  SPC5_EDMAA.CIRQR.R = 6;

   channels[6]->dma_func(6, channels[6]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -219,7 +219,7 @@ CH_IRQ_HANDLER(vector18) {
   if (channels[7] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 7;

+  SPC5_EDMAA.CIRQR.R = 7;

   channels[7]->dma_func(7, channels[7]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -237,7 +237,7 @@ CH_IRQ_HANDLER(vector19) {
   if (channels[8] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 8;

+  SPC5_EDMAA.CIRQR.R = 8;

   channels[8]->dma_func(8, channels[8]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -255,7 +255,7 @@ CH_IRQ_HANDLER(vector20) {
   if (channels[9] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 9;

+  SPC5_EDMAA.CIRQR.R = 9;

   channels[9]->dma_func(9, channels[9]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -273,7 +273,7 @@ CH_IRQ_HANDLER(vector21) {
   if (channels[10] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 10;

+  SPC5_EDMAA.CIRQR.R = 10;

   channels[10]->dma_func(10, channels[10]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -291,7 +291,7 @@ CH_IRQ_HANDLER(vector22) {
   if (channels[11] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 11;

+  SPC5_EDMAA.CIRQR.R = 11;

   channels[11]->dma_func(11, channels[11]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -309,7 +309,7 @@ CH_IRQ_HANDLER(vector23) {
   if (channels[12] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 12;

+  SPC5_EDMAA.CIRQR.R = 12;

   channels[12]->dma_func(12, channels[12]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -327,7 +327,7 @@ CH_IRQ_HANDLER(vector24) {
   if (channels[13] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 13;

+  SPC5_EDMAA.CIRQR.R = 13;

   channels[13]->dma_func(13, channels[13]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -345,7 +345,7 @@ CH_IRQ_HANDLER(vector25) {
   if (channels[14] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 14;

+  SPC5_EDMAA.CIRQR.R = 14;

   channels[14]->dma_func(14, channels[14]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -363,7 +363,7 @@ CH_IRQ_HANDLER(vector26) {
   if (channels[15] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 15;

+  SPC5_EDMAA.CIRQR.R = 15;

   channels[15]->dma_func(15, channels[15]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -382,7 +382,7 @@ CH_IRQ_HANDLER(vector27) {
   if (channels[16] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 16;

+  SPC5_EDMAA.CIRQR.R = 16;

   channels[16]->dma_func(16, channels[16]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -400,7 +400,7 @@ CH_IRQ_HANDLER(vector28) {
   if (channels[17] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 17;

+  SPC5_EDMAA.CIRQR.R = 17;

   channels[17]->dma_func(17, channels[17]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -418,7 +418,7 @@ CH_IRQ_HANDLER(vector29) {
   if (channels[18] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 18;

+  SPC5_EDMAA.CIRQR.R = 18;

   channels[18]->dma_func(18, channels[18]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -436,7 +436,7 @@ CH_IRQ_HANDLER(vector30) {
   if (channels[19] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 19;

+  SPC5_EDMAA.CIRQR.R = 19;

   channels[19]->dma_func(19, channels[19]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -454,7 +454,7 @@ CH_IRQ_HANDLER(vector31) {
   if (channels[20] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 20;

+  SPC5_EDMAA.CIRQR.R = 20;

   channels[20]->dma_func(20, channels[20]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -472,7 +472,7 @@ CH_IRQ_HANDLER(vector32) {
   if (channels[21] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 21;

+  SPC5_EDMAA.CIRQR.R = 21;

   channels[21]->dma_func(21, channels[21]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -490,7 +490,7 @@ CH_IRQ_HANDLER(vector33) {
   if (channels[22] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 22;

+  SPC5_EDMAA.CIRQR.R = 22;

   channels[22]->dma_func(22, channels[22]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -508,7 +508,7 @@ CH_IRQ_HANDLER(vector34) {
   if (channels[23] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 23;

+  SPC5_EDMAA.CIRQR.R = 23;

   channels[23]->dma_func(23, channels[23]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -526,7 +526,7 @@ CH_IRQ_HANDLER(vector35) {
   if (channels[24] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 24;

+  SPC5_EDMAA.CIRQR.R = 24;

   channels[24]->dma_func(24, channels[24]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -544,7 +544,7 @@ CH_IRQ_HANDLER(vector36) {
   if (channels[25] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 25;

+  SPC5_EDMAA.CIRQR.R = 25;

   channels[25]->dma_func(25, channels[25]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -562,7 +562,7 @@ CH_IRQ_HANDLER(vector37) {
   if (channels[26] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 26;

+  SPC5_EDMAA.CIRQR.R = 26;

   channels[26]->dma_func(26, channels[26]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -580,7 +580,7 @@ CH_IRQ_HANDLER(vector38) {
   if (channels[27] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 27;

+  SPC5_EDMAA.CIRQR.R = 27;

   channels[27]->dma_func(27, channels[27]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -598,7 +598,7 @@ CH_IRQ_HANDLER(vector39) {
   if (channels[28] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 28;

+  SPC5_EDMAA.CIRQR.R = 28;

   channels[28]->dma_func(28, channels[28]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -616,7 +616,7 @@ CH_IRQ_HANDLER(vector40) {
   if (channels[29] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 29;

+  SPC5_EDMAA.CIRQR.R = 29;

   channels[29]->dma_func(29, channels[29]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -634,7 +634,7 @@ CH_IRQ_HANDLER(vector41) {
   if (channels[30] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 30;

+  SPC5_EDMAA.CIRQR.R = 30;

   channels[30]->dma_func(30, channels[30]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -652,7 +652,7 @@ CH_IRQ_HANDLER(vector42) {
   if (channels[31] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 31;

+  SPC5_EDMAA.CIRQR.R = 31;

   channels[31]->dma_func(31, channels[31]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -665,17 +665,17 @@ CH_IRQ_HANDLER(vector42) {
  */

 CH_IRQ_HANDLER(vector210) {

   edma_channel_t channel;

-  uint32_t erh, esr = EDMA.ESR.R;

+  uint32_t erh, esr = SPC5_EDMAA.ESR.R;

 

   CH_IRQ_PROLOGUE();

 

   /* Scanning for errors.*/

   channel = 32;

-  while (((erh = EDMA.ERH.R) != 0) && (channel < SPC5_EDMA_NCHANNELS)) {

+  while (((erh = SPC5_EDMAA.ERH.R) != 0) && (channel < SPC5_EDMA_NCHANNELS)) {

 

     if ((erh & (1U << (channel - 32))) != 0) {

       /* Error flag cleared.*/

-      EDMA.CER.R = channel;

+      SPC5_EDMAA.CER.R = channel;

 

       /* If the channel is not associated then the error is simply discarded

          else the error callback is invoked.*/

@@ -703,7 +703,7 @@ CH_IRQ_HANDLER(vector211) {
   if (channels[32] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 32;

+  SPC5_EDMAA.CIRQR.R = 32;

   channels[32]->dma_func(32, channels[32]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -721,7 +721,7 @@ CH_IRQ_HANDLER(vector212) {
   if (channels[33] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 33;

+  SPC5_EDMAA.CIRQR.R = 33;

   channels[33]->dma_func(33, channels[33]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -739,7 +739,7 @@ CH_IRQ_HANDLER(vector213) {
   if (channels[34] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 34;

+  SPC5_EDMAA.CIRQR.R = 34;

   channels[34]->dma_func(34, channels[34]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -757,7 +757,7 @@ CH_IRQ_HANDLER(vector214) {
   if (channels[35] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 35;

+  SPC5_EDMAA.CIRQR.R = 35;

   channels[35]->dma_func(35, channels[35]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -775,7 +775,7 @@ CH_IRQ_HANDLER(vector215) {
   if (channels[36] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 36;

+  SPC5_EDMAA.CIRQR.R = 36;

   channels[36]->dma_func(36, channels[36]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -793,7 +793,7 @@ CH_IRQ_HANDLER(vector216) {
   if (channels[37] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 37;

+  SPC5_EDMAA.CIRQR.R = 37;

   channels[37]->dma_func(37, channels[37]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -811,7 +811,7 @@ CH_IRQ_HANDLER(vector217) {
   if (channels[38] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 38;

+  SPC5_EDMAA.CIRQR.R = 38;

   channels[38]->dma_func(38, channels[38]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -829,7 +829,7 @@ CH_IRQ_HANDLER(vector218) {
   if (channels[39] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 39;

+  SPC5_EDMAA.CIRQR.R = 39;

   channels[39]->dma_func(39, channels[39]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -847,7 +847,7 @@ CH_IRQ_HANDLER(vector219) {
   if (channels[40] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 40;

+  SPC5_EDMAA.CIRQR.R = 40;

   channels[40]->dma_func(40, channels[40]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -865,7 +865,7 @@ CH_IRQ_HANDLER(vector220) {
   if (channels[41] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 41;

+  SPC5_EDMAA.CIRQR.R = 41;

   channels[41]->dma_func(41, channels[41]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -883,7 +883,7 @@ CH_IRQ_HANDLER(vector221) {
   if (channels[42] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 42;

+  SPC5_EDMAA.CIRQR.R = 42;

   channels[42]->dma_func(42, channels[42]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -901,7 +901,7 @@ CH_IRQ_HANDLER(vector222) {
   if (channels[43] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 43;

+  SPC5_EDMAA.CIRQR.R = 43;

   channels[43]->dma_func(43, channels[43]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -919,7 +919,7 @@ CH_IRQ_HANDLER(vector223) {
   if (channels[44] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 44;

+  SPC5_EDMAA.CIRQR.R = 44;

   channels[44]->dma_func(44, channels[44]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -937,7 +937,7 @@ CH_IRQ_HANDLER(vector224) {
   if (channels[45] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 45;

+  SPC5_EDMAA.CIRQR.R = 45;

   channels[45]->dma_func(45, channels[45]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -955,7 +955,7 @@ CH_IRQ_HANDLER(vector225) {
   if (channels[46] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 46;

+  SPC5_EDMAA.CIRQR.R = 46;

   channels[46]->dma_func(46, channels[46]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -973,7 +973,7 @@ CH_IRQ_HANDLER(vector226) {
   if (channels[47] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 47;

+  SPC5_EDMAA.CIRQR.R = 47;

   channels[47]->dma_func(47, channels[47]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -991,7 +991,7 @@ CH_IRQ_HANDLER(vector227) {
   if (channels[48] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 48;

+  SPC5_EDMAA.CIRQR.R = 48;

   channels[48]->dma_func(48, channels[48]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -1009,7 +1009,7 @@ CH_IRQ_HANDLER(vector228) {
   if (channels[49] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 49;

+  SPC5_EDMAA.CIRQR.R = 49;

   channels[49]->dma_func(49, channels[49]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -1027,7 +1027,7 @@ CH_IRQ_HANDLER(vector229) {
   if (channels[50] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 50;

+  SPC5_EDMAA.CIRQR.R = 50;

   channels[50]->dma_func(50, channels[50]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -1045,7 +1045,7 @@ CH_IRQ_HANDLER(vector230) {
   if (channels[51] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 51;

+  SPC5_EDMAA.CIRQR.R = 51;

   channels[51]->dma_func(51, channels[51]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -1063,7 +1063,7 @@ CH_IRQ_HANDLER(vector231) {
   if (channels[52] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 52;

+  SPC5_EDMAA.CIRQR.R = 52;

   channels[52]->dma_func(52, channels[52]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -1081,7 +1081,7 @@ CH_IRQ_HANDLER(vector232) {
   if (channels[53] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 53;

+  SPC5_EDMAA.CIRQR.R = 53;

   channels[53]->dma_func(53, channels[53]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -1099,7 +1099,7 @@ CH_IRQ_HANDLER(vector233) {
   if (channels[54] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 54;

+  SPC5_EDMAA.CIRQR.R = 54;

   channels[54]->dma_func(54, channels[54]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -1117,7 +1117,7 @@ CH_IRQ_HANDLER(vector234) {
   if (channels[55] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 55;

+  SPC5_EDMAA.CIRQR.R = 55;

   channels[55]->dma_func(55, channels[55]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -1135,7 +1135,7 @@ CH_IRQ_HANDLER(vector235) {
   if (channels[56] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 56;

+  SPC5_EDMAA.CIRQR.R = 56;

   channels[56]->dma_func(56, channels[56]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -1153,7 +1153,7 @@ CH_IRQ_HANDLER(vector236) {
   if (channels[57] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 57;

+  SPC5_EDMAA.CIRQR.R = 57;

   channels[57]->dma_func(57, channels[57]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -1171,7 +1171,7 @@ CH_IRQ_HANDLER(vector237) {
   if (channels[58] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 58;

+  SPC5_EDMAA.CIRQR.R = 58;

   channels[58]->dma_func(58, channels[58]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -1189,7 +1189,7 @@ CH_IRQ_HANDLER(vector238) {
   if (channels[59] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 59;

+  SPC5_EDMAA.CIRQR.R = 59;

   channels[59]->dma_func(59, channels[59]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -1207,7 +1207,7 @@ CH_IRQ_HANDLER(vector239) {
   if (channels[60] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 60;

+  SPC5_EDMAA.CIRQR.R = 60;

   channels[60]->dma_func(60, channels[60]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -1225,7 +1225,7 @@ CH_IRQ_HANDLER(vector240) {
   if (channels[61] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 61;

+  SPC5_EDMAA.CIRQR.R = 61;

   channels[61]->dma_func(61, channels[61]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -1243,7 +1243,7 @@ CH_IRQ_HANDLER(vector241) {
   if (channels[62] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 62;

+  SPC5_EDMAA.CIRQR.R = 62;

   channels[62]->dma_func(62, channels[62]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -1261,7 +1261,7 @@ CH_IRQ_HANDLER(vector242) {
   if (channels[63] == NULL) {

     SPC5_EDMA_ERROR_HANDLER();

   }

-  EDMA.CIRQR.R = 63;

+  SPC5_EDMAA.CIRQR.R = 63;

   channels[63]->dma_func(63, channels[63]->dma_param);

 

   CH_IRQ_EPILOGUE();

@@ -1281,13 +1281,13 @@ CH_IRQ_HANDLER(vector242) {
 void edmaInit(void) {

   unsigned i;

 

-  EDMA.CR.R    = SPC5_EDMA_CR_SETTING;

-  EDMA.ERQRL.R = 0x00000000;

-  EDMA.EEIRL.R = 0x00000000;

-  EDMA.IRQRL.R = 0xFFFFFFFF;

-  EDMA.ERL.R =   0xFFFFFFFF;

+  SPC5_EDMAA.CR.R    = SPC5_EDMA_CR_SETTING;

+  SPC5_EDMAA.ERQRL.R = 0x00000000;

+  SPC5_EDMAA.EEIRL.R = 0x00000000;

+  SPC5_EDMAA.IRQRL.R = 0xFFFFFFFF;

+  SPC5_EDMAA.ERL.R =   0xFFFFFFFF;

   for (i = 0; i < SPC5_EDMA_NCHANNELS; i++)

-    EDMA.CPR[i].R = 0;

+    SPC5_EDMAA.CPR[i].R = 0;

 

   /* Error interrupt source.*/

   INTC.PSR[10].R = SPC5_EDMA_ERROR_IRQ_PRIO;

@@ -1311,7 +1311,7 @@ edma_channel_t edmaChannelAllocate(const edma_channel_config_t *ccfg) {
 

 #if SPC5_EDMA_HAS_MUX

   /* TODO: MUX handling.*/

-  channel = EDMA_ERROR;

+  channel = 0;

 #else /* !SPC5_EDMA_HAS_MUX */

   channel = (edma_channel_t)ccfg->dma_periph;

   if (channels[channel] != NULL)

@@ -1324,7 +1324,7 @@ edma_channel_t edmaChannelAllocate(const edma_channel_config_t *ccfg) {
   /* If an error callback is defined then the error interrupt source is

      enabled for the channel.*/

   if (ccfg->dma_error_func != NULL)

-    EDMA.SEEIR.R = channel;

+    SPC5_EDMAA.SEEIR.R = channel;

 

   /* Setting up IRQ priority for the selected channel.*/

   INTC.PSR[11 + channel].R = ccfg->dma_irq_prio;

@@ -1351,9 +1351,9 @@ void edmaChannelRelease(edma_channel_t channel) {
   edmaChannelStop(channel);

 

   /* Clearing ISR sources for the channel.*/

-  EDMA.CIRQR.R = channel;

-  EDMA.CEEIR.R = channel;

-  EDMA.CER.R   = channel;

+  SPC5_EDMAA.CIRQR.R = channel;

+  SPC5_EDMAA.CEEIR.R = channel;

+  SPC5_EDMAA.CER.R   = channel;

 

   /* The channels is flagged as available.*/

   channels[channel] = NULL;

diff --git a/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.h b/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.h
index 9d2bcce82..14c4d4f85 100644
--- a/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.h
+++ b/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.h
@@ -20,8 +20,8 @@
  * @{

  */

 

-#ifndef _EDMA_H_

-#define _EDMA_H_

+#ifndef _SPC5_EDMA_H_

+#define _SPC5_EDMA_H_

 

 /*===========================================================================*/

 /* Driver constants.                                                         */

@@ -83,12 +83,12 @@
 /*===========================================================================*/

 

 /**

- * @brief   Type of and EDMA channel number.

+ * @brief   Type of and eDMA channel number.

  */

 typedef int32_t edma_channel_t;

 

 /**

- * @brief   Type of an EDMA TCD.

+ * @brief   Type of an eDMA TCD.

  */

 typedef struct {

   union {

@@ -97,6 +97,514 @@ typedef struct {
 } edma_tcd_t;

 

 /**

+ * @brief   Type of an eDMA peripheral.

+ */

+typedef struct {

+

+  union {

+    vuint32_t R;

+    struct {

+      vuint32_t :14;

+      vuint32_t CX :1;

+      vuint32_t ECX :1;

+      vuint32_t GRP3PRI :2;

+      vuint32_t GRP2PRI :2;

+      vuint32_t GRP1PRI :2;

+      vuint32_t GRP0PRI :2;

+      vuint32_t EMLM :1;

+      vuint32_t CLM :1;

+      vuint32_t HALT :1;

+      vuint32_t HOE :1;

+      vuint32_t ERGA :1;

+      vuint32_t ERCA :1;

+      vuint32_t EDBG :1;

+      vuint32_t :1;

+    } B;

+  } CR; /* DMA Control Register @baseaddress + 0x0 */

+

+  union {

+    vuint32_t R;

+    struct {

+      vuint32_t VLD :1;

+      vuint32_t :14;

+      vuint32_t ECX :1;

+      vuint32_t GPE :1;

+      vuint32_t CPE :1;

+      vuint32_t ERRCHN :6;

+      vuint32_t SAE :1;

+      vuint32_t SOE :1;

+      vuint32_t DAE :1;

+      vuint32_t DOE :1;

+      vuint32_t NCE :1;

+      vuint32_t SGE :1;

+      vuint32_t SBE :1;

+      vuint32_t DBE :1;

+    } B;

+  } ESR; /* Error Status Register @baseaddress + 0x4 */

+

+  union {

+    vuint32_t R;

+    struct {

+      vuint32_t ERQ63 :1;

+      vuint32_t ERQ62 :1;

+      vuint32_t ERQ61 :1;

+      vuint32_t ERQ60 :1;

+      vuint32_t ERQ59 :1;

+      vuint32_t ERQ58 :1;

+      vuint32_t ERQ57 :1;

+      vuint32_t ERQ56 :1;

+      vuint32_t ERQ55 :1;

+      vuint32_t ERQ54 :1;

+      vuint32_t ERQ53 :1;

+      vuint32_t ERQ52 :1;

+      vuint32_t ERQ51 :1;

+      vuint32_t ERQ50 :1;

+      vuint32_t ERQ49 :1;

+      vuint32_t ERQ48 :1;

+      vuint32_t ERQ47 :1;

+      vuint32_t ERQ46 :1;

+      vuint32_t ERQ45 :1;

+      vuint32_t ERQ44 :1;

+      vuint32_t ERQ43 :1;

+      vuint32_t ERQ42 :1;

+      vuint32_t ERQ41 :1;

+      vuint32_t ERQ40 :1;

+      vuint32_t ERQ39 :1;

+      vuint32_t ERQ38 :1;

+      vuint32_t ERQ37 :1;

+      vuint32_t ERQ36 :1;

+      vuint32_t ERQ35 :1;

+      vuint32_t ERQ34 :1;

+      vuint32_t ERQ33 :1;

+      vuint32_t ERQ32 :1;

+    } B;

+  } ERQRH; /* DMA Enable Request Register High @baseaddress + 0x8*/

+

+  union {

+    vuint32_t R;

+    struct {

+      vuint32_t ERQ31 :1;

+      vuint32_t ERQ30 :1;

+      vuint32_t ERQ29 :1;

+      vuint32_t ERQ28 :1;

+      vuint32_t ERQ27 :1;

+      vuint32_t ERQ26 :1;

+      vuint32_t ERQ25 :1;

+      vuint32_t ERQ24 :1;

+      vuint32_t ERQ23 :1;

+      vuint32_t ERQ22 :1;

+      vuint32_t ERQ21 :1;

+      vuint32_t ERQ20 :1;

+      vuint32_t ERQ19 :1;

+      vuint32_t ERQ18 :1;

+      vuint32_t ERQ17 :1;

+      vuint32_t ERQ16 :1;

+      vuint32_t ERQ15 :1;

+      vuint32_t ERQ14 :1;

+      vuint32_t ERQ13 :1;

+      vuint32_t ERQ12 :1;

+      vuint32_t ERQ11 :1;

+      vuint32_t ERQ10 :1;

+      vuint32_t ERQ09 :1;

+      vuint32_t ERQ08 :1;

+      vuint32_t ERQ07 :1;

+      vuint32_t ERQ06 :1;

+      vuint32_t ERQ05 :1;

+      vuint32_t ERQ04 :1;

+      vuint32_t ERQ03 :1;

+      vuint32_t ERQ02 :1;

+      vuint32_t ERQ01 :1;

+      vuint32_t ERQ00 :1;

+    } B;

+  } ERQRL; /* DMA Enable Request Register Low @baseaddress + 0xC*/

+

+  union {

+    vuint32_t R;

+    struct {

+

+      vuint32_t EEI63 :1;

+      vuint32_t EEI62 :1;

+      vuint32_t EEI61 :1;

+      vuint32_t EEI60 :1;

+      vuint32_t EEI59 :1;

+      vuint32_t EEI58 :1;

+      vuint32_t EEI57 :1;

+      vuint32_t EEI56 :1;

+      vuint32_t EEI55 :1;

+      vuint32_t EEI54 :1;

+      vuint32_t EEI53 :1;

+      vuint32_t EEI52 :1;

+      vuint32_t EEI51 :1;

+      vuint32_t EEI50 :1;

+      vuint32_t EEI49 :1;

+      vuint32_t EEI48 :1;

+      vuint32_t EEI47 :1;

+      vuint32_t EEI46 :1;

+      vuint32_t EEI45 :1;

+      vuint32_t EEI44 :1;

+      vuint32_t EEI43 :1;

+      vuint32_t EEI42 :1;

+      vuint32_t EEI41 :1;

+      vuint32_t EEI40 :1;

+      vuint32_t EEI39 :1;

+      vuint32_t EEI38 :1;

+      vuint32_t EEI37 :1;

+      vuint32_t EEI36 :1;

+      vuint32_t EEI35 :1;

+      vuint32_t EEI34 :1;

+      vuint32_t EEI33 :1;

+      vuint32_t EEI32 :1;

+    } B;

+  } EEIRH; /* DMA Enable Error Interrupt Register High @baseaddress + 0x10*/

+

+  union {

+    vuint32_t R;

+    struct {

+      vuint32_t EEI31 :1;

+      vuint32_t EEI30 :1;

+      vuint32_t EEI29 :1;

+      vuint32_t EEI28 :1;

+      vuint32_t EEI27 :1;

+      vuint32_t EEI26 :1;

+      vuint32_t EEI25 :1;

+      vuint32_t EEI24 :1;

+      vuint32_t EEI23 :1;

+      vuint32_t EEI22 :1;

+      vuint32_t EEI21 :1;

+      vuint32_t EEI20 :1;

+      vuint32_t EEI19 :1;

+      vuint32_t EEI18 :1;

+      vuint32_t EEI17 :1;

+      vuint32_t EEI16 :1;

+      vuint32_t EEI15 :1;

+      vuint32_t EEI14 :1;

+      vuint32_t EEI13 :1;

+      vuint32_t EEI12 :1;

+      vuint32_t EEI11 :1;

+      vuint32_t EEI10 :1;

+      vuint32_t EEI09 :1;

+      vuint32_t EEI08 :1;

+      vuint32_t EEI07 :1;

+      vuint32_t EEI06 :1;

+      vuint32_t EEI05 :1;

+      vuint32_t EEI04 :1;

+      vuint32_t EEI03 :1;

+      vuint32_t EEI02 :1;

+      vuint32_t EEI01 :1;

+      vuint32_t EEI00 :1;

+    } B;

+  } EEIRL; /* DMA Enable Error Interrupt Register Low @baseaddress + 0x14*/

+

+  union {

+    vuint8_t R;

+    struct {

+      vuint8_t NOP :1;

+      vuint8_t SERQ :7;

+    } B;

+  } SERQR; /* DMA Set Enable Request Register @baseaddress + 0x18*/

+

+  union {

+    vuint8_t R;

+    struct {

+      vuint8_t NOP :1;

+      vuint8_t CERQ :7;

+    } B;

+  } CERQR; /* DMA Clear Enable Request Register @baseaddress + 0x19*/

+

+  union {

+    vuint8_t R;

+    struct {

+      vuint8_t NOP :1;

+      vuint8_t SEEI :7;

+    } B;

+  } SEEIR; /* DMA Set Enable Error Interrupt Register @baseaddress + 0x1A*/

+

+  union {

+    vuint8_t R;

+    struct {

+      vuint8_t NOP :1;

+      vuint8_t CEEI :7;

+    } B;

+  } CEEIR; /* DMA Clear Enable Error Interrupt Register @baseaddress + 0x1B*/

+

+  union {

+    vuint8_t R;

+    struct {

+      vuint8_t NOP :1;

+      vuint8_t CINT :7;

+    } B;

+  } CIRQR; /* DMA Clear Interrupt Request Register @baseaddress + 0x1C */

+

+  union {

+    vuint8_t R;

+    struct {

+      vuint8_t NOP :1;

+      vuint8_t CERR :7;

+    } B;

+  } CER; /* DMA Clear error Register @baseaddress + 0x1D */

+

+  union {

+    vuint8_t R;

+    struct {

+      vuint8_t NOP :1;

+      vuint8_t SSB :7;

+    } B;

+  } SSBR; /* Set Start Bit Register @baseaddress + 0x1E */

+

+  union {

+    vuint8_t R;

+    struct {

+      vuint8_t NOP :1;

+      vuint8_t CDSB :7;

+    } B;

+  } CDSBR; /* Clear Done Status Bit Register @baseaddress + 0x1F */

+

+  union {

+    vuint32_t R;

+    struct {

+      vuint32_t INT63 :1;

+      vuint32_t INT62 :1;

+      vuint32_t INT61 :1;

+      vuint32_t INT60 :1;

+      vuint32_t INT59 :1;

+      vuint32_t INT58 :1;

+      vuint32_t INT57 :1;

+      vuint32_t INT56 :1;

+      vuint32_t INT55 :1;

+      vuint32_t INT54 :1;

+      vuint32_t INT53 :1;

+      vuint32_t INT52 :1;

+      vuint32_t INT51 :1;

+      vuint32_t INT50 :1;

+      vuint32_t INT49 :1;

+      vuint32_t INT48 :1;

+      vuint32_t INT47 :1;

+      vuint32_t INT46 :1;

+      vuint32_t INT45 :1;

+      vuint32_t INT44 :1;

+      vuint32_t INT43 :1;

+      vuint32_t INT42 :1;

+      vuint32_t INT41 :1;

+      vuint32_t INT40 :1;

+      vuint32_t INT39 :1;

+      vuint32_t INT38 :1;

+      vuint32_t INT37 :1;

+      vuint32_t INT36 :1;

+      vuint32_t INT35 :1;

+      vuint32_t INT34 :1;

+      vuint32_t INT33 :1;

+      vuint32_t INT32 :1;

+    } B;

+  } IRQRH; /* DMA Interrupt Request High @baseaddress + 0x20 */

+

+  union {

+    vuint32_t R;

+    struct {

+      vuint32_t INT31 :1;

+      vuint32_t INT30 :1;

+      vuint32_t INT29 :1;

+      vuint32_t INT28 :1;

+      vuint32_t INT27 :1;

+      vuint32_t INT26 :1;

+      vuint32_t INT25 :1;

+      vuint32_t INT24 :1;

+      vuint32_t INT23 :1;

+      vuint32_t INT22 :1;

+      vuint32_t INT21 :1;

+      vuint32_t INT20 :1;

+      vuint32_t INT19 :1;

+      vuint32_t INT18 :1;

+      vuint32_t INT17 :1;

+      vuint32_t INT16 :1;

+      vuint32_t INT15 :1;

+      vuint32_t INT14 :1;

+      vuint32_t INT13 :1;

+      vuint32_t INT12 :1;

+      vuint32_t INT11 :1;

+      vuint32_t INT10 :1;

+      vuint32_t INT09 :1;

+      vuint32_t INT08 :1;

+      vuint32_t INT07 :1;

+      vuint32_t INT06 :1;

+      vuint32_t INT05 :1;

+      vuint32_t INT04 :1;

+      vuint32_t INT03 :1;

+      vuint32_t INT02 :1;

+      vuint32_t INT01 :1;

+      vuint32_t INT00 :1;

+    } B;

+  } IRQRL; /* DMA Interrupt Request Low @baseaddress + 0x24 */

+

+  union {

+    vuint32_t R;

+    struct {

+      vuint32_t ERR63 :1;

+      vuint32_t ERR62 :1;

+      vuint32_t ERR61 :1;

+      vuint32_t ERR60 :1;

+      vuint32_t ERR59 :1;

+      vuint32_t ERR58 :1;

+      vuint32_t ERR57 :1;

+      vuint32_t ERR56 :1;

+      vuint32_t ERR55 :1;

+      vuint32_t ERR54 :1;

+      vuint32_t ERR53 :1;

+      vuint32_t ERR52 :1;

+      vuint32_t ERR51 :1;

+      vuint32_t ERR50 :1;

+      vuint32_t ERR49 :1;

+      vuint32_t ERR48 :1;

+      vuint32_t ERR47 :1;

+      vuint32_t ERR46 :1;

+      vuint32_t ERR45 :1;

+      vuint32_t ERR44 :1;

+      vuint32_t ERR43 :1;

+      vuint32_t ERR42 :1;

+      vuint32_t ERR41 :1;

+      vuint32_t ERR40 :1;

+      vuint32_t ERR39 :1;

+      vuint32_t ERR38 :1;

+      vuint32_t ERR37 :1;

+      vuint32_t ERR36 :1;

+      vuint32_t ERR35 :1;

+      vuint32_t ERR34 :1;

+      vuint32_t ERR33 :1;

+      vuint32_t ERR32 :1;

+    } B;

+  } ERH; /* DMA Error High @baseaddress + 0x28 */

+

+  union {

+    vuint32_t R;

+    struct {

+      vuint32_t ERR31 :1;

+      vuint32_t ERR30 :1;

+      vuint32_t ERR29 :1;

+      vuint32_t ERR28 :1;

+      vuint32_t ERR27 :1;

+      vuint32_t ERR26 :1;

+      vuint32_t ERR25 :1;

+      vuint32_t ERR24 :1;

+      vuint32_t ERR23 :1;

+      vuint32_t ERR22 :1;

+      vuint32_t ERR21 :1;

+      vuint32_t ERR20 :1;

+      vuint32_t ERR19 :1;

+      vuint32_t ERR18 :1;

+      vuint32_t ERR17 :1;

+      vuint32_t ERR16 :1;

+      vuint32_t ERR15 :1;

+      vuint32_t ERR14 :1;

+      vuint32_t ERR13 :1;

+      vuint32_t ERR12 :1;

+      vuint32_t ERR11 :1;

+      vuint32_t ERR10 :1;

+      vuint32_t ERR09 :1;

+      vuint32_t ERR08 :1;

+      vuint32_t ERR07 :1;

+      vuint32_t ERR06 :1;

+      vuint32_t ERR05 :1;

+      vuint32_t ERR04 :1;

+      vuint32_t ERR03 :1;

+      vuint32_t ERR02 :1;

+      vuint32_t ERR01 :1;

+      vuint32_t ERR00 :1;

+    } B;

+  } ERL; /* DMA Error Low @baseaddress + 0x2C */

+

+  union {

+    vuint32_t R;

+    struct {

+      vuint32_t HRS63 :1;

+      vuint32_t HRS62 :1;

+      vuint32_t HRS61 :1;

+      vuint32_t HRS60 :1;

+      vuint32_t HRS59 :1;

+      vuint32_t HRS58 :1;

+      vuint32_t HRS57 :1;

+      vuint32_t HRS56 :1;

+      vuint32_t HRS55 :1;

+      vuint32_t HRS54 :1;

+      vuint32_t HRS53 :1;

+      vuint32_t HRS52 :1;

+      vuint32_t HRS51 :1;

+      vuint32_t HRS50 :1;

+      vuint32_t HRS49 :1;

+      vuint32_t HRS48 :1;

+      vuint32_t HRS47 :1;

+      vuint32_t HRS46 :1;

+      vuint32_t HRS45 :1;

+      vuint32_t HRS44 :1;

+      vuint32_t HRS43 :1;

+      vuint32_t HRS42 :1;

+      vuint32_t HRS41 :1;

+      vuint32_t HRS40 :1;

+      vuint32_t HRS39 :1;

+      vuint32_t HRS38 :1;

+      vuint32_t HRS37 :1;

+      vuint32_t HRS36 :1;

+      vuint32_t HRS35 :1;

+      vuint32_t HRS34 :1;

+      vuint32_t HRS33 :1;

+      vuint32_t HRS32 :1;

+    } B;

+  } HRSH; /* hardware request status high @baseaddress + 0x30 */

+

+  union {

+    vuint32_t R;

+    struct {

+      vuint32_t HRS31 :1;

+      vuint32_t HRS30 :1;

+      vuint32_t HRS29 :1;

+      vuint32_t HRS28 :1;

+      vuint32_t HRS27 :1;

+      vuint32_t HRS26 :1;

+      vuint32_t HRS25 :1;

+      vuint32_t HRS24 :1;

+      vuint32_t HRS23 :1;

+      vuint32_t HRS22 :1;

+      vuint32_t HRS21 :1;

+      vuint32_t HRS20 :1;

+      vuint32_t HRS19 :1;

+      vuint32_t HRS18 :1;

+      vuint32_t HRS17 :1;

+      vuint32_t HRS16 :1;

+      vuint32_t HRS15 :1;

+      vuint32_t HRS14 :1;

+      vuint32_t HRS13 :1;

+      vuint32_t HRS12 :1;

+      vuint32_t HRS11 :1;

+      vuint32_t HRS10 :1;

+      vuint32_t HRS09 :1;

+      vuint32_t HRS08 :1;

+      vuint32_t HRS07 :1;

+      vuint32_t HRS06 :1;

+      vuint32_t HRS05 :1;

+      vuint32_t HRS04 :1;

+      vuint32_t HRS03 :1;

+      vuint32_t HRS02 :1;

+      vuint32_t HRS01 :1;

+      vuint32_t HRS00 :1;

+    } B;

+  } HRSL; /* hardware request status low @baseaddress + 0x34 */

+

+  uint32_t eDMA_reserved0038[50]; /* 0x0038-0x00FF */

+

+  union {

+    vuint8_t R;

+    struct {

+      vuint8_t ECP :1;

+      vuint8_t DPA :1;

+      vuint8_t GRPPRI :2;

+      vuint8_t CHPRI :4;

+    } B;

+  } CPR[64]; /* Channel n Priority @baseaddress + 0x100 */

+

+  uint32_t eDMA_reserved0140[944]; /* 0x0140-0x0FFF */

+

+  edma_tcd_t TCD[64];

+} edma_t;

+

+/**

  * @brief   DMA callback type.

  *

  * @param[in] channel   the channel number

@@ -137,6 +645,15 @@ typedef struct {
 /*===========================================================================*/

 

 /**

+ * @name    eDMA units references

+ * @{

+ */

+#if SPC5_HAS_EDMAA || defined(__DOXYGEN__)

+#define SPC5_EDMAA      (*(edma_t *)0xFFF44000U)

+#endif

+/** @} */

+

+/**

  * @brief   Returns the TCD address associated to a channel.

  *

  * @param[in] channel   the channel number

@@ -308,6 +825,6 @@ extern "C" {
 }

 #endif

 

-#endif /* _EDMA_H_ */

+#endif /* _SPC5_EDMA_H_ */

 

 /** @} */