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author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-02-12 13:55:04 +0000 |
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committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-02-12 13:55:04 +0000 |
commit | 93dd0e239e757655b9c20a1d89b0228bc271f86b (patch) | |
tree | 0ca200a74041568b63d4e0c5d41e21546c29dec4 /os | |
parent | 4495dae0e8c418da4868ac671088190875af9180 (diff) | |
download | ChibiOS-93dd0e239e757655b9c20a1d89b0228bc271f86b.tar.gz ChibiOS-93dd0e239e757655b9c20a1d89b0228bc271f86b.tar.bz2 ChibiOS-93dd0e239e757655b9c20a1d89b0228bc271f86b.zip |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5164 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
-rw-r--r-- | os/hal/platforms/SPC56ELxx/hal_lld.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/os/hal/platforms/SPC56ELxx/hal_lld.c b/os/hal/platforms/SPC56ELxx/hal_lld.c index 9d2f82974..32915f161 100644 --- a/os/hal/platforms/SPC56ELxx/hal_lld.c +++ b/os/hal/platforms/SPC56ELxx/hal_lld.c @@ -160,22 +160,24 @@ void spc_early_init(void) { CGM.AC3_SC.R = SPC5_FMPLL0_CLK_SRC;
CGM.AC4_SC.R = SPC5_FMPLL1_CLK_SRC;
- /* Enables the XOSC in order to check its functionality.*/
+ /* Enables the XOSC in order to check its functionality before proceeding
+ with the initialization.*/
ME.DRUN.R = SPC5_ME_MC_SYSCLK_IRC | SPC5_ME_MC_IRCON | SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_FLAON_NORMAL | SPC5_ME_MC_MVRON;
if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED) {
SPC5_CLOCK_FAILURE_HOOK();
}
- /* Initialization of the FMPLLs settings.*/
+ /* Initialization of the FMPLLs settings.
+ TODO: Add settings for the MR registers.*/
CGM.FMPLL[0].CR.R = SPC5_FMPLL0_ODF |
((SPC5_FMPLL0_IDF_VALUE - 1) << 26) |
(SPC5_FMPLL0_NDIV_VALUE << 16);
- CGM.FMPLL[0].MR.R = 0; /* TODO: Add a setting. */
+ CGM.FMPLL[0].MR.R = 0;
CGM.FMPLL[1].CR.R = SPC5_FMPLL1_ODF |
((SPC5_FMPLL1_IDF_VALUE - 1) << 26) |
(SPC5_FMPLL1_NDIV_VALUE << 16);
- CGM.FMPLL[1].MR.R = 0; /* TODO: Add a setting. */
+ CGM.FMPLL[1].MR.R = 0;
/* Run modes initialization, note writes to the MC registers are verified
by a protection mechanism, the operation success is verified at the
@@ -213,7 +215,7 @@ void spc_early_init(void) { ME.LPPC[6].R = SPC5_ME_LP_PC6_BITS;
ME.LPPC[7].R = SPC5_ME_LP_PC7_BITS;
- /* CFLASH settings calculated for a maximum clock of 120MHz.*/
+ /* CFLASH settings initialized for a maximum clock of 120MHz.*/
CFLASH.PFCR0.B.B02_APC = 3;
CFLASH.PFCR0.B.B02_WWSC = 3;
CFLASH.PFCR0.B.B02_RWSC = 3;
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