EQADC driver starts responding.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5382 35acf78f-673a-0410-8e92-d51de3d6d3f4

2 files changed, 19 insertions, 12 deletions

diff --git a/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c b/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c
index 1de887ab7..96a527b61 100644
--- a/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c
+++ b/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c
@@ -619,10 +619,6 @@ void adc_lld_start(ADCDriver *adcp) {
   chDbgAssert((adcp->cfifo_channel != EDMA_ERROR) &&

               (adcp->rfifo_channel != EDMA_ERROR),

               "adc_lld_start(), #2", "channel cannot be allocated");

-

-  /* HW triggers setup.*/

-  SIU.ETISR.R = adcp->config->etisr;

-  SIU.ISEL3.R = adcp->config->isel3;

 }

 

 /**

@@ -660,6 +656,7 @@ void adc_lld_stop(ADCDriver *adcp) {
  * @notapi

  */

 void adc_lld_start_conversion(ADCDriver *adcp) {

+  uint32_t bitoff;

 

   chDbgAssert(adcp->grpp->num_iterations >= adcp->depth,

               "adc_lld_start_conversion(), #1", "too many elements");

@@ -699,6 +696,15 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
                    EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END |

                    ((adcp->depth > 1) ? EDMA_TCD_MODE_INT_HALF: 0));/* mode.*/

 

+

+  /* HW triggers setup.*/

+  bitoff = 20 + ((uint32_t)adcp->fifo * 2);

+  SIU.ETISR.R = (SIU.ETISR.R & ~(3U << bitoff)) |

+                (adcp->grpp->tsel << bitoff);

+  bitoff = (uint32_t)adcp->fifo * 5;

+  SIU.ISEL3.R = (SIU.ISEL3.R & ~(31U << bitoff)) |

+                (adcp->grpp->etsel << bitoff);

+

   /* Starting DMA channels.*/

   edmaChannelStart(adcp->rfifo_channel);

   edmaChannelStart(adcp->cfifo_channel);

diff --git a/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h b/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h
index 98bf63c12..7c04fa56a 100644
--- a/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h
+++ b/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h
@@ -554,6 +554,14 @@ typedef struct {
    */

   uint16_t                  cfcr;

   /**

+   * @brief   SIU ETISR.TSEL value for this queue;

+   */

+  uint8_t                   tsel;

+  /**

+   * @brief   SIU ISEL3.ETSEL value for this queue;

+   */

+  uint8_t                   etsel;

+  /**

    * @brief   Number of command iterations stored in @p commands.

    * @note    The total number of array elements must be @p num_channels *

    *          @p num_iterations.

@@ -574,14 +582,7 @@ typedef struct {
  * @note    It could be empty on some architectures.

  */

 typedef struct {

-  /**

-   * @brief   ETISR register value for the session.

-   */

-  uint32_t                  etisr;

-  /**

-   * @brief   ISEL3 register value for the session.

-   */

-  uint32_t                  isel3;

+  uint32_t                  dummy;

 } ADCConfig;

 

 /**