diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-10-02 10:03:05 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-10-02 10:03:05 +0000 |
| commit | 83e3dc01ad0b5e2d7d18b53a9bbf69d9fdbb68d7 (patch) | |
| tree | ee3e8b33246d1d1a5b3ddaffd6109b4f74cf9c38 /os | |
| parent | 469c8c4377a57fca9b5eb1a2fffa2e8e28c63c1b (diff) | |
| download | ChibiOS-83e3dc01ad0b5e2d7d18b53a9bbf69d9fdbb68d7.tar.gz ChibiOS-83e3dc01ad0b5e2d7d18b53a9bbf69d9fdbb68d7.tar.bz2 ChibiOS-83e3dc01ad0b5e2d7d18b53a9bbf69d9fdbb68d7.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6345 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
| -rw-r--r-- | os/hal/ports/STM32F0xx/hal_lld.h | 5 | ||||
| -rw-r--r-- | os/hal/ports/STM32F1xx/hal_lld.h | 67 | ||||
| -rw-r--r-- | os/hal/ports/STM32F1xx/stm32_isr.h | 142 | ||||
| -rw-r--r-- | os/hal/ports/STM32F1xx/stm32_registry.h | 1070 | ||||
| -rw-r--r-- | os/hal/ports/STM32F30x/hal_lld.h | 5 | ||||
| -rw-r--r-- | os/hal/ports/STM32F37x/hal_lld.h | 5 | ||||
| -rw-r--r-- | os/hal/ports/STM32F4xx/hal_lld.h | 5 | ||||
| -rw-r--r-- | os/hal/ports/STM32L1xx/hal_lld.h | 5 |
8 files changed, 1138 insertions, 166 deletions
diff --git a/os/hal/ports/STM32F0xx/hal_lld.h b/os/hal/ports/STM32F0xx/hal_lld.h index 9ab7f08dd..99fb5bd28 100644 --- a/os/hal/ports/STM32F0xx/hal_lld.h +++ b/os/hal/ports/STM32F0xx/hal_lld.h @@ -44,11 +44,6 @@ /*===========================================================================*/
/**
- * @brief Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS FALSE
-
-/**
* @name Platform identification
* @{
*/
diff --git a/os/hal/ports/STM32F1xx/hal_lld.h b/os/hal/ports/STM32F1xx/hal_lld.h index 7b34b2aab..4c3734da7 100644 --- a/os/hal/ports/STM32F1xx/hal_lld.h +++ b/os/hal/ports/STM32F1xx/hal_lld.h @@ -41,18 +41,11 @@ #ifndef _HAL_LLD_H_
#define _HAL_LLD_H_
-#include "stm32.h"
-
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
- * @brief Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS TRUE
-
-/**
* @name Internal clock sources
* @{
*/
@@ -79,16 +72,6 @@ /* Platform capabilities. */
/*===========================================================================*/
-/**
- * @name STM32F1xx capabilities
- * @{
- */
-/* RTC attributes.*/
-#define STM32_HAS_RTC TRUE
-#define STM32_RTC_HAS_SUBSECONDS TRUE
-#define STM32_RTC_IS_CALENDAR FALSE
-/** @} */
-
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@@ -175,64 +158,14 @@ #error "unspecified, unsupported or invalid STM32 platform"
#endif
-/* There are differences in vector names in the various sub-families,
- normalizing.*/
-#if defined(STM32F10X_XL)
-#define TIM1_BRK_IRQn TIM1_BRK_TIM9_IRQn
-#define TIM1_UP_IRQn TIM1_UP_TIM10_IRQn
-#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM11_IRQn
-#define TIM8_BRK_IRQn TIM8_BRK_TIM12_IRQn
-#define TIM8_UP_IRQn TIM8_UP_TIM13_IRQn
-#define TIM8_TRG_COM_IRQn TIM8_TRG_COM_TIM14_IRQn
-
-#elif defined(STM32F10X_LD_VL)|| defined(STM32F10X_MD_VL) || \
- defined(STM32F10X_HD_VL)
-#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
-#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn
-#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
-#endif
-
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
-/**
- * @brief Type representing a system clock frequency.
- */
-typedef uint32_t halclock_t;
-
-/**
- * @brief Type of the realtime free counter value.
- */
-typedef uint32_t halrtcnt_t;
-
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
-/**
- * @brief Returns the current value of the system free running counter.
- * @note This service is implemented by returning the content of the
- * DWT_CYCCNT register.
- *
- * @return The value of the system free running counter of
- * type halrtcnt_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_value() DWT_CYCCNT
-
-/**
- * @brief Realtime counter frequency.
- * @note The DWT_CYCCNT register is incremented directly by the system
- * clock so this function returns STM32_HCLK.
- *
- * @return The realtime counter frequency of type halclock_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_frequency() STM32_HCLK
-
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
diff --git a/os/hal/ports/STM32F1xx/stm32_isr.h b/os/hal/ports/STM32F1xx/stm32_isr.h index 97a79e337..892fa0f9d 100644 --- a/os/hal/ports/STM32F1xx/stm32_isr.h +++ b/os/hal/ports/STM32F1xx/stm32_isr.h @@ -36,96 +36,90 @@ /*
* CAN units.
*/
-#define STM32_CAN1_TX_HANDLER CAN1_TX_IRQHandler
-#define STM32_CAN1_RX0_HANDLER CAN1_RX0_IRQHandler
-#define STM32_CAN1_RX1_HANDLER CAN1_RX1_IRQHandler
-#define STM32_CAN1_SCE_HANDLER CAN1_SCE_IRQHandler
-#define STM32_CAN2_TX_HANDLER CAN2_TX_IRQHandler
-#define STM32_CAN2_RX0_HANDLER CAN2_RX0_IRQHandler
-#define STM32_CAN2_RX1_HANDLER CAN2_RX1_IRQHandler
-#define STM32_CAN2_SCE_HANDLER CAN2_SCE_IRQHandler
-
-#ifdef STM32F10X_CL
-#define STM32_CAN1_TX_NUMBER CAN1_TX_IRQn
-#define STM32_CAN1_RX0_NUMBER CAN1_RX0_IRQn
-#else
-#define STM32_CAN1_TX_NUMBER USB_HP_CAN1_TX_IRQn
-#define STM32_CAN1_RX0_NUMBER USB_LP_CAN1_RX0_IRQn
-#endif
-#define STM32_CAN1_RX1_NUMBER CAN1_RX1_IRQn
-#define STM32_CAN1_SCE_NUMBER CAN1_SCE_IRQn
-#define STM32_CAN2_TX_NUMBER CAN2_TX_IRQn
-#define STM32_CAN2_RX0_NUMBER CAN2_RX0_IRQn
-#define STM32_CAN2_RX1_NUMBER CAN2_RX1_IRQn
-#define STM32_CAN2_SCE_NUMBER CAN2_SCE_IRQn
+#define STM32_CAN1_TX_HANDLER Vector8C
+#define STM32_CAN1_RX0_HANDLER Vector90
+#define STM32_CAN1_RX1_HANDLER Vector94
+#define STM32_CAN1_SCE_HANDLER Vector98
+#define STM32_CAN2_TX_HANDLER Vector13C
+#define STM32_CAN2_RX0_HANDLER Vector140
+#define STM32_CAN2_RX1_HANDLER Vector144
+#define STM32_CAN2_SCE_HANDLER Vector148
+
+#define STM32_CAN1_TX_NUMBER 19
+#define STM32_CAN1_RX0_NUMBER 20
+#define STM32_CAN1_RX1_NUMBER 21
+#define STM32_CAN1_SCE_NUMBER 22
+#define STM32_CAN2_TX_NUMBER 63
+#define STM32_CAN2_RX0_NUMBER 64
+#define STM32_CAN2_RX1_NUMBER 65
+#define STM32_CAN2_SCE_NUMBER 66
+
+/*
+ * I2C units.
+ */
+#define STM32_I2C1_EVENT_HANDLER VectorBC
+#define STM32_I2C1_ERROR_HANDLER VectorC0
+#define STM32_I2C1_EVENT_NUMBER 31
+#define STM32_I2C1_ERROR_NUMBER 32
+
+#define STM32_I2C2_EVENT_HANDLER VectorC4
+#define STM32_I2C2_ERROR_HANDLER VectorC8
+#define STM32_I2C2_EVENT_NUMBER 33
+#define STM32_I2C2_ERROR_NUMBER 34
/*
* OTG units.
*/
-#define STM32_OTG1_HANDLER OTG_FS_IRQHandler
+#define STM32_OTG1_HANDLER Vector14C
-#define STM32_OTG1_NUMBER OTG_FS_IRQn
+#define STM32_OTG1_NUMBER 67
/*
* SDIO unit.
*/
-#define STM32_SDIO_HANDLER SDIO_IRQHandler
+#define STM32_SDIO_HANDLER Vector104
-#define STM32_SDIO_NUMBER SDIO_IRQn
+#define STM32_SDIO_NUMBER 49
/*
* TIM units.
*/
-#if defined(STM32F10X_XL)
-#define STM32_TIM1_UP_HANDLER TIM1_UP_IRQHandler
-#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
- defined(STM32F10X_HD_VL)
-#define STM32_TIM1_UP_HANDLER TIM1_UP_IRQHandler
-#else
-#define STM32_TIM1_UP_HANDLER TIM1_UP_IRQHandler
-#endif
-#define STM32_TIM1_CC_HANDLER TIM1_CC_IRQHandler
-#define STM32_TIM2_HANDLER TIM2_IRQHandler
-#define STM32_TIM3_HANDLER TIM3_IRQHandler
-#define STM32_TIM4_HANDLER TIM4_IRQHandler
-#define STM32_TIM5_HANDLER TIM5_IRQHandler
-#define STM32_TIM8_UP_HANDLER TIM8_UP_IRQHandler
-#define STM32_TIM8_CC_HANDLER TIM8_CC_IRQHandler
-
-#if defined(STM32F10X_XL)
-#define STM32_TIM1_UP_NUMBER TIM1_UP_TIM10_IRQn
-#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
- defined(STM32F10X_HD_VL)
-#define STM32_TIM1_UP_NUMBER TIM1_UP_TIM16_IRQn
-#else
-#define STM32_TIM1_UP_NUMBER TIM1_UP_IRQn
-#endif
-#define STM32_TIM1_CC_NUMBER TIM1_CC_IRQn
-#define STM32_TIM2_NUMBER TIM2_IRQn
-#define STM32_TIM3_NUMBER TIM3_IRQn
-#define STM32_TIM4_NUMBER TIM4_IRQn
-#define STM32_TIM5_NUMBER TIM5_IRQn
-#ifdef STM32F10X_XL
-#define STM32_TIM8_UP_NUMBER TIM8_UP_TIM13_IRQn
-#else
-#define STM32_TIM8_UP_NUMBER TIM8_UP_IRQn
-#endif
-#define STM32_TIM8_CC_NUMBER TIM8_CC_IRQn
+#define STM32_TIM1_UP_HANDLER VectorA4
+#define STM32_TIM1_CC_HANDLER VectorAC
+#define STM32_TIM2_HANDLER VectorB0
+#define STM32_TIM3_HANDLER VectorB4
+#define STM32_TIM4_HANDLER VectorB8
+#define STM32_TIM5_HANDLER Vector108
+#define STM32_TIM6_HANDLER Vector118
+#define STM32_TIM7_HANDLER Vector11C
+#define STM32_TIM8_UP_HANDLER VectorF0
+#define STM32_TIM8_CC_HANDLER VectorF8
+
+#define STM32_TIM1_UP_NUMBER 25
+#define STM32_TIM1_CC_NUMBER 27
+#define STM32_TIM2_NUMBER 28
+#define STM32_TIM3_NUMBER 29
+#define STM32_TIM4_NUMBER 30
+#define STM32_TIM5_NUMBER 50
+#define STM32_TIM6_NUMBER 54
+#define STM32_TIM7_NUMBER 55
+#define STM32_TIM8_UP_NUMBER 44
+#define STM32_TIM8_CC_NUMBER 46
/*
* USART units.
*/
-#define STM32_USART1_HANDLER USART1_IRQHandler
-#define STM32_USART2_HANDLER USART2_IRQHandler
-#define STM32_USART3_HANDLER USART3_IRQHandler
-#define STM32_UART4_HANDLER UART4_IRQHandler
-#define STM32_UART5_HANDLER UART5_IRQHandler
-
-#define STM32_USART1_NUMBER USART1_IRQn
-#define STM32_USART2_NUMBER USART2_IRQn
-#define STM32_USART3_NUMBER USART3_IRQn
-#define STM32_UART4_NUMBER UART4_IRQn
-#define STM32_UART5_NUMBER UART5_IRQn
+#define STM32_USART1_HANDLER VectorD4
+#define STM32_USART2_HANDLER VectorD8
+#define STM32_USART3_HANDLER VectorDC
+#define STM32_UART4_HANDLER Vector110
+#define STM32_UART5_HANDLER Vector114
+
+#define STM32_USART1_NUMBER 37
+#define STM32_USART2_NUMBER 38
+#define STM32_USART3_NUMBER 39
+#define STM32_UART4_NUMBER 52
+#define STM32_UART5_NUMBER 53
/*
* USB units.
@@ -133,8 +127,8 @@ #define STM32_USB1_HP_HANDLER Vector8C
#define STM32_USB1_LP_HANDLER Vector90
-#define STM32_USB1_HP_NUMBER USB_HP_CAN1_TX_IRQn
-#define STM32_USB1_LP_NUMBER USB_LP_CAN1_RX0_IRQn
+#define STM32_USB1_HP_NUMBER 19
+#define STM32_USB1_LP_NUMBER 20
/** @} */
/*===========================================================================*/
diff --git a/os/hal/ports/STM32F1xx/stm32_registry.h b/os/hal/ports/STM32F1xx/stm32_registry.h new file mode 100644 index 000000000..7cbf36496 --- /dev/null +++ b/os/hal/ports/STM32F1xx/stm32_registry.h @@ -0,0 +1,1070 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F1xx/stm32_registry.h
+ * @brief STM32F1xx capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _STM32_REGISTRY_H_
+#define _STM32_REGISTRY_H_
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+#if defined(STM32F10X_LD_VL) || defined(__DOXYGEN__)
+/**
+ * @name STM32F100 LD capabilities
+ * @{
+ */
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 FALSE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_CAN_MAX_FILTERS 0
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1 TRUE
+#define STM32_HAS_DAC2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_HAS_DMA1 TRUE
+#define STM32_HAS_DMA2 FALSE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS 18
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE FALSE
+#define STM32_HAS_GPIOF FALSE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 FALSE
+#define STM32_HAS_I2C3 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_IS_CALENDAR FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 FALSE
+#define STM32_HAS_SPI3 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 2
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 2
+
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 FALSE
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+/** @} */
+#endif /* defined(STM32F10X_LD_VL) */
+
+#if defined(STM32F10X_MD_VL) || defined(__DOXYGEN__)
+/**
+ * @name STM32F100 MD capabilities
+ * @{
+ */
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 FALSE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_CAN_MAX_FILTERS 0
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1 TRUE
+#define STM32_HAS_DAC2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_HAS_DMA1 TRUE
+#define STM32_HAS_DMA2 FALSE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS 19
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF FALSE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_IS_CALENDAR FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 2
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 2
+
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+/** @} */
+#endif /* defined(STM32F10X_MD_VL) */
+
+#if defined(STM32F10X_LD) || defined(__DOXYGEN__)
+/**
+ * @name STM32F103 LD capabilities
+ * @{
+ */
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_HAS_ADC2 TRUE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1 FALSE
+#define STM32_HAS_DAC2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_HAS_DMA1 TRUE
+#define STM32_HAS_DMA2 FALSE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS 19
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE FALSE
+#define STM32_HAS_GPIOF FALSE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 FALSE
+#define STM32_HAS_I2C3 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_IS_CALENDAR FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 FALSE
+#define STM32_HAS_SPI3 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM6 FALSE
+#define STM32_HAS_TIM7 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM16 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 FALSE
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+/** @} */
+#endif /* defined(STM32F10X_LD) */
+
+#if defined(STM32F10X_MD) || defined(__DOXYGEN__)
+/**
+ * @name STM32F103 MD capabilities
+ * @{
+ */
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_HAS_ADC2 TRUE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1 FALSE
+#define STM32_HAS_DAC2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_HAS_DMA1 TRUE
+#define STM32_HAS_DMA2 FALSE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS 19
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF FALSE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 FALSE
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_IS_CALENDAR FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 FALSE
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM6 FALSE
+#define STM32_HAS_TIM7 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM16 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB TRUE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+/** @} */
+#endif /* defined(STM32F10X_MD) */
+
+#if defined(STM32F10X_HD) || defined(__DOXYGEN__)
+/**
+ * @name STM32F103 HD capabilities
+ * @{
+ */
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_HAS_ADC2 TRUE
+#define STM32_HAS_ADC3 TRUE
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1 TRUE
+#define STM32_HAS_DAC2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_HAS_DMA1 TRUE
+#define STM32_HAS_DMA2 TRUE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS 19
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG TRUE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 FALSE
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_IS_CALENDAR FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO TRUE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 FALSE
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3 FALSE
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM5 TRUE
+#define STM32_TIM5_IS_32BITS FALSE
+#define STM32_TIM5_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM8 TRUE
+#define STM32_TIM8_IS_32BITS FALSE
+#define STM32_TIM8_CHANNELS 4
+
+#define STM32_HAS_TIM9 TRUE
+#define STM32_TIM9_IS_32BITS FALSE
+#define STM32_TIM9_CHANNELS 2
+
+#define STM32_HAS_TIM10 TRUE
+#define STM32_TIM10_IS_32BITS FALSE
+#define STM32_TIM10_CHANNELS 2
+
+#define STM32_HAS_TIM11 TRUE
+#define STM32_TIM11_IS_32BITS FALSE
+#define STM32_TIM11_CHANNELS 2
+
+#define STM32_HAS_TIM12 TRUE
+#define STM32_TIM12_IS_32BITS FALSE
+#define STM32_TIM12_CHANNELS 2
+
+#define STM32_HAS_TIM13 TRUE
+#define STM32_TIM13_IS_32BITS FALSE
+#define STM32_TIM13_CHANNELS 2
+
+#define STM32_HAS_TIM14 TRUE
+#define STM32_TIM14_IS_32BITS FALSE
+#define STM32_TIM14_CHANNELS 2
+
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM16 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB TRUE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+/** @} */
+#endif /* defined(STM32F10X_HD) */
+
+#if defined(STM32F10X_XL) || defined(__DOXYGEN__)
+/**
+ * @name STM32F103 XL capabilities
+ * @{
+ */
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_HAS_ADC2 TRUE
+#define STM32_HAS_ADC3 TRUE
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1 TRUE
+#define STM32_HAS_DAC2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_HAS_DMA1 TRUE
+#define STM32_HAS_DMA2 TRUE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS 19
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG TRUE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 FALSE
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_IS_CALENDAR FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO TRUE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 FALSE
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3 FALSE
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM5 TRUE
+#define STM32_TIM5_IS_32BITS FALSE
+#define STM32_TIM5_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM8 TRUE
+#define STM32_TIM8_IS_32BITS FALSE
+#define STM32_TIM8_CHANNELS 4
+
+#define STM32_HAS_TIM9 TRUE
+#define STM32_TIM9_IS_32BITS FALSE
+#define STM32_TIM9_CHANNELS 2
+
+#define STM32_HAS_TIM10 TRUE
+#define STM32_TIM10_IS_32BITS FALSE
+#define STM32_TIM10_CHANNELS 2
+
+#define STM32_HAS_TIM11 TRUE
+#define STM32_TIM11_IS_32BITS FALSE
+#define STM32_TIM11_CHANNELS 2
+
+#define STM32_HAS_TIM12 TRUE
+#define STM32_TIM12_IS_32BITS FALSE
+#define STM32_TIM12_CHANNELS 2
+
+#define STM32_HAS_TIM13 TRUE
+#define STM32_TIM13_IS_32BITS FALSE
+#define STM32_TIM13_CHANNELS 2
+
+#define STM32_HAS_TIM14 TRUE
+#define STM32_TIM14_IS_32BITS FALSE
+#define STM32_TIM14_CHANNELS 2
+
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM16 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB TRUE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+/** @} */
+#endif /* defined(STM32F10X_XL) */
+
+#if defined(STM32F10X_CL) || defined(__DOXYGEN__)
+/**
+ * @name STM32F105/F107 CL capabilities
+ * @{
+ */
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_HAS_ADC2 TRUE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 TRUE
+#define STM32_CAN_MAX_FILTERS 28
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1 TRUE
+#define STM32_HAS_DAC2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_HAS_DMA1 TRUE
+#define STM32_HAS_DMA2 TRUE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH TRUE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS 20
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF FALSE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 FALSE
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_IS_CALENDAR FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 FALSE
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3 FALSE
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 4
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM5 TRUE
+#define STM32_TIM5_IS_32BITS FALSE
+#define STM32_TIM5_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM16 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+
+#define STM32_HAS_UART5 TRUE
+
+#define STM32_HAS_USART6 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB FALSE
+#define STM32_HAS_OTG1 TRUE
+#define STM32_HAS_OTG2 FALSE
+/** @} */
+#endif /* defined(STM32F10X_CL) */
+
+#endif /* _STM32_REGISTRY_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32F30x/hal_lld.h b/os/hal/ports/STM32F30x/hal_lld.h index f291e8f8a..81f7bf288 100644 --- a/os/hal/ports/STM32F30x/hal_lld.h +++ b/os/hal/ports/STM32F30x/hal_lld.h @@ -43,11 +43,6 @@ /*===========================================================================*/
/**
- * @brief Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS TRUE
-
-/**
* @name Platform identification
* @{
*/
diff --git a/os/hal/ports/STM32F37x/hal_lld.h b/os/hal/ports/STM32F37x/hal_lld.h index efd22043f..728cd152f 100644 --- a/os/hal/ports/STM32F37x/hal_lld.h +++ b/os/hal/ports/STM32F37x/hal_lld.h @@ -43,11 +43,6 @@ /*===========================================================================*/
/**
- * @brief Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS TRUE
-
-/**
* @name Platform identification
* @{
*/
diff --git a/os/hal/ports/STM32F4xx/hal_lld.h b/os/hal/ports/STM32F4xx/hal_lld.h index 349adc704..98bc2105c 100644 --- a/os/hal/ports/STM32F4xx/hal_lld.h +++ b/os/hal/ports/STM32F4xx/hal_lld.h @@ -44,11 +44,6 @@ /*===========================================================================*/
/**
- * @brief Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS TRUE
-
-/**
* @name Platform identification
* @{
*/
diff --git a/os/hal/ports/STM32L1xx/hal_lld.h b/os/hal/ports/STM32L1xx/hal_lld.h index 11998db9a..ff1ec009f 100644 --- a/os/hal/ports/STM32L1xx/hal_lld.h +++ b/os/hal/ports/STM32L1xx/hal_lld.h @@ -43,11 +43,6 @@ /*===========================================================================*/
/**
- * @brief Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS TRUE
-
-/**
* @name Platform identification
* @{
*/
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