diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2010-08-31 18:12:48 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2010-08-31 18:12:48 +0000 |
| commit | 7b11d85a8abe304bdc70a49994e7ce5698336c81 (patch) | |
| tree | b443d4d2930570dc633be98eccb994e088516b9a /os | |
| parent | e0999328d8b5d467b27b7c08cfa4ec06b237c6a1 (diff) | |
| download | ChibiOS-7b11d85a8abe304bdc70a49994e7ce5698336c81.tar.gz ChibiOS-7b11d85a8abe304bdc70a49994e7ce5698336c81.tar.bz2 ChibiOS-7b11d85a8abe304bdc70a49994e7ce5698336c81.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2150 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
| -rw-r--r-- | os/ports/GCC/ARMCMx/chcore_v6m.h | 12 | ||||
| -rw-r--r-- | os/ports/GCC/ARMCMx/chcore_v7m.h | 16 |
2 files changed, 14 insertions, 14 deletions
diff --git a/os/ports/GCC/ARMCMx/chcore_v6m.h b/os/ports/GCC/ARMCMx/chcore_v6m.h index c2d9cb618..a4b0e582d 100644 --- a/os/ports/GCC/ARMCMx/chcore_v6m.h +++ b/os/ports/GCC/ARMCMx/chcore_v6m.h @@ -183,14 +183,14 @@ struct intctx { * @details Usually this function just disables interrupts but may perform
* more actions.
*/
-#define port_lock() asm volatile ("cpsid i")
+#define port_lock() asm volatile ("cpsid i" : : : "memory")
/**
* @brief Kernel-unlock action.
* @details Usually this function just disables interrupts but may perform
* more actions.
*/
-#define port_unlock() asm volatile ("cpsie i")
+#define port_unlock() asm volatile ("cpsie i" : : : "memory")
/**
* @brief Kernel-lock action from an interrupt handler.
@@ -213,17 +213,17 @@ struct intctx { /**
* @brief Disables all the interrupt sources.
*/
-#define port_disable() asm volatile ("cpsid i")
+#define port_disable() asm volatile ("cpsid i" : : : "memory")
/**
* @brief Disables the interrupt sources below kernel-level priority.
*/
-#define port_suspend() asm volatile ("cpsid i")
+#define port_suspend() asm volatile ("cpsid i" : : : "memory")
/**
* @brief Enables all the interrupt sources.
*/
-#define port_enable() asm volatile ("cpsie i")
+#define port_enable() asm volatile ("cpsie i" : : : "memory")
/**
* @brief Enters an architecture-dependent IRQ-waiting mode.
@@ -234,7 +234,7 @@ struct intctx { * @note Implemented as an inlined @p WFI instruction.
*/
#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__)
-#define port_wait_for_interrupt() asm volatile ("wfi")
+#define port_wait_for_interrupt() asm volatile ("wfi" : : : "memory")
#else
#define port_wait_for_interrupt()
#endif
diff --git a/os/ports/GCC/ARMCMx/chcore_v7m.h b/os/ports/GCC/ARMCMx/chcore_v7m.h index 10e076b4f..263e20e2d 100644 --- a/os/ports/GCC/ARMCMx/chcore_v7m.h +++ b/os/ports/GCC/ARMCMx/chcore_v7m.h @@ -162,11 +162,11 @@ struct intctx { #if CH_OPTIMIZE_SPEED
#define port_lock() { \
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \
- asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \
+ asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory"); \
}
#else
#define port_lock() { \
- asm volatile ("bl _port_lock" : : : "r3", "lr"); \
+ asm volatile ("bl _port_lock" : : : "r3", "lr", "memory"); \
}
#endif
@@ -179,11 +179,11 @@ struct intctx { #if CH_OPTIMIZE_SPEED
#define port_unlock() { \
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \
- asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \
+ asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory"); \
}
#else
#define port_unlock() { \
- asm volatile ("bl _port_unlock" : : : "r3", "lr"); \
+ asm volatile ("bl _port_unlock" : : : "r3", "lr", "memory"); \
}
#endif
@@ -211,7 +211,7 @@ struct intctx { * @note In this port it disables all the interrupt sources by raising
* the priority mask to level 0.
*/
-#define port_disable() asm volatile ("cpsid i")
+#define port_disable() asm volatile ("cpsid i" : : : "memory")
/**
* @brief Disables the interrupt sources below kernel-level priority.
@@ -221,7 +221,7 @@ struct intctx { #define port_suspend() { \
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \
asm volatile ("msr BASEPRI, %0 \n\t" \
- "cpsie i" : : "r" (tmp)); \
+ "cpsie i" : : "r" (tmp) : "memory"); \
}
/**
@@ -231,7 +231,7 @@ struct intctx { #define port_enable() { \
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \
asm volatile ("msr BASEPRI, %0 \n\t" \
- "cpsie i" : : "r" (tmp)); \
+ "cpsie i" : : "r" (tmp) : "memory"); \
}
/**
@@ -244,7 +244,7 @@ struct intctx { */
#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__)
#define port_wait_for_interrupt() { \
- asm volatile ("wfi"); \
+ asm volatile ("wfi" : : : "memory"); \
}
#else
#define port_wait_for_interrupt()
|