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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2010-07-31 09:44:41 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2010-07-31 09:44:41 +0000 |
| commit | 76a6057c1dde2252ccaee91ba09fea24e84d18aa (patch) | |
| tree | bdad83f3e7a1fbfe2334ced9324bf6592ab02d58 /os | |
| parent | 28acd9ec851f318a3198b60eb5bf76f46e05adbf (diff) | |
| download | ChibiOS-76a6057c1dde2252ccaee91ba09fea24e84d18aa.tar.gz ChibiOS-76a6057c1dde2252ccaee91ba09fea24e84d18aa.tar.bz2 ChibiOS-76a6057c1dde2252ccaee91ba09fea24e84d18aa.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2103 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
| -rw-r--r-- | os/hal/platforms/STM32/stm32_dma.h | 2 | ||||
| -rw-r--r-- | os/hal/platforms/STM32/uart_lld.c | 8 |
2 files changed, 6 insertions, 4 deletions
diff --git a/os/hal/platforms/STM32/stm32_dma.h b/os/hal/platforms/STM32/stm32_dma.h index 567b3ef0b..1a3abd389 100644 --- a/os/hal/platforms/STM32/stm32_dma.h +++ b/os/hal/platforms/STM32/stm32_dma.h @@ -181,7 +181,7 @@ typedef struct { * @param[in] ch channel number
*/
#define dmaClearChannel(dmap, ch){ \
- (dmap)->IFCR = 1 << (ch); \
+ (dmap)->IFCR = 1 << ((ch) * 4); \
}
/*===========================================================================*/
diff --git a/os/hal/platforms/STM32/uart_lld.c b/os/hal/platforms/STM32/uart_lld.c index e585eed6a..68324b8f4 100644 --- a/os/hal/platforms/STM32/uart_lld.c +++ b/os/hal/platforms/STM32/uart_lld.c @@ -152,7 +152,8 @@ static void usart_start(UARTDriver *uartp) { USART_CR1_TCIE;
u->CR1 = uartp->ud_config->uc_cr1 | cr1;
u->CR2 = uartp->ud_config->uc_cr2 | USART_CR2_LBDIE;
- u->CR3 = uartp->ud_config->uc_cr3 | USART_CR3_EIE;
+ u->CR3 = uartp->ud_config->uc_cr3 | USART_CR3_DMAT | USART_CR3_DMAR |
+ USART_CR3_EIE;
/* Starting the receiver idle loop.*/
set_rx_idle_loop(uartp);
@@ -249,11 +250,11 @@ CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) { CH_IRQ_PROLOGUE();
+ uartp = &UARTD1;
if ((STM32_DMA1->ISR & DMA_ISR_TEIF4) != 0) {
STM32_UART_USART1_DMA_ERROR_HOOK();
}
dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_4);
- uartp = &UARTD1;
if (uartp->ud_rxstate == UART_RX_IDLE) {
/* Fast IRQ path, this is why it is not centralized in serve_rx_end_irq().*/
/* Receiver in idle state, a callback is generated, if enabled, for each
@@ -310,11 +311,11 @@ CH_IRQ_HANDLER(DMA1_Ch6_IRQHandler) { CH_IRQ_PROLOGUE();
+ uartp = &UARTD2;
if ((STM32_DMA1->ISR & DMA_ISR_TEIF6) != 0) {
STM32_UART_USART2_DMA_ERROR_HOOK();
}
dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_6);
- uartp = &UARTD2;
if (uartp->ud_rxstate == UART_RX_IDLE) {
/* Fast IRQ path, this is why it is not centralized in serve_rx_end_irq().*/
/* Receiver in idle state, a callback is generated, if enabled, for each
@@ -435,6 +436,7 @@ void uart_lld_start(UARTDriver *uartp) { uartp->ud_dmaccr |= DMA_CCR1_MSIZE_0 | DMA_CCR1_PSIZE_0;
uartp->ud_dmap->channels[uartp->ud_dmarx].CPAR = (uint32_t)&uartp->ud_usart->DR;
uartp->ud_dmap->channels[uartp->ud_dmatx].CPAR = (uint32_t)&uartp->ud_usart->DR;
+ uartp->ud_rxbuf = 0;
}
uartp->ud_rxstate = UART_RX_IDLE;
|