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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2019-01-06 08:56:22 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2019-01-06 08:56:22 +0000 |
| commit | 6ecd7c2bf023df721108ea64779895a1b9e6e0c8 (patch) | |
| tree | 7a370ed74a18c845f155cd296c110317795bb7b6 /os | |
| parent | cd33832ea347eef0f2380964eddcd2e3744339ba (diff) | |
| download | ChibiOS-6ecd7c2bf023df721108ea64779895a1b9e6e0c8.tar.gz ChibiOS-6ecd7c2bf023df721108ea64779895a1b9e6e0c8.tar.bz2 ChibiOS-6ecd7c2bf023df721108ea64779895a1b9e6e0c8.zip | |
RCC CRC macros for L4 and L4+.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12531 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'os')
| -rw-r--r-- | os/hal/ports/STM32/STM32L4xx+/stm32_rcc.h | 28 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32L4xx/stm32_rcc.h | 28 |
2 files changed, 56 insertions, 0 deletions
diff --git a/os/hal/ports/STM32/STM32L4xx+/stm32_rcc.h b/os/hal/ports/STM32/STM32L4xx+/stm32_rcc.h index 76f842ccc..d88c378f4 100644 --- a/os/hal/ports/STM32/STM32L4xx+/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32L4xx+/stm32_rcc.h @@ -1236,6 +1236,34 @@ /** @} */
/**
+ * @name CRC peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the CRC peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableCRC(lp) rccEnableAHB1(RCC_AHB1ENR_CRCEN, lp)
+
+/**
+ * @brief Disables the CRC peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableCRC() rccDisableAHB1(RCC_AHB1ENR_CRCEN)
+
+/**
+ * @brief Resets the CRC peripheral.
+ *
+ * @api
+ */
+#define rccResetCRC() rccResetAHB1(RCC_AHB1RSTR_CRCRST)
+/** @} */
+
+/**
* @name FSMC peripherals specific RCC operations
* @{
*/
diff --git a/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h b/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h index 91cc696f2..a48e305f8 100644 --- a/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h @@ -1185,6 +1185,34 @@ /** @} */
/**
+ * @name CRC peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the CRC peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableCRC(lp) rccEnableAHB1(RCC_AHB1ENR_CRCEN, lp)
+
+/**
+ * @brief Disables the CRC peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableCRC() rccDisableAHB1(RCC_AHB1ENR_CRCEN)
+
+/**
+ * @brief Resets the CRC peripheral.
+ *
+ * @api
+ */
+#define rccResetCRC() rccResetAHB1(RCC_AHB1RSTR_CRCRST)
+/** @} */
+
+/**
* @name FSMC peripherals specific RCC operations
* @{
*/
|