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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2009-12-18 09:24:29 +0000 | 
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2009-12-18 09:24:29 +0000 | 
| commit | 65f23fc65ff4b60d88281184d9a634375f02e3a1 (patch) | |
| tree | f240449b155caa5d84cb5d3969a282e003108564 /os | |
| parent | ebcb2909b26b261f99ea242629a36a888c53551c (diff) | |
| download | ChibiOS-65f23fc65ff4b60d88281184d9a634375f02e3a1.tar.gz ChibiOS-65f23fc65ff4b60d88281184d9a634375f02e3a1.tar.bz2 ChibiOS-65f23fc65ff4b60d88281184d9a634375f02e3a1.zip  | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1428 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
| -rw-r--r-- | os/hal/platforms/STM32/hal_lld.h | 2 | ||||
| -rw-r--r-- | os/hal/platforms/STM32/pwm_lld.c | 3 | 
2 files changed, 4 insertions, 1 deletions
diff --git a/os/hal/platforms/STM32/hal_lld.h b/os/hal/platforms/STM32/hal_lld.h index 45f74aff0..9144a48aa 100644 --- a/os/hal/platforms/STM32/hal_lld.h +++ b/os/hal/platforms/STM32/hal_lld.h @@ -76,6 +76,8 @@  #define APB1CLK                     (SYSCLK / 2)
  #define APB2CLK                     (SYSCLK / 2)
  #define AHB1CLK                     (SYSCLK / 1)
 +#define TIMCLK2                     (APB2CLK * 2)
 +#define TIMCLK1                     (APB1CLK * 2)
  /*
   * Values derived from the clock settings.
 diff --git a/os/hal/platforms/STM32/pwm_lld.c b/os/hal/platforms/STM32/pwm_lld.c index b1e4f7bc3..7fbaf5eae 100644 --- a/os/hal/platforms/STM32/pwm_lld.c +++ b/os/hal/platforms/STM32/pwm_lld.c @@ -78,6 +78,7 @@ CH_IRQ_HANDLER(VectorA4) {    CH_IRQ_PROLOGUE();
 +  TIM1->SR = ~TIM_SR_UIF;
    PWMD1.pd_config->pc_callback();
    CH_IRQ_EPILOGUE();
 @@ -95,7 +96,7 @@ CH_IRQ_HANDLER(VectorAC) {    CH_IRQ_PROLOGUE();
    sr = TIM1->SR;
 -  TIM1->SR &= ~(TIM_SR_CC1IF | TIM_SR_CC2IF | TIM_SR_CC3IF | TIM_SR_CC4IF);
 +  TIM1->SR = ~(TIM_SR_CC1IF | TIM_SR_CC2IF | TIM_SR_CC3IF | TIM_SR_CC4IF);
    if ((sr & TIM_SR_CC1IF) != 0)
      PWMD1.pd_config->pc_channels[0].pcc_callback();
    if ((sr & TIM_SR_CC2IF) != 0)
  | 
