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| author | barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2014-08-26 08:23:57 +0000 |
|---|---|---|
| committer | barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2014-08-26 08:23:57 +0000 |
| commit | 6220df1090c175979f37717a4f9040770f86a098 (patch) | |
| tree | 8144b4e0749697002da2cc6db09320495cbd2602 /os | |
| parent | e00a505b1c50375062a7ac789b2b95cf558b540c (diff) | |
| download | ChibiOS-6220df1090c175979f37717a4f9040770f86a098.tar.gz ChibiOS-6220df1090c175979f37717a4f9040770f86a098.tar.bz2 ChibiOS-6220df1090c175979f37717a4f9040770f86a098.zip | |
[FSMC NAND] Minor changes in testhal application.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7197 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
| -rw-r--r-- | os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h | 1403 |
1 files changed, 682 insertions, 721 deletions
diff --git a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h index fcf9d6f0c..8be008de3 100644 --- a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h +++ b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h @@ -24,7 +24,7 @@ /* * Board identifier. */ -#define BOARD_NAME "NAND flash test board. Codename PNC" +#define BOARD_NAME "NAND and SRAM test board. Codename Buod" /* * Board oscillators-related settings. @@ -34,7 +34,7 @@ #endif #if !defined(STM32_HSECLK) -#define STM32_HSECLK 8000000 +#define STM32_HSECLK 12000000 #endif /* @@ -51,121 +51,121 @@ /* * IO pins assignments. */ -#define GPIOA_CTL_27V_P 0 -#define GPIOA_CTL_27V_N 1 -#define GPIOA_CTL_6V_P 2 -#define GPIOA_CTL_6V_N 3 +#define GPIOA_PIN0 0 +#define GPIOA_PIN1 1 +#define GPIOA_PIN2 2 +#define GPIOA_PIN3 3 #define GPIOA_SPI1_NSS 4 -#define GPIOA_SPI1_SCK 5 -#define GPIOA_SPI1_MISO 6 -#define GPIOA_SPI1_MOSI 7 -#define GPIOA_TP1 8 -#define GPIOA_TX_MCU 9 -#define GPIOA_RX_MCU 10 -#define GPIOA_OTG_FS_DM 11 -#define GPIOA_OTG_FS_DP 12 +#define GPIOA_PIN5 5 +#define GPIOA_PIN6 6 +#define GPIOA_PIN7 7 +#define GPIOA_PIN8 8 +#define GPIOA_PIN9 9 +#define GPIOA_PIN10 10 +#define GPIOA_PIN11 11 +#define GPIOA_PIN12 12 #define GPIOA_JTMS 13 #define GPIOA_JTCK 14 #define GPIOA_JTDI 15 -#define GPIOB_DATA_SENT_OUT 0 -#define GPIOB_SPI1_RST 1 +#define GPIOB_PIN0 0 +#define GPIOB_NAND_WP 1 #define GPIOB_PIN2 2 #define GPIOB_JTDO 3 #define GPIOB_JTRST 4 -#define GPIOB_NAND_WP 5 -#define GPIOB_I2C1_SCL 6 -#define GPIOB_I2C1_SDA 7 -#define GPIOB_USB_DISCOVERY 8 -#define GPIOB_USB_PRESENT 9 -#define GPIOB_I2C2_SCL 10 -#define GPIOB_I2C2_SDA 11 +#define GPIOB_PIN5 5 +#define GPIOB_PIN6 6 +#define GPIOB_PIN7 7 +#define GPIOB_PIN8 8 +#define GPIOB_PIN9 9 +#define GPIOB_PIN10 10 +#define GPIOB_PIN11 11 #define GPIOB_PIN12 12 -#define GPIOB_SPI2_CLK 13 -#define GPIOB_SPI2_MISO 14 -#define GPIOB_XSENS_EXTTRIG 15 +#define GPIOB_PIN13 13 +#define GPIOB_PIN14 14 +#define GPIOB_PIN15 15 #define GPIOC_PIN0 0 -#define GPIOC_SPI3_CS1 1 -#define GPIOC_SPI3_CS2 2 -#define GPIOC_FLASH_CS 3 -#define GPIOC_SPI2_CS1 4 -#define GPIOC_SPI2_CS2 5 -#define GPIOC_XSENS_TX 6 -#define GPIOC_XSENS_RX 7 -#define GPIOC_MPU6050_CLK 8 -#define GPIOC_TP2 9 -#define GPIOC_FLASH_CLK 10 -#define GPIOC_FLASH_MISO 11 -#define GPIOC_FLASH_MOSI 12 -#define GPIOC_PPS_OUT 13 +#define GPIOC_PIN1 1 +#define GPIOC_PIN2 2 +#define GPIOC_PIN3 3 +#define GPIOC_PIN4 4 +#define GPIOC_PIN5 5 +#define GPIOC_PIN6 6 +#define GPIOC_PIN7 7 +#define GPIOC_PIN8 8 +#define GPIOC_PIN9 9 +#define GPIOC_PIN10 10 +#define GPIOC_PIN11 11 +#define GPIOC_PIN12 12 +#define GPIOC_PIN13 13 #define GPIOC_PIN14 14 #define GPIOC_PIN15 15 -#define GPIOD_NAND_IO2 0 -#define GPIOD_NAND_IO3 1 +#define GPIOD_MEM_D2 0 +#define GPIOD_MEM_D3 1 #define GPIOD_PIN2 2 #define GPIOD_PIN3 3 -#define GPIOD_NAND_RE 4 -#define GPIOD_NAND_WE 5 +#define GPIOD_MEM_OE 4 +#define GPIOD_MEM_WE 5 #define GPIOD_NAND_RB_NWAIT 6 -#define GPIOD_NAND_CE 7 -#define GPIOD_PIN8 8 -#define GPIOD_PIN9 9 -#define GPIOD_PIN10 10 -#define GPIOD_NAND_CLE 11 -#define GPIOD_NAND_ALE 12 +#define GPIOD_NAND_CE1 7 +#define GPIOD_MEM_D13 8 +#define GPIOD_MEM_D14 9 +#define GPIOD_MEM_D15 10 +#define GPIOD_MEM_A16 11 +#define GPIOD_MEM_A17 12 #define GPIOD_PIN13 13 -#define GPIOD_NAND_IO0 14 -#define GPIOD_NAND_IO1 15 +#define GPIOD_MEM_D0 14 +#define GPIOD_MEM_D1 15 -#define GPIOE_MPU6050_INT1 0 -#define GPIOE_MPU6050_INT2 1 +#define GPIOE_SRAM_LB 0 +#define GPIOE_SRAM_UB 1 #define GPIOE_PIN2 2 -#define GPIOE_SPI1_INT 3 -#define GPIOE_PPS_IN 4 -#define GPIOE_DATA_SENT_IN 5 -#define GPIOE_NAND_RB_INT 6 -#define GPIOE_NAND_IO4 7 -#define GPIOE_NAND_IO5 8 -#define GPIOE_NAND_IO6 9 -#define GPIOE_NAND_IO7 10 -#define GPIOE_LED_G 11 -#define GPIOE_LED_R 12 -#define GPIOE_FLASH_WP 13 -#define GPIOE_FLASH_RST 14 -#define GPIOE_PIN15 15 +#define GPIOE_PIN3 3 +#define GPIOE_PIN4 4 +#define GPIOE_PIN5 5 +#define GPIOE_PIN6 6 +#define GPIOE_MEM_D4 7 +#define GPIOE_MEM_D5 8 +#define GPIOE_MEM_D6 9 +#define GPIOE_MEM_D7 10 +#define GPIOE_MEM_D8 11 +#define GPIOE_MEM_D9 12 +#define GPIOE_MEM_D10 13 +#define GPIOE_MEM_D11 14 +#define GPIOE_MEM_D12 15 -#define GPIOF_PIN0 0 -#define GPIOF_PIN1 1 -#define GPIOF_PIN2 2 -#define GPIOF_PIN3 3 -#define GPIOF_PIN4 4 -#define GPIOF_PIN5 5 +#define GPIOF_MEM_A0 0 +#define GPIOF_MEM_A1 1 +#define GPIOF_MEM_A2 2 +#define GPIOF_MEM_A3 3 +#define GPIOF_MEM_A4 4 +#define GPIOF_MEM_A5 5 #define GPIOF_PIN6 6 #define GPIOF_PIN7 7 #define GPIOF_PIN8 8 #define GPIOF_PIN9 9 #define GPIOF_PIN10 10 #define GPIOF_PIN11 11 -#define GPIOF_PIN12 12 -#define GPIOF_PIN13 13 -#define GPIOF_PIN14 14 -#define GPIOF_PIN15 15 +#define GPIOF_MEM_A6 12 +#define GPIOF_MEM_A7 13 +#define GPIOF_MEM_A8 14 +#define GPIOF_MEM_A9 15 -#define GPIOG_PIN0 0 -#define GPIOG_PIN1 1 -#define GPIOG_PIN2 2 -#define GPIOG_PIN3 3 -#define GPIOG_PIN4 4 -#define GPIOG_PIN5 5 -#define GPIOG_PIN6 6 -#define GPIOG_PIN7 7 +#define GPIOG_MEM_A10 0 +#define GPIOG_MEM_A11 1 +#define GPIOG_MEM_A12 2 +#define GPIOG_MEM_A13 3 +#define GPIOG_MEM_A14 4 +#define GPIOG_MEM_A15 5 +#define GPIOG_NAND_RB1 6 +#define GPIOG_NAND_RB2 7 #define GPIOG_PIN8 8 -#define GPIOG_PIN9 9 +#define GPIOG_NAND_CE2 9 #define GPIOG_PIN10 10 #define GPIOG_PIN11 11 -#define GPIOG_PIN12 12 +#define GPIOG_SRAM_CS1 12 #define GPIOG_PIN13 13 #define GPIOG_PIN14 14 #define GPIOG_PIN15 15 @@ -197,8 +197,8 @@ #define GPIOI_PIN7 7 #define GPIOI_PIN8 8 #define GPIOI_PIN9 9 -#define GPIOI_PIN10 10 -#define GPIOI_PIN11 11 +#define GPIOI_LED_R 10 +#define GPIOI_LED_G 11 #define GPIOI_PIN12 12 #define GPIOI_PIN13 13 #define GPIOI_PIN14 14 @@ -229,740 +229,718 @@ /* * GPIOA setup: */ -#define VAL_GPIOA_MODER (PIN_MODE_ANALOG(GPIOA_CTL_27V_P) | \ - PIN_MODE_ANALOG(GPIOA_CTL_27V_N) | \ - PIN_MODE_ANALOG(GPIOA_CTL_6V_P) | \ - PIN_MODE_ANALOG(GPIOA_CTL_6V_N) | \ - PIN_MODE_OUTPUT(GPIOA_SPI1_NSS) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_SCK) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_MISO) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_MOSI) | \ - PIN_MODE_OUTPUT(GPIOA_TP1) | \ - PIN_MODE_ALTERNATE(GPIOA_TX_MCU) | \ - PIN_MODE_ALTERNATE(GPIOA_RX_MCU) | \ - PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \ - PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \ - PIN_MODE_ALTERNATE(GPIOA_JTMS) | \ - PIN_MODE_ALTERNATE(GPIOA_JTCK) | \ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_PIN0) | \ + PIN_MODE_INPUT(GPIOA_PIN1) | \ + PIN_MODE_INPUT(GPIOA_PIN2) | \ + PIN_MODE_INPUT(GPIOA_PIN3) | \ + PIN_MODE_ALTERNATE(GPIOA_SPI1_NSS) | \ + PIN_MODE_INPUT(GPIOA_PIN5) | \ + PIN_MODE_INPUT(GPIOA_PIN6) | \ + PIN_MODE_INPUT(GPIOA_PIN7) | \ + PIN_MODE_INPUT(GPIOA_PIN8) | \ + PIN_MODE_INPUT(GPIOA_PIN9) | \ + PIN_MODE_INPUT(GPIOA_PIN10) | \ + PIN_MODE_INPUT(GPIOA_PIN11) | \ + PIN_MODE_INPUT(GPIOA_PIN12) | \ + PIN_MODE_ALTERNATE(GPIOA_JTMS) | \ + PIN_MODE_ALTERNATE(GPIOA_JTCK) | \ PIN_MODE_ALTERNATE(GPIOA_JTDI)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_CTL_27V_P) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CTL_27V_N) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CTL_6V_P) | \ - PIN_OTYPE_PUSHPULL(GPIOA_CTL_6V_N) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_NSS) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_SCK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_MISO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_MOSI) | \ - PIN_OTYPE_PUSHPULL(GPIOA_TP1) | \ - PIN_OTYPE_PUSHPULL(GPIOA_TX_MCU) | \ - PIN_OTYPE_PUSHPULL(GPIOA_RX_MCU) | \ - PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \ - PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \ - PIN_OTYPE_PUSHPULL(GPIOA_JTMS) | \ - PIN_OTYPE_PUSHPULL(GPIOA_JTCK) | \ +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SPI1_NSS) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOA_JTMS) | \ + PIN_OTYPE_PUSHPULL(GPIOA_JTCK) | \ PIN_OTYPE_PUSHPULL(GPIOA_JTDI)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_2M(GPIOA_CTL_27V_P) | \ - PIN_OSPEED_2M(GPIOA_CTL_27V_N) | \ - PIN_OSPEED_2M(GPIOA_CTL_6V_P) | \ - PIN_OSPEED_2M(GPIOA_CTL_6V_N) | \ - PIN_OSPEED_50M(GPIOA_SPI1_NSS) | \ - PIN_OSPEED_100M(GPIOA_SPI1_SCK) | \ - PIN_OSPEED_100M(GPIOA_SPI1_MISO) | \ - PIN_OSPEED_100M(GPIOA_SPI1_MOSI) | \ - PIN_OSPEED_100M(GPIOA_TP1) | \ - PIN_OSPEED_100M(GPIOA_TX_MCU) | \ - PIN_OSPEED_100M(GPIOA_RX_MCU) | \ - PIN_OSPEED_100M(GPIOA_OTG_FS_DM) | \ - PIN_OSPEED_100M(GPIOA_OTG_FS_DP) | \ - PIN_OSPEED_100M(GPIOA_JTMS) | \ - PIN_OSPEED_100M(GPIOA_JTCK) | \ +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_100M(GPIOA_PIN0) | \ + PIN_OSPEED_100M(GPIOA_PIN1) | \ + PIN_OSPEED_100M(GPIOA_PIN2) | \ + PIN_OSPEED_100M(GPIOA_PIN3) | \ + PIN_OSPEED_100M(GPIOA_SPI1_NSS) | \ + PIN_OSPEED_100M(GPIOA_PIN5) | \ + PIN_OSPEED_100M(GPIOA_PIN6) | \ + PIN_OSPEED_100M(GPIOA_PIN7) | \ + PIN_OSPEED_100M(GPIOA_PIN8) | \ + PIN_OSPEED_100M(GPIOA_PIN9) | \ + PIN_OSPEED_100M(GPIOA_PIN10) | \ + PIN_OSPEED_100M(GPIOA_PIN11) | \ + PIN_OSPEED_100M(GPIOA_PIN12) | \ + PIN_OSPEED_100M(GPIOA_JTMS) | \ + PIN_OSPEED_100M(GPIOA_JTCK) | \ PIN_OSPEED_100M(GPIOA_JTDI)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_CTL_27V_P) | \ - PIN_PUPDR_FLOATING(GPIOA_CTL_27V_N) | \ - PIN_PUPDR_FLOATING(GPIOA_CTL_6V_P) | \ - PIN_PUPDR_FLOATING(GPIOA_CTL_6V_N) | \ - PIN_PUPDR_PULLUP(GPIOA_SPI1_NSS) | \ - PIN_PUPDR_PULLUP(GPIOA_SPI1_SCK) | \ - PIN_PUPDR_PULLUP(GPIOA_SPI1_MISO) | \ - PIN_PUPDR_PULLUP(GPIOA_SPI1_MOSI) | \ - PIN_PUPDR_PULLUP(GPIOA_TP1) | \ - PIN_PUPDR_PULLUP(GPIOA_TX_MCU) | \ - PIN_PUPDR_PULLUP(GPIOA_RX_MCU) | \ - PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \ - PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \ - PIN_PUPDR_FLOATING(GPIOA_JTMS) | \ - PIN_PUPDR_FLOATING(GPIOA_JTCK) | \ +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOA_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOA_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOA_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOA_SPI1_NSS) | \ + PIN_PUPDR_FLOATING(GPIOA_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOA_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOA_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOA_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOA_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOA_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOA_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOA_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOA_JTMS) | \ + PIN_PUPDR_FLOATING(GPIOA_JTCK) | \ PIN_PUPDR_FLOATING(GPIOA_JTDI)) -#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_CTL_27V_P) | \ - PIN_ODR_HIGH(GPIOA_CTL_27V_N) | \ - PIN_ODR_HIGH(GPIOA_CTL_6V_P) | \ - PIN_ODR_HIGH(GPIOA_CTL_6V_N) | \ - PIN_ODR_HIGH(GPIOA_SPI1_NSS) | \ - PIN_ODR_HIGH(GPIOA_SPI1_SCK) | \ - PIN_ODR_HIGH(GPIOA_SPI1_MISO) | \ - PIN_ODR_HIGH(GPIOA_SPI1_MOSI) | \ - PIN_ODR_HIGH(GPIOA_TP1) | \ - PIN_ODR_HIGH(GPIOA_TX_MCU) | \ - PIN_ODR_HIGH(GPIOA_RX_MCU) | \ - PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \ - PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \ - PIN_ODR_HIGH(GPIOA_JTMS) | \ - PIN_ODR_HIGH(GPIOA_JTCK) | \ +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | \ + PIN_ODR_HIGH(GPIOA_PIN1) | \ + PIN_ODR_HIGH(GPIOA_PIN2) | \ + PIN_ODR_HIGH(GPIOA_PIN3) | \ + PIN_ODR_HIGH(GPIOA_SPI1_NSS) | \ + PIN_ODR_HIGH(GPIOA_PIN5) | \ + PIN_ODR_HIGH(GPIOA_PIN6) | \ + PIN_ODR_HIGH(GPIOA_PIN7) | \ + PIN_ODR_HIGH(GPIOA_PIN8) | \ + PIN_ODR_HIGH(GPIOA_PIN9) | \ + PIN_ODR_HIGH(GPIOA_PIN10) | \ + PIN_ODR_HIGH(GPIOA_PIN11) | \ + PIN_ODR_HIGH(GPIOA_PIN12) | \ + PIN_ODR_HIGH(GPIOA_JTMS) | \ + PIN_ODR_HIGH(GPIOA_JTCK) | \ PIN_ODR_HIGH(GPIOA_JTDI)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_CTL_27V_P, 0) | \ - PIN_AFIO_AF(GPIOA_CTL_27V_N, 0) | \ - PIN_AFIO_AF(GPIOA_CTL_6V_P, 0) | \ - PIN_AFIO_AF(GPIOA_CTL_6V_N, 0) | \ - PIN_AFIO_AF(GPIOA_SPI1_NSS, 0) | \ - PIN_AFIO_AF(GPIOA_SPI1_SCK, 5) | \ - PIN_AFIO_AF(GPIOA_SPI1_MISO, 5) | \ - PIN_AFIO_AF(GPIOA_SPI1_MOSI, 5)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_TP1, 0) | \ - PIN_AFIO_AF(GPIOA_TX_MCU, 7) | \ - PIN_AFIO_AF(GPIOA_RX_MCU, 7) | \ - PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \ - PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \ - PIN_AFIO_AF(GPIOA_JTMS, 0) | \ - PIN_AFIO_AF(GPIOA_JTCK, 0) | \ +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0) | \ + PIN_AFIO_AF(GPIOA_PIN1, 0) | \ + PIN_AFIO_AF(GPIOA_PIN2, 0) | \ + PIN_AFIO_AF(GPIOA_PIN3, 0) | \ + PIN_AFIO_AF(GPIOA_SPI1_NSS, 5) | \ + PIN_AFIO_AF(GPIOA_PIN5, 0) | \ + PIN_AFIO_AF(GPIOA_PIN6, 0) | \ + PIN_AFIO_AF(GPIOA_PIN7, 0)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | \ + PIN_AFIO_AF(GPIOA_PIN9, 0) | \ + PIN_AFIO_AF(GPIOA_PIN10, 0) | \ + PIN_AFIO_AF(GPIOA_PIN11, 0) | \ + PIN_AFIO_AF(GPIOA_PIN12, 0) | \ + PIN_AFIO_AF(GPIOA_JTMS, 0) | \ + PIN_AFIO_AF(GPIOA_JTCK, 0) | \ PIN_AFIO_AF(GPIOA_JTDI, 0)) /* * GPIOB setup: */ -#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_DATA_SENT_OUT) | \ - PIN_MODE_OUTPUT(GPIOB_SPI1_RST) | \ +#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \ + PIN_MODE_OUTPUT(GPIOB_NAND_WP) | \ PIN_MODE_INPUT(GPIOB_PIN2) | \ - PIN_MODE_ALTERNATE(GPIOB_JTDO) | \ - PIN_MODE_ALTERNATE(GPIOB_JTRST) | \ - PIN_MODE_OUTPUT(GPIOB_NAND_WP) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ - PIN_MODE_OUTPUT(GPIOB_USB_DISCOVERY) | \ - PIN_MODE_INPUT(GPIOB_USB_PRESENT) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C2_SCL) | \ - PIN_MODE_ALTERNATE(GPIOB_I2C2_SDA) | \ + PIN_MODE_ALTERNATE(GPIOB_JTDO) | \ + PIN_MODE_ALTERNATE(GPIOB_JTRST) | \ + PIN_MODE_INPUT(GPIOB_PIN5) | \ + PIN_MODE_INPUT(GPIOB_PIN6) | \ + PIN_MODE_INPUT(GPIOB_PIN7) | \ + PIN_MODE_INPUT(GPIOB_PIN8) | \ + PIN_MODE_INPUT(GPIOB_PIN9) | \ + PIN_MODE_INPUT(GPIOB_PIN10) | \ + PIN_MODE_INPUT(GPIOB_PIN11) | \ PIN_MODE_INPUT(GPIOB_PIN12) | \ - PIN_MODE_ALTERNATE(GPIOB_SPI2_CLK) | \ - PIN_MODE_ALTERNATE(GPIOB_SPI2_MISO) | \ - PIN_MODE_INPUT(GPIOB_XSENS_EXTTRIG)) + PIN_MODE_INPUT(GPIOB_PIN13) | \ + PIN_MODE_INPUT(GPIOB_PIN14) | \ + PIN_MODE_INPUT(GPIOB_PIN15)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_DATA_SENT_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOB_SPI1_RST) | \ +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOB_NAND_WP) | \ PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOB_JTDO) | \ - PIN_OTYPE_PUSHPULL(GPIOB_JTRST) | \ - PIN_OTYPE_PUSHPULL(GPIOB_NAND_WP) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ - PIN_OTYPE_PUSHPULL(GPIOB_USB_DISCOVERY) | \ - PIN_OTYPE_PUSHPULL(GPIOB_USB_PRESENT) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C2_SCL) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_I2C2_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOB_JTDO) | \ + PIN_OTYPE_PUSHPULL(GPIOB_JTRST) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOB_SPI2_CLK) | \ - PIN_OTYPE_PUSHPULL(GPIOB_SPI2_MISO) | \ - PIN_OTYPE_PUSHPULL(GPIOB_XSENS_EXTTRIG)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_2M(GPIOB_DATA_SENT_OUT) | \ - PIN_OSPEED_2M(GPIOB_SPI1_RST) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_100M(GPIOB_PIN0) | \ + PIN_OSPEED_100M(GPIOB_NAND_WP) | \ PIN_OSPEED_100M(GPIOB_PIN2) | \ - PIN_OSPEED_100M(GPIOB_JTDO) | \ - PIN_OSPEED_100M(GPIOB_JTRST) | \ - PIN_OSPEED_2M(GPIOB_NAND_WP) | \ - PIN_OSPEED_2M(GPIOB_I2C1_SCL) | \ - PIN_OSPEED_2M(GPIOB_I2C1_SDA) | \ - PIN_OSPEED_2M(GPIOB_USB_DISCOVERY) | \ - PIN_OSPEED_2M(GPIOB_USB_PRESENT) | \ - PIN_OSPEED_2M(GPIOB_I2C2_SCL) | \ - PIN_OSPEED_2M(GPIOB_I2C2_SDA) | \ + PIN_OSPEED_100M(GPIOB_JTDO) | \ + PIN_OSPEED_100M(GPIOB_JTRST) | \ + PIN_OSPEED_100M(GPIOB_PIN5) | \ + PIN_OSPEED_100M(GPIOB_PIN6) | \ + PIN_OSPEED_100M(GPIOB_PIN7) | \ + PIN_OSPEED_100M(GPIOB_PIN8) | \ + PIN_OSPEED_100M(GPIOB_PIN9) | \ + PIN_OSPEED_100M(GPIOB_PIN10) | \ + PIN_OSPEED_100M(GPIOB_PIN11) | \ PIN_OSPEED_100M(GPIOB_PIN12) | \ - PIN_OSPEED_100M(GPIOB_SPI2_CLK) | \ - PIN_OSPEED_100M(GPIOB_SPI2_MISO) | \ - PIN_OSPEED_100M(GPIOB_XSENS_EXTTRIG)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_DATA_SENT_OUT) | \ - PIN_PUPDR_PULLDOWN(GPIOB_SPI1_RST) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOB_JTDO) | \ - PIN_PUPDR_FLOATING(GPIOB_JTRST) | \ - PIN_PUPDR_PULLDOWN(GPIOB_NAND_WP) | \ - PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \ - PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \ - PIN_PUPDR_FLOATING(GPIOB_USB_DISCOVERY) | \ - PIN_PUPDR_FLOATING(GPIOB_USB_PRESENT) | \ - PIN_PUPDR_FLOATING(GPIOB_I2C2_SCL) | \ - PIN_PUPDR_FLOATING(GPIOB_I2C2_SDA) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOB_SPI2_CLK) | \ - PIN_PUPDR_PULLUP(GPIOB_SPI2_MISO) | \ - PIN_PUPDR_PULLUP(GPIOB_XSENS_EXTTRIG)) -#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_DATA_SENT_OUT) | \ - PIN_ODR_LOW(GPIOB_SPI1_RST) | \ + PIN_OSPEED_100M(GPIOB_PIN13) | \ + PIN_OSPEED_100M(GPIOB_PIN14) | \ + PIN_OSPEED_100M(GPIOB_PIN15)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_PIN0) | \ + PIN_PUPDR_PULLDOWN(GPIOB_NAND_WP) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOB_JTDO) | \ + PIN_PUPDR_FLOATING(GPIOB_JTRST) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN15)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ + PIN_ODR_LOW(GPIOB_NAND_WP) | \ PIN_ODR_HIGH(GPIOB_PIN2) | \ - PIN_ODR_HIGH(GPIOB_JTDO) | \ - PIN_ODR_HIGH(GPIOB_JTRST) | \ - PIN_ODR_LOW(GPIOB_NAND_WP) | \ - PIN_ODR_LOW(GPIOB_I2C1_SCL) | \ - PIN_ODR_LOW(GPIOB_I2C1_SDA) | \ - PIN_ODR_HIGH(GPIOB_USB_DISCOVERY) | \ - PIN_ODR_HIGH(GPIOB_USB_PRESENT) | \ - PIN_ODR_LOW(GPIOB_I2C2_SCL) | \ - PIN_ODR_LOW(GPIOB_I2C2_SDA) | \ + PIN_ODR_HIGH(GPIOB_JTDO) | \ + PIN_ODR_HIGH(GPIOB_JTRST) | \ + PIN_ODR_HIGH(GPIOB_PIN5) | \ + PIN_ODR_HIGH(GPIOB_PIN6) | \ + PIN_ODR_HIGH(GPIOB_PIN7) | \ + PIN_ODR_HIGH(GPIOB_PIN8) | \ + PIN_ODR_HIGH(GPIOB_PIN9) | \ + PIN_ODR_HIGH(GPIOB_PIN10) | \ + PIN_ODR_HIGH(GPIOB_PIN11) | \ PIN_ODR_HIGH(GPIOB_PIN12) | \ - PIN_ODR_HIGH(GPIOB_SPI2_CLK) | \ - PIN_ODR_HIGH(GPIOB_SPI2_MISO) | \ - PIN_ODR_HIGH(GPIOB_XSENS_EXTTRIG)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_DATA_SENT_OUT, 0) | \ - PIN_AFIO_AF(GPIOB_SPI1_RST, 0) | \ + PIN_ODR_HIGH(GPIOB_PIN13) | \ + PIN_ODR_HIGH(GPIOB_PIN14) | \ + PIN_ODR_HIGH(GPIOB_PIN15)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0) | \ + PIN_AFIO_AF(GPIOB_NAND_WP, 0) | \ PIN_AFIO_AF(GPIOB_PIN2, 0) | \ - PIN_AFIO_AF(GPIOB_JTDO, 0) | \ - PIN_AFIO_AF(GPIOB_JTRST, 0) | \ - PIN_AFIO_AF(GPIOB_NAND_WP, 0) | \ - PIN_AFIO_AF(GPIOB_I2C1_SCL, 4) | \ - PIN_AFIO_AF(GPIOB_I2C1_SDA, 4)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_USB_DISCOVERY, 0) | \ - PIN_AFIO_AF(GPIOB_USB_PRESENT, 0) | \ - PIN_AFIO_AF(GPIOB_I2C2_SCL, 4) | \ - PIN_AFIO_AF(GPIOB_I2C2_SDA, 4) | \ + PIN_AFIO_AF(GPIOB_JTDO, 0) | \ + PIN_AFIO_AF(GPIOB_JTRST, 0) | \ + PIN_AFIO_AF(GPIOB_PIN5, 0) | \ + PIN_AFIO_AF(GPIOB_PIN6, 0) | \ + PIN_AFIO_AF(GPIOB_PIN7, 0)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0) | \ + PIN_AFIO_AF(GPIOB_PIN9, 0) | \ + PIN_AFIO_AF(GPIOB_PIN10, 0) | \ + PIN_AFIO_AF(GPIOB_PIN11, 0) | \ PIN_AFIO_AF(GPIOB_PIN12, 0) | \ - PIN_AFIO_AF(GPIOB_SPI2_CLK, 5) | \ - PIN_AFIO_AF(GPIOB_SPI2_MISO, 5) | \ - PIN_AFIO_AF(GPIOB_XSENS_EXTTRIG, 0)) + PIN_AFIO_AF(GPIOB_PIN13, 0) | \ + PIN_AFIO_AF(GPIOB_PIN14, 0) | \ + PIN_AFIO_AF(GPIOB_PIN15, 0)) /* * GPIOC setup: */ -#define VAL_GPIOC_MODER (PIN_MODE_OUTPUT(GPIOC_PIN0) |\ - PIN_MODE_OUTPUT(GPIOC_SPI3_CS1) | \ - PIN_MODE_OUTPUT(GPIOC_SPI3_CS2) | \ - PIN_MODE_OUTPUT(GPIOC_FLASH_CS) | \ - PIN_MODE_OUTPUT(GPIOC_SPI2_CS1) | \ - PIN_MODE_OUTPUT(GPIOC_SPI2_CS2) | \ - PIN_MODE_ALTERNATE(GPIOC_XSENS_TX) | \ - PIN_MODE_ALTERNATE(GPIOC_XSENS_RX) | \ - PIN_MODE_ALTERNATE(GPIOC_MPU6050_CLK) | \ - PIN_MODE_OUTPUT(GPIOC_TP2) | \ - PIN_MODE_ALTERNATE(GPIOC_FLASH_CLK) | \ - PIN_MODE_ALTERNATE(GPIOC_FLASH_MISO) | \ - PIN_MODE_ALTERNATE(GPIOC_FLASH_MOSI) | \ - PIN_MODE_OUTPUT(GPIOC_PPS_OUT) | \ +#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \ + PIN_MODE_INPUT(GPIOC_PIN1) | \ + PIN_MODE_INPUT(GPIOC_PIN2) | \ + PIN_MODE_INPUT(GPIOC_PIN3) | \ + PIN_MODE_INPUT(GPIOC_PIN4) | \ + PIN_MODE_INPUT(GPIOC_PIN5) | \ + PIN_MODE_INPUT(GPIOC_PIN6) | \ + PIN_MODE_INPUT(GPIOC_PIN7) | \ + PIN_MODE_INPUT(GPIOC_PIN8) | \ + PIN_MODE_INPUT(GPIOC_PIN9) | \ + PIN_MODE_INPUT(GPIOC_PIN10) | \ + PIN_MODE_INPUT(GPIOC_PIN11) | \ + PIN_MODE_INPUT(GPIOC_PIN12) | \ + PIN_MODE_INPUT(GPIOC_PIN13) | \ PIN_MODE_INPUT(GPIOC_PIN14) | \ PIN_MODE_INPUT(GPIOC_PIN15)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) |\ - PIN_OTYPE_PUSHPULL(GPIOC_SPI3_CS1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SPI3_CS2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_FLASH_CS) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SPI2_CS1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SPI2_CS2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_XSENS_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOC_XSENS_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOC_MPU6050_CLK) | \ - PIN_OTYPE_PUSHPULL(GPIOC_TP2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_FLASH_CLK) | \ - PIN_OTYPE_PUSHPULL(GPIOC_FLASH_MISO) | \ - PIN_OTYPE_PUSHPULL(GPIOC_FLASH_MOSI) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PPS_OUT) | \ +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \ PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_2M(GPIOC_PIN0) |\ - PIN_OSPEED_2M(GPIOC_SPI3_CS1) | \ - PIN_OSPEED_2M(GPIOC_SPI3_CS2) | \ - PIN_OSPEED_2M(GPIOC_FLASH_CS) | \ - PIN_OSPEED_2M(GPIOC_SPI2_CS1) | \ - PIN_OSPEED_2M(GPIOC_SPI2_CS2) | \ - PIN_OSPEED_2M(GPIOC_XSENS_TX) | \ - PIN_OSPEED_2M(GPIOC_XSENS_RX) | \ - PIN_OSPEED_100M(GPIOC_MPU6050_CLK) | \ - PIN_OSPEED_100M(GPIOC_TP2) | \ - PIN_OSPEED_100M(GPIOC_FLASH_CLK) | \ - PIN_OSPEED_100M(GPIOC_FLASH_MISO) | \ - PIN_OSPEED_100M(GPIOC_FLASH_MOSI) | \ - PIN_OSPEED_100M(GPIOC_PPS_OUT) | \ +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_100M(GPIOC_PIN0) |\ + PIN_OSPEED_100M(GPIOC_PIN1) | \ + PIN_OSPEED_100M(GPIOC_PIN2) | \ + PIN_OSPEED_100M(GPIOC_PIN3) | \ + PIN_OSPEED_100M(GPIOC_PIN4) | \ + PIN_OSPEED_100M(GPIOC_PIN5) | \ + PIN_OSPEED_100M(GPIOC_PIN6) | \ + PIN_OSPEED_100M(GPIOC_PIN7) | \ + PIN_OSPEED_100M(GPIOC_PIN8) | \ + PIN_OSPEED_100M(GPIOC_PIN9) | \ + PIN_OSPEED_100M(GPIOC_PIN10) | \ + PIN_OSPEED_100M(GPIOC_PIN11) | \ + PIN_OSPEED_100M(GPIOC_PIN12) | \ + PIN_OSPEED_100M(GPIOC_PIN13) | \ PIN_OSPEED_100M(GPIOC_PIN14) | \ PIN_OSPEED_100M(GPIOC_PIN15)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) |\ - PIN_PUPDR_PULLUP(GPIOC_SPI3_CS1) | \ - PIN_PUPDR_PULLUP(GPIOC_SPI3_CS2) | \ - PIN_PUPDR_PULLUP(GPIOC_FLASH_CS) | \ - PIN_PUPDR_PULLUP(GPIOC_SPI2_CS1) | \ - PIN_PUPDR_PULLUP(GPIOC_SPI2_CS2) | \ - PIN_PUPDR_PULLUP(GPIOC_XSENS_TX) | \ - PIN_PUPDR_PULLUP(GPIOC_XSENS_RX) | \ - PIN_PUPDR_PULLUP(GPIOC_MPU6050_CLK) | \ - PIN_PUPDR_PULLUP(GPIOC_TP2) | \ - PIN_PUPDR_PULLUP(GPIOC_FLASH_CLK) | \ - PIN_PUPDR_PULLUP(GPIOC_FLASH_MISO) | \ - PIN_PUPDR_PULLUP(GPIOC_FLASH_MOSI) | \ - PIN_PUPDR_PULLUP(GPIOC_PPS_OUT) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN15)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ - PIN_ODR_HIGH(GPIOC_SPI3_CS1) | \ - PIN_ODR_HIGH(GPIOC_SPI3_CS2) | \ - PIN_ODR_HIGH(GPIOC_FLASH_CS) | \ - PIN_ODR_HIGH(GPIOC_SPI2_CS1) | \ - PIN_ODR_HIGH(GPIOC_SPI2_CS2) | \ - PIN_ODR_HIGH(GPIOC_XSENS_TX) | \ - PIN_ODR_HIGH(GPIOC_XSENS_RX) | \ - PIN_ODR_HIGH(GPIOC_MPU6050_CLK) | \ - PIN_ODR_HIGH(GPIOC_TP2) | \ - PIN_ODR_HIGH(GPIOC_FLASH_CLK) | \ - PIN_ODR_HIGH(GPIOC_FLASH_MISO) | \ - PIN_ODR_HIGH(GPIOC_FLASH_MOSI) | \ - PIN_ODR_HIGH(GPIOC_PPS_OUT) | \ +#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN15)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ + PIN_ODR_HIGH(GPIOC_PIN1) | \ + PIN_ODR_HIGH(GPIOC_PIN2) | \ + PIN_ODR_HIGH(GPIOC_PIN3) | \ + PIN_ODR_HIGH(GPIOC_PIN4) | \ + PIN_ODR_HIGH(GPIOC_PIN5) | \ + PIN_ODR_HIGH(GPIOC_PIN6) | \ + PIN_ODR_HIGH(GPIOC_PIN7) | \ + PIN_ODR_HIGH(GPIOC_PIN8) | \ + PIN_ODR_HIGH(GPIOC_PIN9) | \ + PIN_ODR_HIGH(GPIOC_PIN10) | \ + PIN_ODR_HIGH(GPIOC_PIN11) | \ + PIN_ODR_HIGH(GPIOC_PIN12) | \ + PIN_ODR_HIGH(GPIOC_PIN13) | \ PIN_ODR_HIGH(GPIOC_PIN14) | \ PIN_ODR_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0) |\ - PIN_AFIO_AF(GPIOC_SPI3_CS1, 0) | \ - PIN_AFIO_AF(GPIOC_SPI3_CS2, 0) | \ - PIN_AFIO_AF(GPIOC_FLASH_CS, 0) | \ - PIN_AFIO_AF(GPIOC_SPI2_CS1, 0) | \ - PIN_AFIO_AF(GPIOC_SPI2_CS2, 0) | \ - PIN_AFIO_AF(GPIOC_XSENS_TX, 8) | \ - PIN_AFIO_AF(GPIOC_XSENS_RX, 8)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_MPU6050_CLK, 2) | \ - PIN_AFIO_AF(GPIOC_TP2, 0) | \ - PIN_AFIO_AF(GPIOC_FLASH_CLK, 6) | \ - PIN_AFIO_AF(GPIOC_FLASH_MISO, 6) | \ - PIN_AFIO_AF(GPIOC_FLASH_MOSI, 6) | \ - PIN_AFIO_AF(GPIOC_PPS_OUT, 0) | \ +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0) | \ + PIN_AFIO_AF(GPIOC_PIN1, 0) | \ + PIN_AFIO_AF(GPIOC_PIN2, 0) | \ + PIN_AFIO_AF(GPIOC_PIN3, 0) | \ + PIN_AFIO_AF(GPIOC_PIN4, 0) | \ + PIN_AFIO_AF(GPIOC_PIN5, 0) | \ + PIN_AFIO_AF(GPIOC_PIN6, 0) | \ + PIN_AFIO_AF(GPIOC_PIN7, 0)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0) | \ + PIN_AFIO_AF(GPIOC_PIN9, 0) | \ + PIN_AFIO_AF(GPIOC_PIN10, 0) | \ + PIN_AFIO_AF(GPIOC_PIN11, 0) | \ + PIN_AFIO_AF(GPIOC_PIN12, 0) | \ + PIN_AFIO_AF(GPIOC_PIN13, 0) | \ PIN_AFIO_AF(GPIOC_PIN14, 0) | \ PIN_AFIO_AF(GPIOC_PIN15, 0)) /* * GPIOD setup: */ -#define VAL_GPIOD_MODER (PIN_MODE_ALTERNATE(GPIOD_NAND_IO2) | \ - PIN_MODE_ALTERNATE(GPIOD_NAND_IO3) | \ +#define VAL_GPIOD_MODER (PIN_MODE_ALTERNATE(GPIOD_MEM_D2) | \ + PIN_MODE_ALTERNATE(GPIOD_MEM_D3) | \ PIN_MODE_INPUT(GPIOD_PIN2) | \ PIN_MODE_INPUT(GPIOD_PIN3) | \ - PIN_MODE_ALTERNATE(GPIOD_NAND_RE) | \ - PIN_MODE_ALTERNATE(GPIOD_NAND_WE) | \ - PIN_MODE_INPUT(GPIOD_NAND_RB_NWAIT) | \ - PIN_MODE_ALTERNATE(GPIOD_NAND_CE) | \ - PIN_MODE_INPUT(GPIOD_PIN8) | \ - PIN_MODE_INPUT(GPIOD_PIN9) | \ - PIN_MODE_INPUT(GPIOD_PIN10) | \ - PIN_MODE_ALTERNATE(GPIOD_NAND_CLE) | \ - PIN_MODE_ALTERNATE(GPIOD_NAND_ALE) | \ + PIN_MODE_ALTERNATE(GPIOD_MEM_OE) | \ + PIN_MODE_ALTERNATE(GPIOD_MEM_WE) | \ + PIN_MODE_INPUT(GPIOD_NAND_RB_NWAIT) | \ + PIN_MODE_ALTERNATE(GPIOD_NAND_CE1) | \ + PIN_MODE_ALTERNATE(GPIOD_MEM_D13) | \ + PIN_MODE_ALTERNATE(GPIOD_MEM_D14) | \ + PIN_MODE_ALTERNATE(GPIOD_MEM_D15) | \ + PIN_MODE_ALTERNATE(GPIOD_MEM_A16) | \ + PIN_MODE_ALTERNATE(GPIOD_MEM_A17) | \ PIN_MODE_INPUT(GPIOD_PIN13) | \ - PIN_MODE_ALTERNATE(GPIOD_NAND_IO0) | \ - PIN_MODE_ALTERNATE(GPIOD_NAND_IO1)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_NAND_IO2) | \ - PIN_OTYPE_PUSHPULL(GPIOD_NAND_IO3) | \ + PIN_MODE_ALTERNATE(GPIOD_MEM_D0) | \ + PIN_MODE_ALTERNATE(GPIOD_MEM_D1)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_MEM_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_MEM_D3) | \ PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_NAND_RE) | \ - PIN_OTYPE_PUSHPULL(GPIOD_NAND_WE) |\ - PIN_OTYPE_PUSHPULL(GPIOD_NAND_RB_NWAIT) | \ - PIN_OTYPE_PUSHPULL(GPIOD_NAND_CE) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOD_NAND_CLE) | \ - PIN_OTYPE_PUSHPULL(GPIOD_NAND_ALE) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOD_NAND_IO0) | \ - PIN_OTYPE_PUSHPULL(GPIOD_NAND_IO1)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_100M(GPIOD_NAND_IO2) | \ - PIN_OSPEED_100M(GPIOD_NAND_IO3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_MEM_OE) | \ + PIN_OTYPE_PUSHPULL(GPIOD_MEM_WE) | \ + PIN_OTYPE_PUSHPULL(GPIOD_NAND_RB_NWAIT) |\ + PIN_OTYPE_PUSHPULL(GPIOD_NAND_CE1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_MEM_D13) | \ + PIN_OTYPE_PUSHPULL(GPIOD_MEM_D14) | \ + PIN_OTYPE_PUSHPULL(GPIOD_MEM_D15) | \ + PIN_OTYPE_PUSHPULL(GPIOD_MEM_A16) | \ + PIN_OTYPE_PUSHPULL(GPIOD_MEM_A17) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOD_MEM_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOD_MEM_D1)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_100M(GPIOD_MEM_D2) | \ + PIN_OSPEED_100M(GPIOD_MEM_D3) | \ PIN_OSPEED_100M(GPIOD_PIN2) | \ PIN_OSPEED_100M(GPIOD_PIN3) | \ - PIN_OSPEED_100M(GPIOD_NAND_RE) | \ - PIN_OSPEED_100M(GPIOD_NAND_WE) | \ - PIN_OSPEED_100M(GPIOD_NAND_RB_NWAIT) | \ - PIN_OSPEED_100M(GPIOD_NAND_CE) | \ - PIN_OSPEED_100M(GPIOD_PIN8) | \ - PIN_OSPEED_100M(GPIOD_PIN9) | \ - PIN_OSPEED_100M(GPIOD_PIN10) | \ - PIN_OSPEED_100M(GPIOD_NAND_CLE) | \ - PIN_OSPEED_100M(GPIOD_NAND_ALE) | \ - PIN_OSPEED_100M(GPIOD_PIN13) | \ - PIN_OSPEED_100M(GPIOD_NAND_IO0) | \ - PIN_OSPEED_100M(GPIOD_NAND_IO1)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_NAND_IO2) | \ - PIN_PUPDR_PULLUP(GPIOD_NAND_IO3) | \ + PIN_OSPEED_100M(GPIOD_MEM_OE) | \ + PIN_OSPEED_100M(GPIOD_MEM_WE) | \ + PIN_OSPEED_100M(GPIOD_NAND_RB_NWAIT) | \ + PIN_OSPEED_100M(GPIOD_NAND_CE1) | \ + PIN_OSPEED_100M(GPIOD_MEM_D13) | \ + PIN_OSPEED_100M(GPIOD_MEM_D14) | \ + PIN_OSPEED_100M(GPIOD_MEM_D15) | \ + PIN_OSPEED_100M(GPIOD_MEM_A16) | \ + PIN_OSPEED_100M(GPIOD_MEM_A17) | \ + PIN_OSPEED_100M(GPIOD_PIN13) | \ + PIN_OSPEED_100M(GPIOD_MEM_D0) | \ + PIN_OSPEED_100M(GPIOD_MEM_D1)) + +#if STM32_NAND_USE_EXT_INT +#define NAND_RB_NWAIT_PUPDR(pin) (PIN_PUPDR_PULLUP(pin)) +#else +#define NAND_RB_NWAIT_PUPDR(pin) (PIN_PUPDR_FLOATING(pin)) +#endif +#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_MEM_D2) | \ + PIN_PUPDR_PULLUP(GPIOD_MEM_D3) | \ PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOD_NAND_RE) | \ - PIN_PUPDR_PULLUP(GPIOD_NAND_WE) |\ - PIN_PUPDR_PULLUP(GPIOD_NAND_RB_NWAIT) | \ - PIN_PUPDR_PULLUP(GPIOD_NAND_CE) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOD_NAND_CLE) | \ - PIN_PUPDR_PULLUP(GPIOD_NAND_ALE) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOD_NAND_IO0) | \ - PIN_PUPDR_PULLUP(GPIOD_NAND_IO1)) -#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_NAND_IO2) | \ - PIN_ODR_HIGH(GPIOD_NAND_IO3) | \ + PIN_PUPDR_PULLUP(GPIOD_MEM_OE) | \ + PIN_PUPDR_PULLUP(GPIOD_MEM_WE) | \ + NAND_RB_NWAIT_PUPDR(GPIOD_NAND_RB_NWAIT) | \ + PIN_PUPDR_PULLUP(GPIOD_NAND_CE1) | \ + PIN_PUPDR_PULLUP(GPIOD_MEM_D13) | \ + PIN_PUPDR_PULLUP(GPIOD_MEM_D14) | \ + PIN_PUPDR_PULLUP(GPIOD_MEM_D15) | \ + PIN_PUPDR_PULLUP(GPIOD_MEM_A16) | \ + PIN_PUPDR_PULLUP(GPIOD_MEM_A17) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOD_MEM_D0) | \ + PIN_PUPDR_PULLUP(GPIOD_MEM_D1)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_MEM_D2) | \ + PIN_ODR_HIGH(GPIOD_MEM_D3) | \ PIN_ODR_HIGH(GPIOD_PIN2) | \ PIN_ODR_HIGH(GPIOD_PIN3) | \ - PIN_ODR_HIGH(GPIOD_NAND_RE) | \ - PIN_ODR_HIGH(GPIOD_NAND_WE) | \ - PIN_ODR_HIGH(GPIOD_NAND_RB_NWAIT) | \ - PIN_ODR_HIGH(GPIOD_NAND_CE) | \ - PIN_ODR_HIGH(GPIOD_PIN8) | \ - PIN_ODR_HIGH(GPIOD_PIN9) | \ - PIN_ODR_HIGH(GPIOD_PIN10) | \ - PIN_ODR_HIGH(GPIOD_NAND_CLE) | \ - PIN_ODR_HIGH(GPIOD_NAND_ALE) | \ - PIN_ODR_HIGH(GPIOD_PIN13) | \ - PIN_ODR_HIGH(GPIOD_NAND_IO0) | \ - PIN_ODR_HIGH(GPIOD_NAND_IO1)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_NAND_IO2, 12) | \ - PIN_AFIO_AF(GPIOD_NAND_IO3, 12) | \ + PIN_ODR_HIGH(GPIOD_MEM_OE) | \ + PIN_ODR_HIGH(GPIOD_MEM_WE) | \ + PIN_ODR_HIGH(GPIOD_NAND_RB_NWAIT) | \ + PIN_ODR_HIGH(GPIOD_NAND_CE1) | \ + PIN_ODR_HIGH(GPIOD_MEM_D13) | \ + PIN_ODR_HIGH(GPIOD_MEM_D14) | \ + PIN_ODR_HIGH(GPIOD_MEM_D15) | \ + PIN_ODR_HIGH(GPIOD_MEM_A16) | \ + PIN_ODR_HIGH(GPIOD_MEM_A17) | \ + PIN_ODR_HIGH(GPIOD_PIN13) | \ + PIN_ODR_HIGH(GPIOD_MEM_D0) | \ + PIN_ODR_HIGH(GPIOD_MEM_D1)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_MEM_D2, 12) | \ + PIN_AFIO_AF(GPIOD_MEM_D3, 12) | \ PIN_AFIO_AF(GPIOD_PIN2, 0) | \ PIN_AFIO_AF(GPIOD_PIN3, 0) | \ - PIN_AFIO_AF(GPIOD_NAND_RE, 12) | \ - PIN_AFIO_AF(GPIOD_NAND_WE, 12) | \ - PIN_AFIO_AF(GPIOD_NAND_RB_NWAIT, 0) | \ - PIN_AFIO_AF(GPIOD_NAND_CE, 12)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \ - PIN_AFIO_AF(GPIOD_PIN9, 0) | \ - PIN_AFIO_AF(GPIOD_PIN10, 0) | \ - PIN_AFIO_AF(GPIOD_NAND_CLE, 12) | \ - PIN_AFIO_AF(GPIOD_NAND_ALE, 12) | \ - PIN_AFIO_AF(GPIOD_PIN13, 0) | \ - PIN_AFIO_AF(GPIOD_NAND_IO0, 12) | \ - PIN_AFIO_AF(GPIOD_NAND_IO1, 12)) + PIN_AFIO_AF(GPIOD_MEM_OE, 12) | \ + PIN_AFIO_AF(GPIOD_MEM_WE, 12) | \ + PIN_AFIO_AF(GPIOD_NAND_RB_NWAIT, 0) | \ + PIN_AFIO_AF(GPIOD_NAND_CE1, 12)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_MEM_D13, 12) | \ + PIN_AFIO_AF(GPIOD_MEM_D14, 12) | \ + PIN_AFIO_AF(GPIOD_MEM_D15, 12) | \ + PIN_AFIO_AF(GPIOD_MEM_A16, 12) | \ + PIN_AFIO_AF(GPIOD_MEM_A17, 12) | \ + PIN_AFIO_AF(GPIOD_PIN13, 0) | \ + PIN_AFIO_AF(GPIOD_MEM_D0, 12) | \ + PIN_AFIO_AF(GPIOD_MEM_D1, 12)) /* * GPIOE setup: */ -#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_MPU6050_INT1) | \ - PIN_MODE_INPUT(GPIOE_MPU6050_INT2) | \ +#define VAL_GPIOE_MODER (PIN_MODE_ALTERNATE(GPIOE_SRAM_LB) | \ + PIN_MODE_ALTERNATE(GPIOE_SRAM_UB) | \ PIN_MODE_INPUT(GPIOE_PIN2) | \ - PIN_MODE_INPUT(GPIOE_SPI1_INT) | \ - PIN_MODE_INPUT(GPIOE_PPS_IN) | \ - PIN_MODE_INPUT(GPIOE_DATA_SENT_IN) | \ - PIN_MODE_INPUT(GPIOE_NAND_RB_INT) | \ - PIN_MODE_ALTERNATE(GPIOE_NAND_IO4) | \ - PIN_MODE_ALTERNATE(GPIOE_NAND_IO5) | \ - PIN_MODE_ALTERNATE(GPIOE_NAND_IO6) | \ - PIN_MODE_ALTERNATE(GPIOE_NAND_IO7) | \ - PIN_MODE_OUTPUT(GPIOE_LED_R) | \ - PIN_MODE_OUTPUT(GPIOE_LED_G) | \ - PIN_MODE_ALTERNATE(GPIOE_FLASH_WP) | \ - PIN_MODE_ALTERNATE(GPIOE_FLASH_RST) | \ - PIN_MODE_INPUT(GPIOE_PIN15)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_MPU6050_INT1) | \ - PIN_OTYPE_PUSHPULL(GPIOE_MPU6050_INT2) | \ + PIN_MODE_INPUT(GPIOE_PIN3) | \ + PIN_MODE_INPUT(GPIOE_PIN4) | \ + PIN_MODE_INPUT(GPIOE_PIN5) | \ + PIN_MODE_INPUT(GPIOE_PIN6) | \ + PIN_MODE_ALTERNATE(GPIOE_MEM_D4) | \ + PIN_MODE_ALTERNATE(GPIOE_MEM_D5) | \ + PIN_MODE_ALTERNATE(GPIOE_MEM_D6) | \ + PIN_MODE_ALTERNATE(GPIOE_MEM_D7) | \ + PIN_MODE_ALTERNATE(GPIOE_MEM_D8) | \ + PIN_MODE_ALTERNATE(GPIOE_MEM_D9) | \ + PIN_MODE_ALTERNATE(GPIOE_MEM_D10) | \ + PIN_MODE_ALTERNATE(GPIOE_MEM_D11) | \ + PIN_MODE_ALTERNATE(GPIOE_MEM_D12)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_SRAM_LB) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SRAM_UB) | \ PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOE_SPI1_INT) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PPS_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOE_DATA_SENT_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOE_NAND_RB_INT) | \ - PIN_OTYPE_PUSHPULL(GPIOE_NAND_IO4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_NAND_IO5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_NAND_IO6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_NAND_IO7) | \ - PIN_OTYPE_PUSHPULL(GPIOE_LED_R) | \ - PIN_OTYPE_PUSHPULL(GPIOE_LED_G) | \ - PIN_OTYPE_PUSHPULL(GPIOE_FLASH_WP) | \ - PIN_OTYPE_PUSHPULL(GPIOE_FLASH_RST) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_100M(GPIOE_MPU6050_INT1) | \ - PIN_OSPEED_100M(GPIOE_MPU6050_INT2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_MEM_D4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_MEM_D5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_MEM_D6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_MEM_D7) | \ + PIN_OTYPE_PUSHPULL(GPIOE_MEM_D8) | \ + PIN_OTYPE_PUSHPULL(GPIOE_MEM_D9) | \ + PIN_OTYPE_PUSHPULL(GPIOE_MEM_D10) | \ + PIN_OTYPE_PUSHPULL(GPIOE_MEM_D11) | \ + PIN_OTYPE_PUSHPULL(GPIOE_MEM_D12)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_100M(GPIOE_SRAM_LB) | \ + PIN_OSPEED_100M(GPIOE_SRAM_UB) | \ PIN_OSPEED_100M(GPIOE_PIN2) | \ - PIN_OSPEED_100M(GPIOE_SPI1_INT) | \ - PIN_OSPEED_100M(GPIOE_PPS_IN) | \ - PIN_OSPEED_100M(GPIOE_DATA_SENT_IN) | \ - PIN_OSPEED_100M(GPIOE_NAND_RB_INT) | \ - PIN_OSPEED_100M(GPIOE_NAND_IO4) | \ - PIN_OSPEED_100M(GPIOE_NAND_IO5) | \ - PIN_OSPEED_100M(GPIOE_NAND_IO6) | \ - PIN_OSPEED_100M(GPIOE_NAND_IO7) | \ - PIN_OSPEED_2M(GPIOE_LED_R) | \ - PIN_OSPEED_2M(GPIOE_LED_G) | \ - PIN_OSPEED_2M(GPIOE_FLASH_WP) | \ - PIN_OSPEED_2M(GPIOE_FLASH_RST) | \ - PIN_OSPEED_100M(GPIOE_PIN15)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLDOWN(GPIOE_MPU6050_INT1) | \ - PIN_PUPDR_PULLDOWN(GPIOE_MPU6050_INT2) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOE_SPI1_INT) | \ - PIN_PUPDR_PULLUP(GPIOE_PPS_IN) | \ - PIN_PUPDR_PULLUP(GPIOE_DATA_SENT_IN) | \ - PIN_PUPDR_PULLUP(GPIOE_NAND_RB_INT) | \ - PIN_PUPDR_PULLUP(GPIOE_NAND_IO4) | \ - PIN_PUPDR_PULLUP(GPIOE_NAND_IO5) | \ - PIN_PUPDR_PULLUP(GPIOE_NAND_IO6) | \ - PIN_PUPDR_PULLUP(GPIOE_NAND_IO7) | \ - PIN_PUPDR_PULLDOWN(GPIOE_LED_R) | \ - PIN_PUPDR_PULLDOWN(GPIOE_LED_G) | \ - PIN_PUPDR_PULLUP(GPIOE_FLASH_WP) | \ - PIN_PUPDR_PULLUP(GPIOE_FLASH_RST) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN15)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_MPU6050_INT1) | \ - PIN_ODR_HIGH(GPIOE_MPU6050_INT2) | \ + PIN_OSPEED_100M(GPIOE_PIN3) | \ + PIN_OSPEED_100M(GPIOE_PIN4) | \ + PIN_OSPEED_100M(GPIOE_PIN5) | \ + PIN_OSPEED_100M(GPIOE_PIN6) | \ + PIN_OSPEED_100M(GPIOE_MEM_D4) | \ + PIN_OSPEED_100M(GPIOE_MEM_D5) | \ + PIN_OSPEED_100M(GPIOE_MEM_D6) | \ + PIN_OSPEED_100M(GPIOE_MEM_D7) | \ + PIN_OSPEED_100M(GPIOE_MEM_D8) | \ + PIN_OSPEED_100M(GPIOE_MEM_D9) | \ + PIN_OSPEED_100M(GPIOE_MEM_D10) | \ + PIN_OSPEED_100M(GPIOE_MEM_D11) | \ + PIN_OSPEED_100M(GPIOE_MEM_D12)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_SRAM_LB) | \ + PIN_PUPDR_PULLUP(GPIOE_SRAM_UB) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOE_MEM_D4) | \ + PIN_PUPDR_PULLUP(GPIOE_MEM_D5) | \ + PIN_PUPDR_PULLUP(GPIOE_MEM_D6) | \ + PIN_PUPDR_PULLUP(GPIOE_MEM_D7) | \ + PIN_PUPDR_PULLUP(GPIOE_MEM_D8) | \ + PIN_PUPDR_PULLUP(GPIOE_MEM_D9) | \ + PIN_PUPDR_PULLUP(GPIOE_MEM_D10) | \ + PIN_PUPDR_PULLUP(GPIOE_MEM_D11) | \ + PIN_PUPDR_PULLUP(GPIOE_MEM_D12)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_SRAM_LB) | \ + PIN_ODR_HIGH(GPIOE_SRAM_UB) | \ PIN_ODR_HIGH(GPIOE_PIN2) | \ - PIN_ODR_HIGH(GPIOE_SPI1_INT) | \ - PIN_ODR_HIGH(GPIOE_PPS_IN) | \ - PIN_ODR_HIGH(GPIOE_DATA_SENT_IN) | \ - PIN_ODR_HIGH(GPIOE_NAND_RB_INT) | \ - PIN_ODR_HIGH(GPIOE_NAND_IO4) | \ - PIN_ODR_HIGH(GPIOE_NAND_IO5) | \ - PIN_ODR_HIGH(GPIOE_NAND_IO6) | \ - PIN_ODR_HIGH(GPIOE_NAND_IO7) | \ - PIN_ODR_LOW(GPIOE_LED_R) | \ - PIN_ODR_LOW(GPIOE_LED_G) | \ - PIN_ODR_HIGH(GPIOE_FLASH_WP) | \ - PIN_ODR_HIGH(GPIOE_FLASH_RST) | \ - PIN_ODR_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_MPU6050_INT1, 0) | \ - PIN_AFIO_AF(GPIOE_MPU6050_INT2, 0) | \ + PIN_ODR_HIGH(GPIOE_PIN3) | \ + PIN_ODR_HIGH(GPIOE_PIN4) | \ + PIN_ODR_HIGH(GPIOE_PIN5) | \ + PIN_ODR_HIGH(GPIOE_PIN6) | \ + PIN_ODR_HIGH(GPIOE_MEM_D4) | \ + PIN_ODR_HIGH(GPIOE_MEM_D5) | \ + PIN_ODR_HIGH(GPIOE_MEM_D6) | \ + PIN_ODR_HIGH(GPIOE_MEM_D7) | \ + PIN_ODR_HIGH(GPIOE_MEM_D8) | \ + PIN_ODR_HIGH(GPIOE_MEM_D9) | \ + PIN_ODR_HIGH(GPIOE_MEM_D10) | \ + PIN_ODR_HIGH(GPIOE_MEM_D11) | \ + PIN_ODR_HIGH(GPIOE_MEM_D12)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_SRAM_LB, 12) | \ + PIN_AFIO_AF(GPIOE_SRAM_UB, 12) | \ PIN_AFIO_AF(GPIOE_PIN2, 0) | \ - PIN_AFIO_AF(GPIOE_SPI1_INT, 0) | \ - PIN_AFIO_AF(GPIOE_PPS_IN, 0) | \ - PIN_AFIO_AF(GPIOE_DATA_SENT_IN, 0) | \ - PIN_AFIO_AF(GPIOE_NAND_RB_INT, 0) | \ - PIN_AFIO_AF(GPIOE_NAND_IO4, 12)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_NAND_IO5, 12) | \ - PIN_AFIO_AF(GPIOE_NAND_IO6, 12) | \ - PIN_AFIO_AF(GPIOE_NAND_IO7, 12) | \ - PIN_AFIO_AF(GPIOE_LED_R, 0) | \ - PIN_AFIO_AF(GPIOE_LED_G, 0) | \ - PIN_AFIO_AF(GPIOE_FLASH_WP, 0) | \ - PIN_AFIO_AF(GPIOE_FLASH_RST, 0) | \ - PIN_AFIO_AF(GPIOE_PIN15, 0)) + PIN_AFIO_AF(GPIOE_PIN3, 0) | \ + PIN_AFIO_AF(GPIOE_PIN4, 0) | \ + PIN_AFIO_AF(GPIOE_PIN5, 0) | \ + PIN_AFIO_AF(GPIOE_PIN6, 0) | \ + PIN_AFIO_AF(GPIOE_MEM_D4, 12)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_MEM_D5, 12) | \ + PIN_AFIO_AF(GPIOE_MEM_D6, 12) | \ + PIN_AFIO_AF(GPIOE_MEM_D7, 12) | \ + PIN_AFIO_AF(GPIOE_MEM_D8, 12) | \ + PIN_AFIO_AF(GPIOE_MEM_D9, 12) | \ + PIN_AFIO_AF(GPIOE_MEM_D10, 12) | \ + PIN_AFIO_AF(GPIOE_MEM_D11, 12) | \ + PIN_AFIO_AF(GPIOE_MEM_D12, 12)) /* * GPIOF setup: */ -#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \ - PIN_MODE_INPUT(GPIOF_PIN1) | \ - PIN_MODE_INPUT(GPIOF_PIN2) | \ - PIN_MODE_INPUT(GPIOF_PIN3) | \ - PIN_MODE_INPUT(GPIOF_PIN4) | \ - PIN_MODE_INPUT(GPIOF_PIN5) | \ +#define VAL_GPIOF_MODER (PIN_MODE_ALTERNATE(GPIOF_MEM_A0) | \ + PIN_MODE_ALTERNATE(GPIOF_MEM_A1) | \ + PIN_MODE_ALTERNATE(GPIOF_MEM_A2) | \ + PIN_MODE_ALTERNATE(GPIOF_MEM_A3) | \ + PIN_MODE_ALTERNATE(GPIOF_MEM_A4) | \ + PIN_MODE_ALTERNATE(GPIOF_MEM_A5) | \ PIN_MODE_INPUT(GPIOF_PIN6) | \ PIN_MODE_INPUT(GPIOF_PIN7) | \ PIN_MODE_INPUT(GPIOF_PIN8) | \ PIN_MODE_INPUT(GPIOF_PIN9) | \ PIN_MODE_INPUT(GPIOF_PIN10) | \ PIN_MODE_INPUT(GPIOF_PIN11) | \ - PIN_MODE_INPUT(GPIOF_PIN12) | \ - PIN_MODE_INPUT(GPIOF_PIN13) | \ - PIN_MODE_INPUT(GPIOF_PIN14) | \ - PIN_MODE_INPUT(GPIOF_PIN15)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ + PIN_MODE_ALTERNATE(GPIOF_MEM_A6) | \ + PIN_MODE_ALTERNATE(GPIOF_MEM_A7) | \ + PIN_MODE_ALTERNATE(GPIOF_MEM_A8) | \ + PIN_MODE_ALTERNATE(GPIOF_MEM_A9)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_MEM_A0) | \ + PIN_OTYPE_PUSHPULL(GPIOF_MEM_A1) | \ + PIN_OTYPE_PUSHPULL(GPIOF_MEM_A2) | \ + PIN_OTYPE_PUSHPULL(GPIOF_MEM_A3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_MEM_A4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_MEM_A5) | \ PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(GPIOF_PIN0) | \ - PIN_OSPEED_100M(GPIOF_PIN1) | \ - PIN_OSPEED_100M(GPIOF_PIN2) | \ - PIN_OSPEED_100M(GPIOF_PIN3) | \ - PIN_OSPEED_100M(GPIOF_PIN4) | \ - PIN_OSPEED_100M(GPIOF_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_MEM_A6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_MEM_A7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_MEM_A8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_MEM_A9)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(GPIOF_MEM_A0) | \ + PIN_OSPEED_100M(GPIOF_MEM_A1) | \ + PIN_OSPEED_100M(GPIOF_MEM_A2) | \ + PIN_OSPEED_100M(GPIOF_MEM_A3) | \ + PIN_OSPEED_100M(GPIOF_MEM_A4) | \ + PIN_OSPEED_100M(GPIOF_MEM_A5) | \ PIN_OSPEED_100M(GPIOF_PIN6) | \ PIN_OSPEED_100M(GPIOF_PIN7) | \ PIN_OSPEED_100M(GPIOF_PIN8) | \ PIN_OSPEED_100M(GPIOF_PIN9) | \ PIN_OSPEED_100M(GPIOF_PIN10) | \ PIN_OSPEED_100M(GPIOF_PIN11) | \ - PIN_OSPEED_100M(GPIOF_PIN12) | \ - PIN_OSPEED_100M(GPIOF_PIN13) | \ - PIN_OSPEED_100M(GPIOF_PIN14) | \ - PIN_OSPEED_100M(GPIOF_PIN15)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN15)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ - PIN_ODR_HIGH(GPIOF_PIN1) | \ - PIN_ODR_HIGH(GPIOF_PIN2) | \ - PIN_ODR_HIGH(GPIOF_PIN3) | \ - PIN_ODR_HIGH(GPIOF_PIN4) | \ - PIN_ODR_HIGH(GPIOF_PIN5) | \ + PIN_OSPEED_100M(GPIOF_MEM_A6) | \ + PIN_OSPEED_100M(GPIOF_MEM_A7) | \ + PIN_OSPEED_100M(GPIOF_MEM_A8) | \ + PIN_OSPEED_100M(GPIOF_MEM_A9)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_MEM_A0) | \ + PIN_PUPDR_PULLUP(GPIOF_MEM_A1) | \ + PIN_PUPDR_PULLUP(GPIOF_MEM_A2) | \ + PIN_PUPDR_PULLUP(GPIOF_MEM_A3) | \ + PIN_PUPDR_PULLUP(GPIOF_MEM_A4) | \ + PIN_PUPDR_PULLUP(GPIOF_MEM_A5) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOF_MEM_A6) | \ + PIN_PUPDR_PULLUP(GPIOF_MEM_A7) | \ + PIN_PUPDR_PULLUP(GPIOF_MEM_A8) | \ + PIN_PUPDR_PULLUP(GPIOF_MEM_A9)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_MEM_A0) | \ + PIN_ODR_HIGH(GPIOF_MEM_A1) | \ + PIN_ODR_HIGH(GPIOF_MEM_A2) | \ + PIN_ODR_HIGH(GPIOF_MEM_A3) | \ + PIN_ODR_HIGH(GPIOF_MEM_A4) | \ + PIN_ODR_HIGH(GPIOF_MEM_A5) | \ PIN_ODR_HIGH(GPIOF_PIN6) | \ PIN_ODR_HIGH(GPIOF_PIN7) | \ PIN_ODR_HIGH(GPIOF_PIN8) | \ PIN_ODR_HIGH(GPIOF_PIN9) | \ PIN_ODR_HIGH(GPIOF_PIN10) | \ PIN_ODR_HIGH(GPIOF_PIN11) | \ - PIN_ODR_HIGH(GPIOF_PIN12) | \ - PIN_ODR_HIGH(GPIOF_PIN13) | \ - PIN_ODR_HIGH(GPIOF_PIN14) | \ - PIN_ODR_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0) | \ - PIN_AFIO_AF(GPIOF_PIN1, 0) | \ - PIN_AFIO_AF(GPIOF_PIN2, 0) | \ - PIN_AFIO_AF(GPIOF_PIN3, 0) | \ - PIN_AFIO_AF(GPIOF_PIN4, 0) | \ - PIN_AFIO_AF(GPIOF_PIN5, 0) | \ + PIN_ODR_HIGH(GPIOF_MEM_A6) | \ + PIN_ODR_HIGH(GPIOF_MEM_A7) | \ + PIN_ODR_HIGH(GPIOF_MEM_A8) | \ + PIN_ODR_HIGH(GPIOF_MEM_A9)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_MEM_A0, 12) | \ + PIN_AFIO_AF(GPIOF_MEM_A1, 12) | \ + PIN_AFIO_AF(GPIOF_MEM_A2, 12) | \ + PIN_AFIO_AF(GPIOF_MEM_A3, 12) | \ + PIN_AFIO_AF(GPIOF_MEM_A4, 12) | \ + PIN_AFIO_AF(GPIOF_MEM_A5, 12) | \ PIN_AFIO_AF(GPIOF_PIN6, 0) | \ PIN_AFIO_AF(GPIOF_PIN7, 0)) #define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \ PIN_AFIO_AF(GPIOF_PIN9, 0) | \ PIN_AFIO_AF(GPIOF_PIN10, 0) | \ PIN_AFIO_AF(GPIOF_PIN11, 0) | \ - PIN_AFIO_AF(GPIOF_PIN12, 0) | \ - PIN_AFIO_AF(GPIOF_PIN13, 0) | \ - PIN_AFIO_AF(GPIOF_PIN14, 0) | \ - PIN_AFIO_AF(GPIOF_PIN15, 0)) + PIN_AFIO_AF(GPIOF_MEM_A6, 12) | \ + PIN_AFIO_AF(GPIOF_MEM_A7, 12) | \ + PIN_AFIO_AF(GPIOF_MEM_A8, 12) | \ + PIN_AFIO_AF(GPIOF_MEM_A9, 12)) /* * GPIOG setup: - * - * PG0 - PIN0 (input floating). - * PG1 - PIN1 (input floating). - * PG2 - PIN2 (input floating). - * PG3 - PIN3 (input floating). - * PG4 - PIN4 (input floating). - * PG5 - PIN5 (input floating). - * PG6 - PIN6 (input floating). - * PG7 - PIN7 (input floating). - * PG8 - PIN8 (input floating). - * PG9 - PIN9 (input floating). - * PG10 - PIN10 (input floating). - * PG11 - PIN11 (input floating). - * PG12 - PIN12 (input floating). - * PG13 - PIN13 (input floating). - * PG14 - PIN14 (input floating). - * PG15 - PIN15 (input floating). */ -#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \ - PIN_MODE_INPUT(GPIOG_PIN1) | \ - PIN_MODE_INPUT(GPIOG_PIN2) | \ - PIN_MODE_INPUT(GPIOG_PIN3) | \ - PIN_MODE_INPUT(GPIOG_PIN4) | \ - PIN_MODE_INPUT(GPIOG_PIN5) | \ - PIN_MODE_INPUT(GPIOG_PIN6) | \ - PIN_MODE_INPUT(GPIOG_PIN7) | \ +#define VAL_GPIOG_MODER (PIN_MODE_ALTERNATE(GPIOG_MEM_A10) | \ + PIN_MODE_ALTERNATE(GPIOG_MEM_A11) | \ + PIN_MODE_ALTERNATE(GPIOG_MEM_A12) | \ + PIN_MODE_ALTERNATE(GPIOG_MEM_A13) | \ + PIN_MODE_ALTERNATE(GPIOG_MEM_A14) | \ + PIN_MODE_ALTERNATE(GPIOG_MEM_A15) | \ + PIN_MODE_ALTERNATE(GPIOG_NAND_RB1) | \ + PIN_MODE_ALTERNATE(GPIOG_NAND_RB2) | \ PIN_MODE_INPUT(GPIOG_PIN8) | \ - PIN_MODE_INPUT(GPIOG_PIN9) | \ + PIN_MODE_ALTERNATE(GPIOG_NAND_CE2) | \ PIN_MODE_INPUT(GPIOG_PIN10) | \ PIN_MODE_INPUT(GPIOG_PIN11) | \ - PIN_MODE_INPUT(GPIOG_PIN12) | \ + PIN_MODE_ALTERNATE(GPIOG_SRAM_CS1) | \ PIN_MODE_INPUT(GPIOG_PIN13) | \ PIN_MODE_INPUT(GPIOG_PIN14) | \ PIN_MODE_INPUT(GPIOG_PIN15)) -#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \ +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_MEM_A10) | \ + PIN_OTYPE_PUSHPULL(GPIOG_MEM_A11) | \ + PIN_OTYPE_PUSHPULL(GPIOG_MEM_A12) | \ + PIN_OTYPE_PUSHPULL(GPIOG_MEM_A13) | \ + PIN_OTYPE_PUSHPULL(GPIOG_MEM_A14) | \ + PIN_OTYPE_PUSHPULL(GPIOG_MEM_A15) | \ + PIN_OTYPE_PUSHPULL(GPIOG_NAND_RB1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_NAND_RB2) | \ PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOG_NAND_CE2) | \ PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOG_SRAM_CS1) | \ PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \ PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) -#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_100M(GPIOG_PIN0) | \ - PIN_OSPEED_100M(GPIOG_PIN1) | \ - PIN_OSPEED_100M(GPIOG_PIN2) | \ - PIN_OSPEED_100M(GPIOG_PIN3) | \ - PIN_OSPEED_100M(GPIOG_PIN4) | \ - PIN_OSPEED_100M(GPIOG_PIN5) | \ - PIN_OSPEED_100M(GPIOG_PIN6) | \ - PIN_OSPEED_100M(GPIOG_PIN7) | \ +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_100M(GPIOG_MEM_A10) | \ + PIN_OSPEED_100M(GPIOG_MEM_A11) | \ + PIN_OSPEED_100M(GPIOG_MEM_A12) | \ + PIN_OSPEED_100M(GPIOG_MEM_A13) | \ + PIN_OSPEED_100M(GPIOG_MEM_A14) | \ + PIN_OSPEED_100M(GPIOG_MEM_A15) | \ + PIN_OSPEED_100M(GPIOG_NAND_RB1) | \ + PIN_OSPEED_100M(GPIOG_NAND_RB2) | \ PIN_OSPEED_100M(GPIOG_PIN8) | \ - PIN_OSPEED_100M(GPIOG_PIN9) | \ + PIN_OSPEED_100M(GPIOG_NAND_CE2) | \ PIN_OSPEED_100M(GPIOG_PIN10) | \ PIN_OSPEED_100M(GPIOG_PIN11) | \ - PIN_OSPEED_100M(GPIOG_PIN12) | \ + PIN_OSPEED_100M(GPIOG_SRAM_CS1) | \ PIN_OSPEED_100M(GPIOG_PIN13) | \ PIN_OSPEED_100M(GPIOG_PIN14) | \ PIN_OSPEED_100M(GPIOG_PIN15)) -#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN15)) -#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ - PIN_ODR_HIGH(GPIOG_PIN1) | \ - PIN_ODR_HIGH(GPIOG_PIN2) | \ - PIN_ODR_HIGH(GPIOG_PIN3) | \ - PIN_ODR_HIGH(GPIOG_PIN4) | \ - PIN_ODR_HIGH(GPIOG_PIN5) | \ - PIN_ODR_HIGH(GPIOG_PIN6) | \ - PIN_ODR_HIGH(GPIOG_PIN7) | \ + +#if STM32_NAND_USE_EXT_INT +#define NAND_RB1_PUPDR(pin) (PIN_PUPDR_FLOATING(pin)) +#else +#define NAND_RB1_PUPDR(pin) (PIN_PUPDR_PULLUP(pin)) +#endif +#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_MEM_A10) | \ + PIN_PUPDR_PULLUP(GPIOG_MEM_A11) | \ + PIN_PUPDR_PULLUP(GPIOG_MEM_A12) | \ + PIN_PUPDR_PULLUP(GPIOG_MEM_A13) | \ + PIN_PUPDR_PULLUP(GPIOG_MEM_A14) | \ + PIN_PUPDR_PULLUP(GPIOG_MEM_A15) | \ + NAND_RB1_PUPDR(GPIOG_NAND_RB1) | \ + PIN_PUPDR_PULLUP(GPIOG_NAND_RB2) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOG_NAND_CE2) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOG_SRAM_CS1) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN15)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_MEM_A10) | \ + PIN_ODR_HIGH(GPIOG_MEM_A11) | \ + PIN_ODR_HIGH(GPIOG_MEM_A12) | \ + PIN_ODR_HIGH(GPIOG_MEM_A13) | \ + PIN_ODR_HIGH(GPIOG_MEM_A14) | \ + PIN_ODR_HIGH(GPIOG_MEM_A15) | \ + PIN_ODR_HIGH(GPIOG_NAND_RB1) | \ + PIN_ODR_HIGH(GPIOG_NAND_RB2) | \ PIN_ODR_HIGH(GPIOG_PIN8) | \ - PIN_ODR_HIGH(GPIOG_PIN9) | \ + PIN_ODR_HIGH(GPIOG_NAND_CE2) | \ PIN_ODR_HIGH(GPIOG_PIN10) | \ PIN_ODR_HIGH(GPIOG_PIN11) | \ - PIN_ODR_HIGH(GPIOG_PIN12) | \ + PIN_ODR_HIGH(GPIOG_SRAM_CS1) | \ PIN_ODR_HIGH(GPIOG_PIN13) | \ PIN_ODR_HIGH(GPIOG_PIN14) | \ PIN_ODR_HIGH(GPIOG_PIN15)) -#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0) | \ - PIN_AFIO_AF(GPIOG_PIN1, 0) | \ - PIN_AFIO_AF(GPIOG_PIN2, 0) | \ - PIN_AFIO_AF(GPIOG_PIN3, 0) | \ - PIN_AFIO_AF(GPIOG_PIN4, 0) | \ - PIN_AFIO_AF(GPIOG_PIN5, 0) | \ - PIN_AFIO_AF(GPIOG_PIN6, 0) | \ - PIN_AFIO_AF(GPIOG_PIN7, 0)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_MEM_A10, 12) | \ + PIN_AFIO_AF(GPIOG_MEM_A11, 12) | \ + PIN_AFIO_AF(GPIOG_MEM_A12, 12) | \ + PIN_AFIO_AF(GPIOG_MEM_A13, 12) | \ + PIN_AFIO_AF(GPIOG_MEM_A14, 12) | \ + PIN_AFIO_AF(GPIOG_MEM_A15, 12) | \ + PIN_AFIO_AF(GPIOG_NAND_RB1, 12) | \ + PIN_AFIO_AF(GPIOG_NAND_RB2, 12)) #define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0) | \ - PIN_AFIO_AF(GPIOG_PIN9, 0) | \ + PIN_AFIO_AF(GPIOG_NAND_CE2, 12) | \ PIN_AFIO_AF(GPIOG_PIN10, 0) | \ PIN_AFIO_AF(GPIOG_PIN11, 0) | \ - PIN_AFIO_AF(GPIOG_PIN12, 0) | \ + PIN_AFIO_AF(GPIOG_SRAM_CS1, 12) | \ PIN_AFIO_AF(GPIOG_PIN13, 0) | \ PIN_AFIO_AF(GPIOG_PIN14, 0) | \ PIN_AFIO_AF(GPIOG_PIN15, 0)) /* * GPIOH setup: - * - * PH0 - OSC_IN (input floating). - * PH1 - OSC_OUT (input floating). - * PH2 - PIN2 (input floating). - * PH3 - PIN3 (input floating). - * PH4 - PIN4 (input floating). - * PH5 - PIN5 (input floating). - * PH6 - PIN6 (input floating). - * PH7 - PIN7 (input floating). - * PH8 - PIN8 (input floating). - * PH9 - PIN9 (input floating). - * PH10 - PIN10 (input floating). - * PH11 - PIN11 (input floating). - * PH12 - PIN12 (input floating). - * PH13 - PIN13 (input floating). - * PH14 - PIN14 (input floating). - * PH15 - PIN15 (input floating). */ #define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ @@ -1063,23 +1041,6 @@ /* * GPIOI setup: - * - * PI0 - PIN0 (input floating). - * PI1 - PIN1 (input floating). - * PI2 - PIN2 (input floating). - * PI3 - PIN3 (input floating). - * PI4 - PIN4 (input floating). - * PI5 - PIN5 (input floating). - * PI6 - PIN6 (input floating). - * PI7 - PIN7 (input floating). - * PI8 - PIN8 (input floating). - * PI9 - PIN9 (input floating). - * PI10 - PIN10 (input floating). - * PI11 - PIN11 (input floating). - * PI12 - PIN12 (input floating). - * PI13 - PIN13 (input floating). - * PI14 - PIN14 (input floating). - * PI15 - PIN15 (input floating). */ #define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ PIN_MODE_INPUT(GPIOI_PIN1) | \ @@ -1091,8 +1052,8 @@ PIN_MODE_INPUT(GPIOI_PIN7) | \ PIN_MODE_INPUT(GPIOI_PIN8) | \ PIN_MODE_INPUT(GPIOI_PIN9) | \ - PIN_MODE_INPUT(GPIOI_PIN10) | \ - PIN_MODE_INPUT(GPIOI_PIN11) | \ + PIN_MODE_OUTPUT(GPIOI_LED_R) | \ + PIN_MODE_OUTPUT(GPIOI_LED_G) | \ PIN_MODE_INPUT(GPIOI_PIN12) | \ PIN_MODE_INPUT(GPIOI_PIN13) | \ PIN_MODE_INPUT(GPIOI_PIN14) | \ @@ -1107,8 +1068,8 @@ PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOI_LED_R) | \ + PIN_OTYPE_PUSHPULL(GPIOI_LED_G) | \ PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ @@ -1123,8 +1084,8 @@ PIN_OSPEED_100M(GPIOI_PIN7) | \ PIN_OSPEED_100M(GPIOI_PIN8) | \ PIN_OSPEED_100M(GPIOI_PIN9) | \ - PIN_OSPEED_100M(GPIOI_PIN10) | \ - PIN_OSPEED_100M(GPIOI_PIN11) | \ + PIN_OSPEED_100M(GPIOI_LED_R) | \ + PIN_OSPEED_100M(GPIOI_LED_G) | \ PIN_OSPEED_100M(GPIOI_PIN12) | \ PIN_OSPEED_100M(GPIOI_PIN13) | \ PIN_OSPEED_100M(GPIOI_PIN14) | \ @@ -1139,8 +1100,8 @@ PIN_PUPDR_FLOATING(GPIOI_PIN7) | \ PIN_PUPDR_FLOATING(GPIOI_PIN8) | \ PIN_PUPDR_FLOATING(GPIOI_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOI_LED_R) | \ + PIN_PUPDR_FLOATING(GPIOI_LED_G) | \ PIN_PUPDR_FLOATING(GPIOI_PIN12) | \ PIN_PUPDR_FLOATING(GPIOI_PIN13) | \ PIN_PUPDR_FLOATING(GPIOI_PIN14) | \ @@ -1155,8 +1116,8 @@ PIN_ODR_HIGH(GPIOI_PIN7) | \ PIN_ODR_HIGH(GPIOI_PIN8) | \ PIN_ODR_HIGH(GPIOI_PIN9) | \ - PIN_ODR_HIGH(GPIOI_PIN10) | \ - PIN_ODR_HIGH(GPIOI_PIN11) | \ + PIN_ODR_LOW(GPIOI_LED_R) | \ + PIN_ODR_LOW(GPIOI_LED_G) | \ PIN_ODR_HIGH(GPIOI_PIN12) | \ PIN_ODR_HIGH(GPIOI_PIN13) | \ PIN_ODR_HIGH(GPIOI_PIN14) | \ @@ -1171,8 +1132,8 @@ PIN_AFIO_AF(GPIOI_PIN7, 0)) #define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0) | \ PIN_AFIO_AF(GPIOI_PIN9, 0) | \ - PIN_AFIO_AF(GPIOI_PIN10, 0) | \ - PIN_AFIO_AF(GPIOI_PIN11, 0) | \ + PIN_AFIO_AF(GPIOI_LED_R, 0) | \ + PIN_AFIO_AF(GPIOI_LED_G, 0) | \ PIN_AFIO_AF(GPIOI_PIN12, 0) | \ PIN_AFIO_AF(GPIOI_PIN13, 0) | \ PIN_AFIO_AF(GPIOI_PIN14, 0) | \ @@ -1180,8 +1141,8 @@ #define nand_wp_assert() palClearPad(GPIOB, GPIOB_NAND_WP) #define nand_wp_release() palSetPad(GPIOB, GPIOB_NAND_WP) -#define red_led_on() palSetPad(GPIOE, GPIOE_LED_R) -#define red_led_off() palClearPad(GPIOE, GPIOE_LED_R) +#define red_led_on() palSetPad(GPIOI, GPIOI_LED_R) +#define red_led_off() palClearPad(GPIOI, GPIOI_LED_R) #if !defined(_FROM_ASM_) #ifdef __cplusplus |