RTC. Final polishing.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/rtc_dev@3275 35acf78f-673a-0410-8e92-d51de3d6d3f4

5 files changed, 40 insertions, 43 deletions

diff --git a/os/hal/dox/rtc.dox b/os/hal/dox/rtc.dox
index 3663374de..3572aca18 100644
--- a/os/hal/dox/rtc.dox
+++ b/os/hal/dox/rtc.dox
@@ -24,6 +24,8 @@
  * @details This module defines an abstract interface for Real Time Clock cell.

  *          If you do not need callback functionality than disable 

  *          @p RTC_SUPPORTS_CALLBACKS option in @p halconf.h.

+ *          In @p halconf.h you also can select clock source for RTC in

+ *          @p RTC_CLOCK_SOURCE option.

  *

  * @pre     In order to use the RTC driver the @p HAL_USE_RTC option

  *          must be enabled in @p halconf.h. 

diff --git a/os/hal/include/rtc.h b/os/hal/include/rtc.h
index aa1a61f49..ad66fcd8b 100644
--- a/os/hal/include/rtc.h
+++ b/os/hal/include/rtc.h
@@ -37,16 +37,6 @@
 /*===========================================================================*/

 /* Driver constants.                                                         */

 /*===========================================================================*/

-/* TODO: move this to hal_lld_f103.h & mcuconf.h */

-#define STM32_LSECLK             32768       /**< Low speed external clock.  */

-

-

-/* RCC_CFGR register bits definitions.*/

-#define STM32_RTC_NONE           (0 << 8)    /**< */

-#define STM32_RTC_LSE            (1 << 8)    /**< LSE oscillator clock used as RTC clock */

-#define STM32_RTC_LSI            (2 << 8)    /**< LSI oscillator clock used as RTC clock */

-#define STM32_RTC_HSE            (3 << 8)    /**< HSE oscillator clock divided by 128 used as RTC clock */

-

 

 /*===========================================================================*/

 /* Driver pre-compile time settings.                                         */

diff --git a/os/hal/platforms/STM32/rtc_lld.c b/os/hal/platforms/STM32/rtc_lld.c
index ed458190d..ce483d3f9 100644
--- a/os/hal/platforms/STM32/rtc_lld.c
+++ b/os/hal/platforms/STM32/rtc_lld.c
@@ -30,31 +30,6 @@
 #include "hal.h"

 

 

-// TODO: defines look in 4492 stm32f10x.h

-

-

-/** The RTCCLK clock source can be either the HSE/128, LSE or LSI clocks. This is selected

-by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR).

-This selection

-CANNOT

-be modified without resetting the Backup domain.

-

-The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not.

-Consequently:

-* If LSE is selected as RTC clock:

-– The RTC continues to work even if the VDD supply is switched off, provided the

-VBAT supply is maintained.

-* If LSI is selected as Auto-Wakeup unit (AWU) clock:

-– The AWU state is not guaranteed if the VDD supply is powered off. Refer to

-Section 6.2.5: LSI clock on page 87 for more details on LSI calibration.

-* If the HSE clock divided by 128 is used as the RTC clock:

-– The RTC state is not guaranteed if the VDD supply is powered off or if the internal

-voltage regulator is powered off (removing power from the 1.8 V domain).

-– The DPB bit (Disable backup domain write protection) in the Power controller

-register must be set to 1 (refer to Section 4.4.1: Power control register

-(PWR_CR)).

-*/

-

 #if HAL_USE_RTC || defined(__DOXYGEN__)

 

 /*===========================================================================*/

@@ -137,13 +112,37 @@ void rtc_lld_init(void){
   PWR->CR |= PWR_CR_DBP;                                    /* enable access */

 

   if (!(RCC->BDCR & (RCC_BDCR_RTCEN | RCC_BDCR_LSEON))){    /* BKP domain was reseted */

-    RCC->BDCR |= STM32_RTC_LSE;                             /* select clocking from LSE */

+    RCC->BDCR |= RTC_CLOCK_SOURCE;                          /* select clocking from LSE */

     RCC->BDCR |= RCC_BDCR_LSEON;                            /* switch LSE on */

     while(!(RCC->BDCR & RCC_BDCR_LSEON))                    /* wait for stabilization */

       ;

     RCC->BDCR |= RCC_BDCR_RTCEN;                            /* run clock */

   }

 

+  #if defined(RTC_CLOCK_SOURCE) == defined(RCC_BDCR_RTCSEL_LSE)

+    uint32_t preload = STM32_LSECLK - 1UL;

+  #elif defined(RTC_CLOCK_SOURCE) == defined(RCC_BDCR_RTCSEL_LSI)

+    uint32_t preload = STM32_LSICLK - 1UL;

+  #elif defined(RTC_CLOCK_SOURCE) == defined(RCC_BDCR_RTCSEL_HSE)

+    uint32_t preload = (STM32_HSICLK / 128UL) - 1UL;

+  #else

+    #error "RTC clock source not selected"

+  #endif /* RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_LSE */

+

+  /* Write preload register only if value changed */

+  if (preload != (((uint32_t)(RTC->PRLH)) << 16) + RTC->PRLH){

+    while(!(RTC->CRL & RTC_CRL_RTOFF))

+      ;

+

+    RTC->CRL |= RTC_CRL_CNF;                            /* switch on configure mode */

+    RTC->PRLH = (uint16_t)((preload >> 16) & 0b1111);   /* write preloader */

+    RTC->PRLL = (uint16_t)(preload & 0xFFFF);

+    RTC->CRL &= ~RTC_CRL_CNF;                           /* switch off configure mode */

+

+    while(!(RTC->CRL & RTC_CRL_RTOFF))                  /* wait for completion */

+      ;

+  }

+

   /* Ensure that RTC_CNT and RTC_DIV contain actual values after enabling

    * clocking on APB1, because these values only update when APB1 functioning.*/

   RTC->CRL &= ~(RTC_CRL_RSF);

@@ -181,7 +180,8 @@ void rtc_lld_start(RTCDriver *rtcp, const RTCConfig *rtccfgp){
     isr_flags |= RTC_CRH_SECIE;

   }

 

-  RTC->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF); /* clear all even flags*/

+  /* clear all event flags just to be safe */

+  RTC->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF);

   RTC->CRH |= isr_flags;

 }

 

@@ -201,14 +201,11 @@ void rtc_lld_stop(void){
  * @param[in] tv_sec     time value in UNIX notation.

  */

 void rtc_lld_set_time(uint32_t tv_sec){

-  uint32_t preload = STM32_LSECLK - 1UL;

 

   while(!(RTC->CRL & RTC_CRL_RTOFF))

     ;

 

   RTC->CRL |= RTC_CRL_CNF;                            /* switch on configure mode */

-  RTC->PRLH = (uint16_t)((preload >> 16) & 0b1111);   /* write preloader */

-  RTC->PRLL = (uint16_t)(preload & 0xFFFF);

   RTC->CNTH = (uint16_t)((tv_sec >> 16) & 0xFFFF);    /* write time */

   RTC->CNTL = (uint16_t)(tv_sec & 0xFFFF);

   RTC->CRL &= ~RTC_CRL_CNF;                           /* switch off configure mode */

diff --git a/os/hal/platforms/STM32/rtc_lld.h b/os/hal/platforms/STM32/rtc_lld.h
index fe51df254..a0490b29a 100644
--- a/os/hal/platforms/STM32/rtc_lld.h
+++ b/os/hal/platforms/STM32/rtc_lld.h
@@ -47,6 +47,14 @@
 #define RTC_SUPPORTS_CALLBACKS              TRUE

 #endif

 

+/**

+ * @brief   Clock source selecting. LSE by default.

+ */

+#if !defined(RTC_CLOCK_SOURCE) || defined(__DOXYGEN__)

+#define RTC_CLOCK_SOURCE                    RCC_BDCR_RTCSEL_LSE

+#endif

+

+

 /*===========================================================================*/

 /* Derived constants and error checks.                                       */

 /*===========================================================================*/

diff --git a/os/hal/src/rtc.c b/os/hal/src/rtc.c
index 0db21d4d5..f1aa03a34 100644
--- a/os/hal/src/rtc.c
+++ b/os/hal/src/rtc.c
@@ -92,14 +92,14 @@ void rtcSetTime(uint32_t tv_sec){
 /**

  * @brief Return current time in UNIX notation.

  */

-uint32_t rtcGetSec(void){

+inline uint32_t rtcGetSec(void){

   return rtc_lld_get_sec();

 }

 

 /**

  * @brief Return fractional part of current time (milliseconds).

  */

-uint16_t rtcGetMsec(void){

+inline uint16_t rtcGetMsec(void){

   return rtc_lld_get_msec();

 }

 

@@ -113,7 +113,7 @@ void rtcSetAlarm(uint32_t tv_alarm){
 /**

  * @brief Get current alarm date in UNIX notation.

  */

-uint32_t rtcGetAlarm(void){

+inline uint32_t rtcGetAlarm(void){

   return rtc_lld_get_alarm();

 }