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authorbarthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>2012-03-04 16:22:51 +0000
committerbarthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>2012-03-04 16:22:51 +0000
commit4769c8ec62147079b4f23bd71d3d44774a30506f (patch)
tree9b79f55333cc8b964d640d9914be277e32180652 /os
parentfc972f48d6c432993bcad77033ce4824cb44c5d0 (diff)
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RTC. APB1 clock check moved to rtc_lld.h
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4019 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
-rw-r--r--os/hal/platforms/STM32/RTCv2/rtc_lld.h4
-rw-r--r--os/hal/platforms/STM32F4xx/hal_lld.h3
2 files changed, 4 insertions, 3 deletions
diff --git a/os/hal/platforms/STM32/RTCv2/rtc_lld.h b/os/hal/platforms/STM32/RTCv2/rtc_lld.h
index a9346b5ac..3f0139f00 100644
--- a/os/hal/platforms/STM32/RTCv2/rtc_lld.h
+++ b/os/hal/platforms/STM32/RTCv2/rtc_lld.h
@@ -87,6 +87,10 @@
#define RTC_USE_INTERRUPTS FALSE
#endif
+#if STM32_PCLK1 < (STM32_RTCCLK * 7)
+#error "STM32_PCLK1 frequency is too low to handle RTC without ugly workaround"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h
index a29c33cde..c88ac3a96 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.h
+++ b/os/hal/platforms/STM32F4xx/hal_lld.h
@@ -1103,9 +1103,6 @@
#if STM32_PCLK1 > STM32_PCLK1_MAX
#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
#endif
-#if STM32_PCLK1 < (STM32_RTCCLK * 7)
-#error "STM32_PCLK1 frequency is too low to handle RTC without ugly workaround"
-#endif
/**
* @brief APB2 frequency.