git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5119 35acf78f-673a-0410-8e92-d51de3d6d3f4

7 files changed, 153 insertions, 196 deletions

diff --git a/os/ports/GCC/PPC/SPC56ELxx/bam.s b/os/ports/GCC/PPC/SPC56ELxx/bam.s
index 9d20aa056..9bcb9acf4 100644
--- a/os/ports/GCC/PPC/SPC56ELxx/bam.s
+++ b/os/ports/GCC/PPC/SPC56ELxx/bam.s
@@ -116,8 +116,7 @@
         mtspr       319, %r31

 

         /* HW configuration.*/

-        bl          _hwconf

-        bl          _ivorinit

+        bl          _coreinit

 

         b           _boot_address

 

diff --git a/os/ports/GCC/PPC/SPC56ELxx/core.s b/os/ports/GCC/PPC/SPC56ELxx/core.s
index 2211b8dbd..3d1bfb021 100644
--- a/os/ports/GCC/PPC/SPC56ELxx/core.s
+++ b/os/ports/GCC/PPC/SPC56ELxx/core.s
@@ -19,8 +19,8 @@
 */

 

 /**

- * @file    SPC56ELxx/hwconf.s

- * @brief   SPC56ELxx low level hardware configuration.

+ * @file    SPC56ELxx/core.s

+ * @brief   e200z4 core configuration.

  *

  * @addtogroup PPC_CORE

  * @{

@@ -153,85 +153,165 @@
 

 #if !defined(__DOXYGEN__)

 

+        .section    .handlers, "ax"

+

+        /*

+         * Unhandled exceptions handler.

+         */

+         .weak      _IVOR0

+_IVOR0:

+         .weak      _IVOR1

+_IVOR1:

+         .weak      _IVOR2

+_IVOR2:

+         .weak      _IVOR3

+_IVOR3:

+         .weak      _IVOR5

+_IVOR5:

+         .weak      _IVOR6

+_IVOR6:

+         .weak      _IVOR7

+_IVOR7:

+         .weak      _IVOR8

+_IVOR8:

+         .weak      _IVOR9

+_IVOR9:

+         .weak      _IVOR11

+_IVOR11:

+         .weak      _IVOR12

+_IVOR12:

+         .weak      _IVOR13

+_IVOR13:

+         .weak      _IVOR14

+_IVOR14:

+         .weak      _IVOR15

+_IVOR15:

+        .weak      _unhandled_exception

+        .type       _unhandled_exception, @function

+_unhandled_exception:

+        b       _unhandled_exception

+

         .section    .coreinit, "ax"

 

         .align      2

         .globl      _coreinit

         .type       _coreinit, @function

 _coreinit:

-        /* MSR settings.*/

-        lis         r3, MSR_DEFAULT@h

-        ori         r3, r3, MSR_DEFAULT@l

-        mtMSR       r3

-

-        /* TLB0 allocated to flash.*/

-        lis         r3, TLB0_MAS0@h

-        mtspr       624, r3         /* MAS0 */

-        lis         r3, TLB0_MAS1@h

-        ori         r3, r3, TLB0_MAS1@l

-        mtspr       625, r3         /* MAS1 */

-        lis         r3, TLB0_MAS2@h

-        ori         r3, r3, TLB0_MAS2@l

-        mtspr       626, r3         /* MAS2 */

-        lis         r3, TLB0_MAS3@h

-        ori         r3, r3, TLB0_MAS3@l

-        mtspr       627, r3         /* MAS3 */

+        /* MSR initialization.*/

+        lis         %r3, MSR_DEFAULT@h

+        ori         %r3, %r3, MSR_DEFAULT@l

+        mtMSR       %r3

+

+        /*

+         * IVPR initialization.

+         */

+        lis         %r3, __ivpr_base__@h

+        ori         %r3, %r3, __ivpr_base__@l

+        mtIVPR      %r3

+

+        /*

+         * IVORs initialization.

+         */

+        lis         %r3, _unhandled_exception@h

+        ori         %r3, %r3, _unhandled_exception@l

+        mtspr       400, %r3    /* IVOR0-15 */

+        mtspr       401, %r3

+        mtspr       402, %r3

+        mtspr       403, %r3

+        mtspr       404, %r3

+        mtspr       405, %r3

+        mtspr       406, %r3

+        mtspr       407, %r3

+        mtspr       408, %r3

+        mtspr       409, %r3

+        mtspr       410, %r3

+        mtspr       411, %r3

+        mtspr       412, %r3

+        mtspr       413, %r3

+        mtspr       414, %r3

+        mtspr       415, %r3

+        mtspr       528, %r3    /* IVOR32-34 */

+        mtspr       529, %r3

+        mtspr       530, %r3

+

+        /*

+         * TLB0 allocated to flash.

+         */

+        lis         %r3, TLB0_MAS0@h

+        mtspr       624, %r3         /* MAS0 */

+        lis         %r3, TLB0_MAS1@h

+        ori         %r3, %r3, TLB0_MAS1@l

+        mtspr       625, %r3         /* MAS1 */

+        lis         %r3, TLB0_MAS2@h

+        ori         %r3, %r3, TLB0_MAS2@l

+        mtspr       626, %r3         /* MAS2 */

+        lis         %r3, TLB0_MAS3@h

+        ori         %r3, %r3, TLB0_MAS3@l

+        mtspr       627, %r3         /* MAS3 */

         tlbwe

 

-        /* TLB1 allocated to external RAM, if any.*/

-        lis         r3, TLB1_MAS0@h

-        mtspr       624, r3         /* MAS0 */

-        lis         r3, TLB1_MAS1@h

-        ori         r3, r3, TLB1_MAS1@l

-        mtspr       625, r3         /* MAS1 */

-        lis         r3, TLB1_MAS2@h

-        ori         r3, r3, TLB1_MAS2@l

-        mtspr       626, r3         /* MAS2 */

-        lis         r3, TLB1_MAS3@h

-        ori         r3, r3, TLB1_MAS3@l

-        mtspr       627, r3         /* MAS3 */

+        /*

+         * TLB1 allocated to external RAM, if any.

+         */

+        lis         %r3, TLB1_MAS0@h

+        mtspr       624, %r3         /* MAS0 */

+        lis         %r3, TLB1_MAS1@h

+        ori         %r3, %r3, TLB1_MAS1@l

+        mtspr       625, %r3         /* MAS1 */

+        lis         %r3, TLB1_MAS2@h

+        ori         %r3, %r3, TLB1_MAS2@l

+        mtspr       626, %r3         /* MAS2 */

+        lis         %r3, TLB1_MAS3@h

+        ori         %r3, %r3, TLB1_MAS3@l

+        mtspr       627, %r3         /* MAS3 */

         tlbwe

 

-        /* TLB2 allocated to internal RAM.*/

-        lis         r3, TLB2_MAS0@h

-        mtspr       624, r3         /* MAS0 */

-        lis         r3, TLB2_MAS1@h

-        ori         r3, r3, TLB2_MAS1@l

-        mtspr       625, r3         /* MAS1 */

-        lis         r3, TLB2_MAS2@h

-        ori         r3, r3, TLB2_MAS2@l

-        mtspr       626, r3         /* MAS2 */

-        lis         r3, TLB2_MAS3@h

-        ori         r3, r3, TLB2_MAS3@l

-        mtspr       627, r3         /* MAS3 */

+        /*

+         * TLB2 allocated to internal RAM.

+         */

+        lis         %r3, TLB2_MAS0@h

+        mtspr       624, %r3         /* MAS0 */

+        lis         %r3, TLB2_MAS1@h

+        ori         %r3, %r3, TLB2_MAS1@l

+        mtspr       625, %r3         /* MAS1 */

+        lis         %r3, TLB2_MAS2@h

+        ori         %r3, %r3, TLB2_MAS2@l

+        mtspr       626, %r3         /* MAS2 */

+        lis         %r3, TLB2_MAS3@h

+        ori         %r3, %r3, TLB2_MAS3@l

+        mtspr       627, %r3         /* MAS3 */

         tlbwe

 

-        /* TLB3 allocated to internal Peripherals Bridge A.*/

-        lis         r3, TLB3_MAS0@h

-        mtspr       624, r3         /* MAS0 */

-        lis         r3, TLB3_MAS1@h

-        ori         r3, r3, TLB3_MAS1@l

-        mtspr       625, r3         /* MAS1 */

-        lis         r3, TLB3_MAS2@h

-        ori         r3, r3, TLB3_MAS2@l

-        mtspr       626, r3         /* MAS2 */

-        lis         r3, TLB3_MAS3@h

-        ori         r3, r3, TLB3_MAS3@l

-        mtspr       627, r3         /* MAS3 */

+        /*

+         * TLB3 allocated to internal Peripherals Bridge A.

+         */

+        lis         %r3, TLB3_MAS0@h

+        mtspr       624, %r3         /* MAS0 */

+        lis         %r3, TLB3_MAS1@h

+        ori         %r3, %r3, TLB3_MAS1@l

+        mtspr       625, %r3         /* MAS1 */

+        lis         %r3, TLB3_MAS2@h

+        ori         %r3, %r3, TLB3_MAS2@l

+        mtspr       626, %r3         /* MAS2 */

+        lis         %r3, TLB3_MAS3@h

+        ori         %r3, %r3, TLB3_MAS3@l

+        mtspr       627, %r3         /* MAS3 */

         tlbwe

 

-        /* TLB4 allocated to internal Peripherals Bridge B.*/

-        lis         r3, TLB4_MAS0@h

-        mtspr       624, r3         /* MAS0 */

-        lis         r3, TLB4_MAS1@h

-        ori         r3, r3, TLB4_MAS1@l

-        mtspr       625, r3         /* MAS1 */

-        lis         r3, TLB4_MAS2@h

-        ori         r3, r3, TLB4_MAS2@l

-        mtspr       626, r3         /* MAS2 */

-        lis         r3, TLB4_MAS3@h

-        ori         r3, r3, TLB4_MAS3@l

-        mtspr       627, r3         /* MAS3 */

+        /*

+         * TLB4 allocated to internal Peripherals Bridge B.

+         */

+        lis         %r3, TLB4_MAS0@h

+        mtspr       624, %r3         /* MAS0 */

+        lis         %r3, TLB4_MAS1@h

+        ori         %r3, %r3, TLB4_MAS1@l

+        mtspr       625, %r3         /* MAS1 */

+        lis         %r3, TLB4_MAS2@h

+        ori         %r3, %r3, TLB4_MAS2@l

+        mtspr       626, %r3         /* MAS2 */

+        lis         %r3, TLB4_MAS3@h

+        ori         %r3, %r3, TLB4_MAS3@l

+        mtspr       627, %r3         /* MAS3 */

         tlbwe

 

         blr

diff --git a/os/ports/GCC/PPC/SPC56ELxx/ivor.s b/os/ports/GCC/PPC/SPC56ELxx/ivor.s
deleted file mode 100644
index 7d2207441..000000000
--- a/os/ports/GCC/PPC/SPC56ELxx/ivor.s
+++ /dev/null
@@ -1,121 +0,0 @@
-/*

-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,

-                 2011,2012,2013 Giovanni Di Sirio.

-

-    This file is part of ChibiOS/RT.

-

-    ChibiOS/RT is free software; you can redistribute it and/or modify

-    it under the terms of the GNU General Public License as published by

-    the Free Software Foundation; either version 3 of the License, or

-    (at your option) any later version.

-

-    ChibiOS/RT is distributed in the hope that it will be useful,

-    but WITHOUT ANY WARRANTY; without even the implied warranty of

-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

-    GNU General Public License for more details.

-

-    You should have received a copy of the GNU General Public License

-    along with this program.  If not, see <http://www.gnu.org/licenses/>.

-*/

-

-/**

- * @file    SPC56ELxx/ivor.s

- * @brief   SPC56ELxx IVORx handlers.

- *

- * @addtogroup PPC_CORE

- * @{

- */

-

-/*

- * Imports the PPC configuration headers.

- */

-#define _FROM_ASM_

-#include "chconf.h"

-#include "chcore.h"

-

-#if !defined(__DOXYGEN__)

-        /*

-         * INTC registers address.

-         */

-        .equ  INTC_IACKR, 0xfff48010

-        .equ  INTC_EOIR,  0xfff48018

-

-        .section    .handlers, "ax"

-

-        .align      2

-        .globl      _ivorinit

-        .type       _ivorinit, @function

-_ivorinit:

-        /*

-         * IVPR initialization.

-         */

-        lis         %r4, __ivpr_base__@h

-        ori         %r4, %r4, __ivpr_base__@l

-        mtIVPR      %r4

-

-        /*

-         * IVOR default settings.

-         */

-        lis         %r4, _unhandled_exception@h

-        ori         %r4, %r4, _unhandled_exception@l

-        mtspr       400, %r4    /* IVOR0-15 */

-        mtspr       401, %r4

-        mtspr       402, %r4

-        mtspr       403, %r4

-        mtspr       404, %r4

-        mtspr       405, %r4

-        mtspr       406, %r4

-        mtspr       407, %r4

-        mtspr       408, %r4

-        mtspr       409, %r4

-        mtspr       410, %r4

-        mtspr       411, %r4

-        mtspr       412, %r4

-        mtspr       413, %r4

-        mtspr       414, %r4

-        mtspr       415, %r4

-        mtspr       528, %r4    /* IVOR32-34 */

-        mtspr       529, %r4

-        mtspr       530, %r4

-

-        blr

-

-        /*

-         * Unhandled exceptions handler.

-         */

-         .weak      _IVOR0

-_IVOR0:

-         .weak      _IVOR1

-_IVOR1:

-         .weak      _IVOR2

-_IVOR2:

-         .weak      _IVOR3

-_IVOR3:

-         .weak      _IVOR5

-_IVOR5:

-         .weak      _IVOR6

-_IVOR6:

-         .weak      _IVOR7

-_IVOR7:

-         .weak      _IVOR8

-_IVOR8:

-         .weak      _IVOR9

-_IVOR9:

-         .weak      _IVOR11

-_IVOR11:

-         .weak      _IVOR12

-_IVOR12:

-         .weak      _IVOR13

-_IVOR13:

-         .weak      _IVOR14

-_IVOR14:

-         .weak      _IVOR15

-_IVOR15:

-        .weak      _unhandled_exception

-        .type       _unhandled_exception, @function

-_unhandled_exception:

-        b       _unhandled_exception

-

-#endif /* !defined(__DOXYGEN__) */

-

-/** @} */

diff --git a/os/ports/GCC/PPC/SPC56ELxx/ld/SPC56EL54_LSM.ld b/os/ports/GCC/PPC/SPC56ELxx/ld/SPC56EL54_LSM.ld
index 1475dbbde..63d3e47fc 100644
--- a/os/ports/GCC/PPC/SPC56ELxx/ld/SPC56EL54_LSM.ld
+++ b/os/ports/GCC/PPC/SPC56ELxx/ld/SPC56EL54_LSM.ld
@@ -48,7 +48,7 @@ SECTIONS
     {

         __ivpr_base__ = .;

         KEEP(*(.bam))

-        KEEP(*(.hwconf))

+        KEEP(*(.coreinit))

         KEEP(*(.crt0))

         KEEP(*(.handlers))

         . = ALIGN(0x800);

diff --git a/os/ports/GCC/PPC/SPC56ELxx/ld/SPC56EL60_LSM.ld b/os/ports/GCC/PPC/SPC56ELxx/ld/SPC56EL60_LSM.ld
index c33227120..f0f203783 100644
--- a/os/ports/GCC/PPC/SPC56ELxx/ld/SPC56EL60_LSM.ld
+++ b/os/ports/GCC/PPC/SPC56ELxx/ld/SPC56EL60_LSM.ld
@@ -48,7 +48,7 @@ SECTIONS
     {

         __ivpr_base__ = .;

         KEEP(*(.bam))

-        KEEP(*(.hwconf))

+        KEEP(*(.coreinit))

         KEEP(*(.crt0))

         KEEP(*(.handlers))

         . = ALIGN(0x800);

diff --git a/os/ports/GCC/PPC/SPC56ELxx/ld/SPC56EL70_LSM.ld b/os/ports/GCC/PPC/SPC56ELxx/ld/SPC56EL70_LSM.ld
index 0f7c4f0d6..e39e14b4e 100644
--- a/os/ports/GCC/PPC/SPC56ELxx/ld/SPC56EL70_LSM.ld
+++ b/os/ports/GCC/PPC/SPC56ELxx/ld/SPC56EL70_LSM.ld
@@ -48,7 +48,7 @@ SECTIONS
     {

         __ivpr_base__ = .;

         KEEP(*(.bam))

-        KEEP(*(.hwconf))

+        KEEP(*(.coreinit))

         KEEP(*(.crt0))

         KEEP(*(.handlers))

         . = ALIGN(0x800);

diff --git a/os/ports/GCC/PPC/SPC56ELxx/port.mk b/os/ports/GCC/PPC/SPC56ELxx/port.mk
index 815d22ab4..5a81771db 100644
--- a/os/ports/GCC/PPC/SPC56ELxx/port.mk
+++ b/os/ports/GCC/PPC/SPC56ELxx/port.mk
@@ -2,10 +2,9 @@
 PORTSRC = ${CHIBIOS}/os/ports/GCC/PPC/chcore.c

 

 PORTASM = ${CHIBIOS}/os/ports/GCC/PPC/SPC56ELxx/bam.s \

-          ${CHIBIOS}/os/ports/GCC/PPC/SPC56ELxx/hwconf.s \

-          ${CHIBIOS}/os/ports/GCC/PPC/SPC56ELxx/ivor.s \

+          ${CHIBIOS}/os/ports/GCC/PPC/SPC56ELxx/core.s \

           ${CHIBIOS}/os/ports/GCC/PPC/SPC56ELxx/vectors.s \

-          ${CHIBIOS}/os/ports/GCC/PPC/isr.s \

+          ${CHIBIOS}/os/ports/GCC/PPC/ivor.s \

           ${CHIBIOS}/os/ports/GCC/PPC/crt0.s

 

 PORTINC = ${CHIBIOS}/os/ports/GCC/PPC \