diff options
| author | pcirillo <pcirillo@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-05-15 13:42:41 +0000 |
|---|---|---|
| committer | pcirillo <pcirillo@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-05-15 13:42:41 +0000 |
| commit | 460ae80f9260fbea7c6b4d94e99a40acfcc018bc (patch) | |
| tree | 80e012e3b46e5973b7dcbdbcb199254258ee68f6 /os | |
| parent | 155b0d13536dabeb0eb2f8928e0d2b55640a17cc (diff) | |
| download | ChibiOS-460ae80f9260fbea7c6b4d94e99a40acfcc018bc.tar.gz ChibiOS-460ae80f9260fbea7c6b4d94e99a40acfcc018bc.tar.bz2 ChibiOS-460ae80f9260fbea7c6b4d94e99a40acfcc018bc.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5738 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
| -rw-r--r-- | os/hal/platforms/SPC563Mxx/spc563m_registry.h | 43 | ||||
| -rw-r--r-- | os/hal/platforms/SPC564Axx/spc564a_registry.h | 59 | ||||
| -rw-r--r-- | os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.c | 907 | ||||
| -rw-r--r-- | os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.h | 443 | ||||
| -rw-r--r-- | os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.c | 951 | ||||
| -rw-r--r-- | os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.h | 457 | ||||
| -rw-r--r-- | os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.c | 117 | ||||
| -rw-r--r-- | os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.h | 114 |
8 files changed, 3091 insertions, 0 deletions
diff --git a/os/hal/platforms/SPC563Mxx/spc563m_registry.h b/os/hal/platforms/SPC563Mxx/spc563m_registry.h index f77635840..bf3cca0d5 100644 --- a/os/hal/platforms/SPC563Mxx/spc563m_registry.h +++ b/os/hal/platforms/SPC563Mxx/spc563m_registry.h @@ -74,6 +74,49 @@ /* SIU attributes.*/
#define SPC5_HAS_SIU TRUE
#define SPC5_SIU_SUPPORTS_PORTS FALSE
+
+/* EMIOS attributes.*/
+#define SPC5_HAS_EMIOS TRUE
+
+#define SPC5_EMIOS_NUM_CHANNELS 16
+
+#define SPC5_EMIOS_FLAG_F0_HANDLER vector51
+#define SPC5_EMIOS_FLAG_F1_HANDLER vector52
+#define SPC5_EMIOS_FLAG_F2_HANDLER vector53
+#define SPC5_EMIOS_FLAG_F3_HANDLER vector54
+#define SPC5_EMIOS_FLAG_F4_HANDLER vector55
+#define SPC5_EMIOS_FLAG_F5_HANDLER vector56
+#define SPC5_EMIOS_FLAG_F6_HANDLER vector57
+#define SPC5_EMIOS_FLAG_F8_HANDLER vector59
+#define SPC5_EMIOS_FLAG_F9_HANDLER vector60
+#define SPC5_EMIOS_FLAG_F10_HANDLER vector61
+#define SPC5_EMIOS_FLAG_F11_HANDLER vector62
+#define SPC5_EMIOS_FLAG_F12_HANDLER vector63
+#define SPC5_EMIOS_FLAG_F13_HANDLER vector64
+#define SPC5_EMIOS_FLAG_F14_HANDLER vector65
+#define SPC5_EMIOS_FLAG_F15_HANDLER vector66
+#define SPC5_EMIOS_FLAG_F23_HANDLER vector209
+#define SPC5_EMIOS_FLAG_F0_NUMBER 51
+#define SPC5_EMIOS_FLAG_F1_NUMBER 52
+#define SPC5_EMIOS_FLAG_F2_NUMBER 53
+#define SPC5_EMIOS_FLAG_F3_NUMBER 54
+#define SPC5_EMIOS_FLAG_F4_NUMBER 55
+#define SPC5_EMIOS_FLAG_F5_NUMBER 56
+#define SPC5_EMIOS_FLAG_F6_NUMBER 57
+#define SPC5_EMIOS_FLAG_F8_NUMBER 59
+#define SPC5_EMIOS_FLAG_F9_NUMBER 60
+#define SPC5_EMIOS_FLAG_F10_NUMBER 61
+#define SPC5_EMIOS_FLAG_F11_NUMBER 62
+#define SPC5_EMIOS_FLAG_F12_NUMBER 63
+#define SPC5_EMIOS_FLAG_F13_NUMBER 64
+#define SPC5_EMIOS_FLAG_F14_NUMBER 65
+#define SPC5_EMIOS_FLAG_F15_NUMBER 66
+#define SPC5_EMIOS_FLAG_F23_NUMBER 209
+
+#define SPC5_EMIOS_CLK (64000000 / \
+ SPC5_EMIOS_GLOBAL_PRESCALER)
+#define SPC5_EMIOS_ENABLE_CLOCK()
+#define SPC5_EMIOS_DISABLE_CLOCK()
/** @} */
#endif /* _SPC563M_REGISTRY_H_ */
diff --git a/os/hal/platforms/SPC564Axx/spc564a_registry.h b/os/hal/platforms/SPC564Axx/spc564a_registry.h index 6d84e6354..6002453c9 100644 --- a/os/hal/platforms/SPC564Axx/spc564a_registry.h +++ b/os/hal/platforms/SPC564Axx/spc564a_registry.h @@ -57,6 +57,65 @@ /* SIU attributes.*/
#define SPC5_HAS_SIU TRUE
#define SPC5_SIU_SUPPORTS_PORTS FALSE
+
+/* EMIOS attributes.*/
+#define SPC5_HAS_EMIOS TRUE
+
+#define SPC5_EMIOS_NUM_CHANNELS 24
+
+#define SPC5_EMIOS_FLAG_F0_HANDLER vector51
+#define SPC5_EMIOS_FLAG_F1_HANDLER vector52
+#define SPC5_EMIOS_FLAG_F2_HANDLER vector53
+#define SPC5_EMIOS_FLAG_F3_HANDLER vector54
+#define SPC5_EMIOS_FLAG_F4_HANDLER vector55
+#define SPC5_EMIOS_FLAG_F5_HANDLER vector56
+#define SPC5_EMIOS_FLAG_F6_HANDLER vector57
+#define SPC5_EMIOS_FLAG_F7_HANDLER vector58
+#define SPC5_EMIOS_FLAG_F8_HANDLER vector59
+#define SPC5_EMIOS_FLAG_F9_HANDLER vector60
+#define SPC5_EMIOS_FLAG_F10_HANDLER vector61
+#define SPC5_EMIOS_FLAG_F11_HANDLER vector62
+#define SPC5_EMIOS_FLAG_F12_HANDLER vector63
+#define SPC5_EMIOS_FLAG_F13_HANDLER vector64
+#define SPC5_EMIOS_FLAG_F14_HANDLER vector65
+#define SPC5_EMIOS_FLAG_F15_HANDLER vector66
+#define SPC5_EMIOS_FLAG_F16_HANDLER vector202
+#define SPC5_EMIOS_FLAG_F17_HANDLER vector203
+#define SPC5_EMIOS_FLAG_F18_HANDLER vector204
+#define SPC5_EMIOS_FLAG_F19_HANDLER vector205
+#define SPC5_EMIOS_FLAG_F20_HANDLER vector206
+#define SPC5_EMIOS_FLAG_F21_HANDLER vector207
+#define SPC5_EMIOS_FLAG_F22_HANDLER vector208
+#define SPC5_EMIOS_FLAG_F23_HANDLER vector209
+#define SPC5_EMIOS_FLAG_F0_NUMBER 51
+#define SPC5_EMIOS_FLAG_F1_NUMBER 52
+#define SPC5_EMIOS_FLAG_F2_NUMBER 53
+#define SPC5_EMIOS_FLAG_F3_NUMBER 54
+#define SPC5_EMIOS_FLAG_F4_NUMBER 55
+#define SPC5_EMIOS_FLAG_F5_NUMBER 56
+#define SPC5_EMIOS_FLAG_F6_NUMBER 57
+#define SPC5_EMIOS_FLAG_F7_NUMBER 58
+#define SPC5_EMIOS_FLAG_F8_NUMBER 59
+#define SPC5_EMIOS_FLAG_F9_NUMBER 60
+#define SPC5_EMIOS_FLAG_F10_NUMBER 61
+#define SPC5_EMIOS_FLAG_F11_NUMBER 62
+#define SPC5_EMIOS_FLAG_F12_NUMBER 63
+#define SPC5_EMIOS_FLAG_F13_NUMBER 64
+#define SPC5_EMIOS_FLAG_F14_NUMBER 65
+#define SPC5_EMIOS_FLAG_F15_NUMBER 66
+#define SPC5_EMIOS_FLAG_F16_NUMBER 202
+#define SPC5_EMIOS_FLAG_F17_NUMBER 203
+#define SPC5_EMIOS_FLAG_F18_NUMBER 204
+#define SPC5_EMIOS_FLAG_F19_NUMBER 205
+#define SPC5_EMIOS_FLAG_F20_NUMBER 206
+#define SPC5_EMIOS_FLAG_F21_NUMBER 207
+#define SPC5_EMIOS_FLAG_F22_NUMBER 208
+#define SPC5_EMIOS_FLAG_F23_NUMBER 209
+
+#define SPC5_EMIOS_CLK (64000000 / \
+ SPC5_EMIOS_GLOBAL_PRESCALER)
+#define SPC5_EMIOS_ENABLE_CLOCK()
+#define SPC5_EMIOS_DISABLE_CLOCK()
/** @} */
#endif /* _SPC563M_REGISTRY_H_ */
diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.c b/os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.c new file mode 100644 index 000000000..b4b9fce01 --- /dev/null +++ b/os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.c @@ -0,0 +1,907 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC5xx/eMIOS200_v1/icu_lld.c
+ * @brief SPC5xx low level icu driver code.
+ *
+ * @addtogroup ICU
+ * @{
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_ICU || defined(__DOXYGEN__)
+
+#include "spc5_emios.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief ICUD1 driver identifier.
+ * @note The driver ICUD1 allocates the unified channel eMIOS_CH0
+ * when enabled.
+ */
+#if SPC5_ICU_USE_EMIOS_CH0 || defined(__DOXYGEN__)
+ICUDriver ICUD1;
+#endif
+
+/**
+ * @brief ICUD2 driver identifier.
+ * @note The driver ICUD2 allocates the unified channel eMIOS_CH1
+ * when enabled.
+ */
+#if SPC5_ICU_USE_EMIOS_CH1 || defined(__DOXYGEN__)
+ICUDriver ICUD2;
+#endif
+
+/**
+ * @brief ICUD3 driver identifier.
+ * @note The driver ICUD3 allocates the unified channel eMIOS_CH2
+ * when enabled.
+ */
+#if SPC5_ICU_USE_EMIOS_CH2 || defined(__DOXYGEN__)
+ICUDriver ICUD3;
+#endif
+ +
+/**
+ * @brief ICUD4 driver identifier.
+ * @note The driver ICUD4 allocates the unified channel eMIOS_CH3
+ * when enabled.
+ */
+#if SPC5_ICU_USE_EMIOS_CH3 || defined(__DOXYGEN__)
+ICUDriver ICUD4;
+#endif
+
+/**
+ * @brief ICUD5 driver identifier.
+ * @note The driver ICUD5 allocates the unified channel eMIOS_CH4
+ * when enabled.
+ */
+#if SPC5_ICU_USE_EMIOS_CH4 || defined(__DOXYGEN__)
+ICUDriver ICUD5;
+#endif
+
+/**
+ * @brief ICUD6 driver identifier.
+ * @note The driver ICUD6 allocates the unified channel eMIOS_CH5
+ * when enabled.
+ */
+#if SPC5_ICU_USE_EMIOS_CH5 || defined(__DOXYGEN__)
+ICUDriver ICUD6;
+#endif
+
+/**
+ * @brief ICUD7 driver identifier.
+ * @note The driver ICUD7 allocates the unified channel eMIOS_CH6
+ * when enabled.
+ */
+#if SPC5_ICU_USE_EMIOS_CH6 || defined(__DOXYGEN__)
+ICUDriver ICUD7;
+#endif
+
+/**
+ * @brief ICUD8 driver identifier.
+ * @note The driver ICUD8 allocates the unified channel eMIOS_CH8
+ * when enabled.
+ */
+#if SPC5_ICU_USE_EMIOS_CH8 || defined(__DOXYGEN__)
+ICUDriver ICUD8;
+#endif
+
+/**
+ * @brief ICUD9 driver identifier.
+ * @note The driver ICUD9 allocates the unified channel eMIOS_CH7
+ * when enabled.
+ */
+#if SPC5_ICU_USE_EMIOS_CH7 || defined(__DOXYGEN__)
+ICUDriver ICUD9;
+#endif
+
+/**
+ * @brief ICUD10 driver identifier.
+ * @note The driver ICUD10 allocates the unified channel eMIOS_CH16
+ * when enabled.
+ */
+#if SPC5_ICU_USE_EMIOS_CH16 || defined(__DOXYGEN__)
+ICUDriver ICUD10;
+#endif
+
+/**
+ * @brief ICUD11 driver identifier.
+ * @note The driver ICUD11 allocates the unified channel eMIOS_CH17
+ * when enabled.
+ */
+#if SPC5_ICU_USE_EMIOS_CH17 || defined(__DOXYGEN__)
+ICUDriver ICUD11;
+#endif
+
+/**
+ * @brief ICUD12 driver identifier.
+ * @note The driver ICUD12 allocates the unified channel eMIOS_CH18
+ * when enabled.
+ */
+#if SPC5_ICU_USE_EMIOS_CH18 || defined(__DOXYGEN__)
+ICUDriver ICUD12;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Width and Period registers.
+ */
+uint32_t width;
+uint32_t period;
+
+/**
+ * @brief A2 temp registers.
+ */
+uint32_t A2_1, A2_2, A2_3;
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief ICU IRQ handler.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ */
+static void icu_lld_serve_interrupt(ICUDriver *icup) {
+
+ uint32_t sr = icup->emiosp->CH[icup->ch_number].CSR.R;
+
+ if(sr && EMIOSS_OVFL && icup->config->overflow_cb != NULL){
+ icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_OVFLC;
+ _icu_isr_invoke_overflow_cb(icup);
+ }
+ if (sr && EMIOSS_FLAG){
+ icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_FLAGC;
+ if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH) {
+ if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 1U && \
+ icup->config->period_cb != NULL) {
+ A2_3 = icup->emiosp->CH[icup->ch_number].CADR.R;
+ period = A2_3 - A2_1;
+ _icu_isr_invoke_period_cb(icup);
+ A2_1 = A2_3;
+ } else if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 0 && \
+ icup->config->width_cb != NULL) {
+ A2_2 = icup->emiosp->CH[icup->ch_number].CADR.R;
+ width = A2_2 - A2_1;
+ _icu_isr_invoke_width_cb(icup);
+ }
+ } else if (icup->config->mode == ICU_INPUT_ACTIVE_LOW) {
+ if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 1U && \
+ icup->config->width_cb != NULL) {
+ A2_2 = icup->emiosp->CH[icup->ch_number].CADR.R;
+ width = A2_2 - A2_1;
+ _icu_isr_invoke_width_cb(icup);
+ } else if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 0 && \
+ icup->config->period_cb != NULL) {
+ A2_3 = icup->emiosp->CH[icup->ch_number].CADR.R;
+ period = A2_3 - A2_1;
+ _icu_isr_invoke_period_cb(icup);
+ A2_1 = A2_3;
+ }
+ }
+ }
+ if(sr && EMIOSS_OVR){
+ icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_OVRC;
+ }
+
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if SPC5_ICU_USE_EMIOS_CH0
+#if !defined(SPC5_EMIOS_FLAG_F0_HANDLER)
+#error "SPC5_EMIOS_FLAG_F0_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS Channel 0 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F0_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ icu_lld_serve_interrupt(&ICUD1);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_ICU_USE_EMIOS_CH0 */
+
+#if SPC5_ICU_USE_EMIOS_CH1
+#if !defined(SPC5_EMIOS_FLAG_F1_HANDLER)
+#error "SPC5_EMIOS_FLAG_F1_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS Channel 1 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F1_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ icu_lld_serve_interrupt(&ICUD2);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_ICU_USE_EMIOS_CH1 */
+
+#if SPC5_ICU_USE_EMIOS_CH2
+#if !defined(SPC5_EMIOS_FLAG_F2_HANDLER)
+#error "SPC5_EMIOS_FLAG_F2_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS Channel 2 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F2_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ icu_lld_serve_interrupt(&ICUD3);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_ICU_USE_EMIOS_CH2 */
+
+#if SPC5_ICU_USE_EMIOS_CH3
+#if !defined(SPC5_EMIOS_FLAG_F3_HANDLER)
+#error "SPC5_EMIOS_FLAG_F3_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS Channel 3 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F3_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ icu_lld_serve_interrupt(&ICUD4);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_ICU_USE_EMIOS_CH3 */
+
+#if SPC5_ICU_USE_EMIOS_CH4
+#if !defined(SPC5_EMIOS_FLAG_F4_HANDLER)
+#error "SPC5_EMIOS_FLAG_F4_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS Channel 4 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F4_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ icu_lld_serve_interrupt(&ICUD5);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_ICU_USE_EMIOS_CH4 */
+
+#if SPC5_ICU_USE_EMIOS_CH5
+#if !defined(SPC5_EMIOS_FLAG_F5_HANDLER)
+#error "SPC5_EMIOS_FLAG_F5_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS Channel 5 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F5_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ icu_lld_serve_interrupt(&ICUD6);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_ICU_USE_EMIOS_CH5 */
+
+#if SPC5_ICU_USE_EMIOS_CH6
+#if !defined(SPC5_EMIOS_FLAG_F6_HANDLER)
+#error "SPC5_EMIOS_FLAG_F6_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS Channel 6 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F6_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ icu_lld_serve_interrupt(&ICUD7);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_ICU_USE_EMIOS_CH6 */
+
+#if SPC5_ICU_USE_EMIOS_CH7
+#if !defined(SPC5_EMIOS_FLAG_F7_HANDLER)
+#error "SPC5_EMIOS_FLAG_F7_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS Channel 7 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F7_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ icu_lld_serve_interrupt(&ICUD9);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_ICU_USE_EMIOS_CH7 */
+
+#if SPC5_ICU_USE_EMIOS_CH7
+#if !defined(SPC5_EMIOS_FLAG_F7_HANDLER)
+#error "SPC5_EMIOS_FLAG_F7_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS Channel 8 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F8_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ icu_lld_serve_interrupt(&ICUD8);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_ICU_USE_EMIOS_CH8 */
+
+#if SPC5_ICU_USE_EMIOS_CH16
+#if !defined(SPC5_EMIOS_FLAG_F16_HANDLER)
+#error "SPC5_EMIOS_FLAG_F16_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS Channel 16 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F16_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ icu_lld_serve_interrupt(&ICUD10);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_ICU_USE_EMIOS_CH16 */
+
+#if SPC5_ICU_USE_EMIOS_CH17
+#if !defined(SPC5_EMIOS_FLAG_F17_HANDLER)
+#error "SPC5_EMIOS_FLAG_F17_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS Channel 17 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F17_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ icu_lld_serve_interrupt(&ICUD11);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_ICU_USE_EMIOS_CH17 */
+
+#if SPC5_ICU_USE_EMIOS_CH18
+#if !defined(SPC5_EMIOS_FLAG_F18_HANDLER)
+#error "SPC5_EMIOS_FLAG_F18_HANDLER not defined"
+#endif
+/**
+ * @brief eMIOS Channel 18 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F18_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ icu_lld_serve_interrupt(&ICUD12);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_ICU_USE_EMIOS_CH18 */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level ICU driver initialization.
+ *
+ * @notapi
+ */
+void icu_lld_init(void) {
+
+ /* Initialize A2 temp registers.*/
+ A2_1 = 0U;
+ A2_2 = 0U;
+ A2_3 = 0U;
+
+ /* eMIOSx channels initially all not in use.*/
+ reset_emios_active_channels();
+
+#if SPC5_ICU_USE_EMIOS_CH0
+ /* Driver initialization.*/
+ icuObjectInit(&ICUD1);
+ ICUD1.emiosp = &EMIOS;
+ ICUD1.ch_number = 0U;
+ ICUD1.clock = SPC5_EMIOS_CLK;
+#endif /* SPC5_ICU_USE_EMIOS_CH0 */
+
+#if SPC5_ICU_USE_EMIOS_CH1
+ /* Driver initialization.*/
+ icuObjectInit(&ICUD2);
+ ICUD2.emiosp = &EMIOS;
+ ICUD2.ch_number = 1U;
+ ICUD2.clock = SPC5_EMIOS_CLK;
+#endif /* SPC5_ICU_USE_EMIOS_CH1 */
+
+#if SPC5_ICU_USE_EMIOS_CH2
+ /* Driver initialization.*/
+ icuObjectInit(&ICUD3);
+ ICUD3.emiosp = &EMIOS;
+ ICUD3.ch_number = 2U;
+ ICUD3.clock = SPC5_EMIOS_CLK;
+#endif /* SPC5_ICU_USE_EMIOS_CH2 */
+
+#if SPC5_ICU_USE_EMIOS_CH3
+ /* Driver initialization.*/
+ icuObjectInit(&ICUD4);
+ ICUD4.emiosp = &EMIOS;
+ ICUD4.ch_number = 3U;
+ ICUD4.clock = SPC5_EMIOS_CLK;
+#endif /* SPC5_ICU_USE_EMIOS_CH3 */
+
+#if SPC5_ICU_USE_EMIOS_CH4
+ /* Driver initialization.*/
+ icuObjectInit(&ICUD5);
+ ICUD5.emiosp = &EMIOS;
+ ICUD5.ch_number = 4U;
+ ICUD5.clock = SPC5_EMIOS_CLK;
+#endif /* SPC5_ICU_USE_EMIOS_CH4 */
+
+#if SPC5_ICU_USE_EMIOS_CH5
+ /* Driver initialization.*/
+ icuObjectInit(&ICUD6);
+ ICUD6.emiosp = &EMIOS;
+ ICUD6.ch_number = 5U;
+ ICUD6.clock = SPC5_EMIOS_CLK;
+#endif /* SPC5_ICU_USE_EMIOS_CH5 */
+
+#if SPC5_ICU_USE_EMIOS_CH6
+ /* Driver initialization.*/
+ icuObjectInit(&ICUD7);
+ ICUD7.emiosp = &EMIOS;
+ ICUD7.ch_number = 6U;
+ ICUD7.clock = SPC5_EMIOS_CLK;
+#endif /* SPC5_ICU_USE_EMIOS_CH6 */
+
+#if SPC5_ICU_USE_EMIOS_CH8
+ /* Driver initialization.*/
+ icuObjectInit(&ICUD8);
+ ICUD8.emiosp = &EMIOS;
+ ICUD8.ch_number = 8U;
+ ICUD8.clock = SPC5_EMIOS_CLK;
+#endif /* SPC5_ICU_USE_EMIOS_CH8 */
+
+#if SPC5_ICU_USE_EMIOS_CH7
+ /* Driver initialization.*/
+ icuObjectInit(&ICUD9);
+ ICUD9.emiosp = &EMIOS;
+ ICUD9.ch_number = 7U;
+ ICUD9.clock = SPC5_EMIOS_CLK;
+#endif /* SPC5_ICU_USE_EMIOS_CH7 */
+
+#if SPC5_ICU_USE_EMIOS_CH16
+ /* Driver initialization.*/
+ icuObjectInit(&ICUD10);
+ ICUD10.emiosp = &EMIOS;
+ ICUD10.ch_number = 16U;
+ ICUD10.clock = SPC5_EMIOS_CLK;
+#endif /* SPC5_ICU_USE_EMIOS_CH16 */
+
+#if SPC5_ICU_USE_EMIOS_CH17
+ /* Driver initialization.*/
+ icuObjectInit(&ICUD11);
+ ICUD11.emiosp = &EMIOS;
+ ICUD11.ch_number = 17U;
+ ICUD11.clock = SPC5_EMIOS_CLK;
+#endif /* SPC5_ICU_USE_EMIOS_CH17 */
+
+#if SPC5_ICU_USE_EMIOS_CH18
+ /* Driver initialization.*/
+ icuObjectInit(&ICUD12);
+ ICUD12.emiosp = &EMIOS;
+ ICUD12.ch_number = 18U;
+ ICUD12.clock = SPC5_EMIOS_CLK;
+#endif /* SPC5_ICU_USE_EMIOS_CH18 */
+
+#if SPC5_ICU_USE_EMIOS
+
+#if SPC5_EMIOS_NUM_CHANNELS == 16
+ INTC.PSR[SPC5_EMIOS_FLAG_F0_NUMBER].R = SPC5_EMIOS_FLAG_F0_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F1_NUMBER].R = SPC5_EMIOS_FLAG_F1_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F2_NUMBER].R = SPC5_EMIOS_FLAG_F2_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F3_NUMBER].R = SPC5_EMIOS_FLAG_F3_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F4_NUMBER].R = SPC5_EMIOS_FLAG_F4_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F5_NUMBER].R = SPC5_EMIOS_FLAG_F5_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F6_NUMBER].R = SPC5_EMIOS_FLAG_F6_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F8_NUMBER].R = SPC5_EMIOS_FLAG_F8_PRIORITY;
+#endif
+
+#if SPC5_EMIOS_NUM_CHANNELS == 24
+ INTC.PSR[SPC5_EMIOS_FLAG_F0_NUMBER].R = SPC5_EMIOS_FLAG_F0_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F1_NUMBER].R = SPC5_EMIOS_FLAG_F1_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F2_NUMBER].R = SPC5_EMIOS_FLAG_F2_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F3_NUMBER].R = SPC5_EMIOS_FLAG_F3_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F4_NUMBER].R = SPC5_EMIOS_FLAG_F4_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F5_NUMBER].R = SPC5_EMIOS_FLAG_F5_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F6_NUMBER].R = SPC5_EMIOS_FLAG_F6_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F7_NUMBER].R = SPC5_EMIOS_FLAG_F7_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F8_NUMBER].R = SPC5_EMIOS_FLAG_F8_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F16_NUMBER].R = SPC5_EMIOS_FLAG_F16_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F17_NUMBER].R = SPC5_EMIOS_FLAG_F17_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F18_NUMBER].R = SPC5_EMIOS_FLAG_F18_PRIORITY;
+#endif
+
+#endif
+}
+
+/**
+ * @brief Configures and activates the ICU peripheral.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ *
+ * @notapi
+ */
+void icu_lld_start(ICUDriver *icup) {
+
+ chDbgAssert(get_emios_active_channels() < SPC5_EMIOS_NUM_CHANNELS,
+ "icu_lld_start(), #1", "too many channels");
+
+ if (icup->state == ICU_STOP) {
+ /* Enables the peripheral.*/
+#if SPC5_ICU_USE_EMIOS_CH0
+ if (&ICUD1 == icup)
+ increase_emios_active_channels();
+#endif /* SPC5_ICU_USE_EMIOS_CH0 */
+#if SPC5_ICU_USE_EMIOS_CH1
+ if (&ICUD2 == icup)
+ increase_emios_active_channels();
+#endif /* SPC5_ICU_USE_EMIOS_CH1 */
+#if SPC5_ICU_USE_EMIOS_CH2
+ if (&ICUD3 == icup)
+ increase_emios_active_channels();
+#endif /* SPC5_ICU_USE_EMIOS_CH2 */
+#if SPC5_ICU_USE_EMIOS_CH3
+ if (&ICUD4 == icup)
+ increase_emios_active_channels();
+#endif /* SPC5_ICU_USE_EMIOS_CH3 */
+#if SPC5_ICU_USE_EMIOS_CH4
+ if (&ICUD5 == icup)
+ increase_emios_active_channels();
+#endif /* SPC5_ICU_USE_EMIOS_CH4 */
+#if SPC5_ICU_USE_EMIOS_CH5
+ if (&ICUD6 == icup)
+ increase_emios_active_channels();
+#endif /* SPC5_ICU_USE_EMIOS_CH5 */
+#if SPC5_ICU_USE_EMIOS_CH6
+ if (&ICUD7 == icup)
+ increase_emios_active_channels();
+#endif /* SPC5_ICU_USE_EMIOS_CH6 */
+#if SPC5_ICU_USE_EMIOS_CH8
+ if (&ICUD8 == icup)
+ increase_emios_active_channels();
+#endif /* SPC5_ICU_USE_EMIOS_CH8 */
+#if SPC5_ICU_USE_EMIOS_CH7
+ if (&ICUD9 == icup)
+ increase_emios_active_channels();
+#endif /* SPC5_ICU_USE_EMIOS_CH7 */
+#if SPC5_ICU_USE_EMIOS_CH16
+ if (&ICUD10 == icup)
+ increase_emios_active_channels();
+#endif /* SPC5_ICU_USE_EMIOS_CH16 */
+#if SPC5_ICU_USE_EMIOS_CH17
+ if (&ICUD11 == icup)
+ increase_emios_active_channels();
+#endif /* SPC5_ICU_USE_EMIOS_CH17 */
+#if SPC5_ICU_USE_EMIOS_CH18
+ if (&ICUD12 == icup)
+ increase_emios_active_channels();
+#endif /* SPC5_ICU_USE_EMIOS_CH18 */
+
+ /* Set eMIOS Clock.*/
+#if SPC5_ICU_USE_EMIOS
+ active_emios_clock(icup, NULL);
+#endif
+
+ }
+ /* Configures the peripheral.*/
+
+ /* Channel enables.*/
+ icup->emiosp->UCDIS.R &= ~(1 << icup->ch_number);
+
+ /* Clear pending IRQs (if any).*/
+ icup->emiosp->CH[icup->ch_number].CSR.R = EMIOSS_OVRC |
+ EMIOSS_OVFLC | EMIOSS_FLAGC;
+
+ /* Set clock prescaler and control register.*/
+ uint32_t psc = (icup->clock / icup->config->frequency);
+ chDbgAssert((psc <= 4) &&
+ ((psc * icup->config->frequency) == icup->clock) &&
+ ((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)),
+ "icu_lld_start(), #1", "invalid frequency");
+
+ icup->emiosp->CH[icup->ch_number].CCR.B.UCPREN = 0;
+ icup->emiosp->CH[icup->ch_number].CCR.R |=
+ EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER) |
+ EMIOSC_EDSEL | EMIOS_CCR_MODE_SAIC;
+ icup->emiosp->CH[icup->ch_number].CCR.B.UCPRE = psc - 1;
+ icup->emiosp->CH[icup->ch_number].CCR.R |= EMIOSC_UCPREN;
+
+ /* Set source polarity.*/
+ if(icup->config->mode == ICU_INPUT_ACTIVE_HIGH){
+ icup->emiosp->CH[icup->ch_number].CCR.R |= EMIOSC_EDPOL;
+ } else {
+ icup->emiosp->CH[icup->ch_number].CCR.R &= ~EMIOSC_EDPOL;
+ }
+
+ /* Direct pointers to the period and width registers in order to make
+ reading data faster from within callbacks.*/
+ icup->pccrp = .
+ icup->wccrp = &width;
+
+ /* Channel disables.*/
+ icup->emiosp->UCDIS.R |= (1 << icup->ch_number);
+
+}
+
+/**
+ * @brief Deactivates the ICU peripheral.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ *
+ * @notapi
+ */
+void icu_lld_stop(ICUDriver *icup) {
+
+ chDbgAssert(get_emios_active_channels() < SPC5_EMIOS_NUM_CHANNELS,
+ "icu_lld_stop(), #1", "too many channels");
+
+ if (icup->state == ICU_READY) {
+
+ /* Disables the peripheral.*/
+#if SPC5_ICU_USE_EMIOS_CH0
+ if (&ICUD1 == icup) {
+ /* Reset UC Control Register.*/
+ icup->emiosp->CH[icup->ch_number].CCR.R = 0;
+
+ decrease_emios_active_channels();
+ }
+#endif /* SPC5_ICU_USE_EMIOS_CH0 */
+#if SPC5_ICU_USE_EMIOS_CH1
+ if (&ICUD2 == icup) {
+ /* Reset UC Control Register.*/
+ icup->emiosp->CH[icup->ch_number].CCR.R = 0;
+
+ decrease_emios_active_channels();
+ }
+#endif /* SPC5_ICU_USE_EMIOS_CH1 */
+#if SPC5_ICU_USE_EMIOS_CH2
+ if (&ICUD3 == icup) {
+ /* Reset UC Control Register.*/
+ icup->emiosp->CH[icup->ch_number].CCR.R = 0;
+
+ decrease_emios_active_channels();
+ }
+#endif /* SPC5_ICU_USE_EMIOS_CH2 */
+#if SPC5_ICU_USE_EMIOS_CH3
+ if (&ICUD4 == icup) {
+ /* Reset UC Control Register.*/
+ icup->emiosp->CH[icup->ch_number].CCR.R = 0;
+
+ decrease_emios_active_channels();
+ }
+#endif /* SPC5_ICU_USE_EMIOS_CH3 */
+#if SPC5_ICU_USE_EMIOS_CH4
+ if (&ICUD5 == icup) {
+ /* Reset UC Control Register.*/
+ icup->emiosp->CH[icup->ch_number].CCR.R = 0;
+
+ decrease_emios_active_channels();
+ }
+#endif /* SPC5_ICU_USE_EMIOS_CH4 */
+#if SPC5_ICU_USE_EMIOS_CH5
+ if (&ICUD6 == icup) {
+ /* Reset UC Control Register.*/
+ icup->emiosp->CH[icup->ch_number].CCR.R = 0;
+
+ decrease_emios_active_channels();
+ }
+#endif /* SPC5_ICU_USE_EMIOS_CH5 */
+#if SPC5_ICU_USE_EMIOS_CH6
+ if (&ICUD7 == icup) {
+ /* Reset UC Control Register.*/
+ icup->emiosp->CH[icup->ch_number].CCR.R = 0;
+
+ decrease_emios_active_channels();
+ }
+#endif /* SPC5_ICU_USE_EMIOS_CH6 */
+#if SPC5_ICU_USE_EMIOS_CH8
+ if (&ICUD8 == icup) {
+ /* Reset UC Control Register.*/
+ icup->emiosp->CH[icup->ch_number].CCR.R = 0;
+
+ decrease_emios_active_channels();
+ }
+#endif /* SPC5_ICU_USE_EMIOS_CH8 */
+#if SPC5_ICU_USE_EMIOS_CH7
+ if (&ICUD9 == icup) {
+ /* Reset UC Control Register.*/
+ icup->emiosp->CH[icup->ch_number].CCR.R = 0;
+
+ decrease_emios_active_channels();
+ }
+#endif /* SPC5_ICU_USE_EMIOS_CH7 */
+#if SPC5_ICU_USE_EMIOS_CH16
+ if (&ICUD10 == icup) {
+ /* Reset UC Control Register.*/
+ icup->emiosp->CH[icup->ch_number].CCR.R = 0;
+
+ decrease_emios_active_channels();
+ }
+#endif /* SPC5_ICU_USE_EMIOS_CH16 */
+#if SPC5_ICU_USE_EMIOS_CH17
+ if (&ICUD11 == icup) {
+ /* Reset UC Control Register.*/
+ icup->emiosp->CH[icup->ch_number].CCR.R = 0;
+
+ decrease_emios_active_channels();
+ }
+#endif /* SPC5_ICU_USE_EMIOS_CH17 */
+#if SPC5_ICU_USE_EMIOS_CH18
+ if (&ICUD12 == icup) {
+ /* Reset UC Control Register.*/
+ icup->emiosp->CH[icup->ch_number].CCR.R = 0;
+
+ decrease_emios_active_channels();
+ }
+#endif /* SPC5_ICU_USE_EMIOS_CH18 */
+
+ /* eMIOS clock deactivation.*/
+#if SPC5_ICU_USE_EMIOS
+ deactive_emios_clock();
+#endif
+
+ }
+}
+
+/**
+ * @brief Enables the input capture.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ *
+ * @notapi
+ */
+void icu_lld_enable(ICUDriver *icup) {
+
+ /* Clear pending IRQs (if any).*/
+ icup->emiosp->CH[icup->ch_number].CSR.R = EMIOSS_OVRC |
+ EMIOSS_OVFLC | EMIOSS_FLAGC;
+
+ /* Active interrupts.*/
+ if (icup->config->period_cb != NULL || icup->config->width_cb != NULL || \
+ icup->config->overflow_cb != NULL) {
+ icup->emiosp->CH[icup->ch_number].CCR.B.FEN = 1U;
+ }
+
+ /* Channel enables.*/
+ icup->emiosp->UCDIS.R &= ~(1 << icup->ch_number);
+
+}
+
+/**
+ * @brief Disables the input capture.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ *
+ * @notapi
+ */
+void icu_lld_disable(ICUDriver *icup) {
+
+ /* Clear pending IRQs (if any).*/
+ icup->emiosp->CH[icup->ch_number].CSR.R = EMIOSS_OVRC |
+ EMIOSS_OVFLC | EMIOSS_FLAGC;
+
+ /* Disable interrupts.*/
+ icup->emiosp->CH[icup->ch_number].CCR.B.FEN = 0;
+
+ /* Channel disables.*/
+ icup->emiosp->UCDIS.R |= (1 << icup->ch_number);
+
+}
+
+#endif /* HAL_USE_ICU */
+
+/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.h b/os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.h new file mode 100644 index 000000000..bc750d5f2 --- /dev/null +++ b/os/hal/platforms/SPC5xx/eMIOS200_v1/icu_lld.h @@ -0,0 +1,443 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC5xx/eMIOS200_v1/icu_lld.h
+ * @brief SPC5xx low level icu driver header.
+ *
+ * @addtogroup ICU
+ * @{
+ */
+
+#ifndef _ICU_LLD_H_
+#define _ICU_LLD_H_
+
+#if HAL_USE_ICU || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief ICUD1 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD1 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_ICU_USE_EMIOS_CH0) || defined(__DOXYGEN__)
+#define SPC5_ICU_USE_EMIOS_CH0 FALSE
+#endif
+
+/**
+ * @brief ICUD2 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD2 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_ICU_USE_EMIOS_CH1) || defined(__DOXYGEN__)
+#define SPC5_ICU_USE_EMIOS_CH1 FALSE
+#endif
+
+/**
+ * @brief ICUD3 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD3 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_ICU_USE_EMIOS_CH2) || defined(__DOXYGEN__)
+#define SPC5_ICU_USE_EMIOS_CH2 FALSE
+#endif
+
+/**
+ * @brief ICUD4 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD4 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_ICU_USE_EMIOS_CH3) || defined(__DOXYGEN__)
+#define SPC5_ICU_USE_EMIOS_CH3 FALSE
+#endif
+
+/**
+ * @brief ICUD5 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD5 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_ICU_USE_EMIOS_CH4) || defined(__DOXYGEN__)
+#define SPC5_ICU_USE_EMIOS_CH4 FALSE
+#endif
+
+/**
+ * @brief ICUD6 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD6 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_ICU_USE_EMIOS_CH5) || defined(__DOXYGEN__)
+#define SPC5_ICU_USE_EMIOS_CH5 FALSE
+#endif
+
+/**
+ * @brief ICUD7 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD7 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_ICU_USE_EMIOS_CH6) || defined(__DOXYGEN__)
+#define SPC5_ICU_USE_EMIOS_CH6 FALSE
+#endif
+
+/**
+ * @brief ICUD8 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD8 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_ICU_USE_EMIOS_CH8) || defined(__DOXYGEN__)
+#define SPC5_ICU_USE_EMIOS_CH8 FALSE
+#endif
+
+/**
+ * @brief ICUD9 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD9 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_ICU_USE_EMIOS_CH7) || defined(__DOXYGEN__)
+#define SPC5_ICU_USE_EMIOS_CH7 FALSE
+#endif
+
+/**
+ * @brief ICUD10 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD10 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_ICU_USE_EMIOS_CH16) || defined(__DOXYGEN__)
+#define SPC5_ICU_USE_EMIOS_CH16 FALSE
+#endif
+
+/**
+ * @brief ICUD11 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD11 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_ICU_USE_EMIOS_CH17) || defined(__DOXYGEN__)
+#define SPC5_ICU_USE_EMIOS_CH17 FALSE
+#endif
+
+/**
+ * @brief ICUD12 driver enable switch.
+ * @details If set to @p TRUE the support for ICUD12 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_ICU_USE_EMIOS_CH18) || defined(__DOXYGEN__)
+#define SPC5_ICU_USE_EMIOS_CH18 FALSE
+#endif
+
+/**
+ * @brief ICUD1 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS_FLAG_F0_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS_FLAG_F0_PRIORITY 7
+#endif
+
+/**
+ * @brief ICUD2 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS_FLAG_F1_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS_FLAG_F1_PRIORITY 7
+#endif
+
+/**
+ * @brief ICUD3 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS_FLAG_F2_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS_FLAG_F2_PRIORITY 7
+#endif
+
+/**
+ * @brief ICUD4 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS_FLAG_F3_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS_FLAG_F3_PRIORITY 7
+#endif
+
+/**
+ * @brief ICUD5 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS_FLAG_F4_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS_FLAG_F4_PRIORITY 7
+#endif
+
+/**
+ * @brief ICUD6 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS_FLAG_F5_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS_FLAG_F5_PRIORITY 7
+#endif
+
+/**
+ * @brief ICUD7 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS_FLAG_F6_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS_FLAG_F6_PRIORITY 7
+#endif
+
+/**
+ * @brief ICUD8 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS_FLAG_F8_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS_FLAG_F8_PRIORITY 7
+#endif
+
+/**
+ * @brief ICUD9 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS_FLAG_F7_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS_FLAG_F7_PRIORITY 7
+#endif
+
+/**
+ * @brief ICUD10 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS_FLAG_F16_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS_FLAG_F16_PRIORITY 7
+#endif
+
+/**
+ * @brief ICUD11 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS_FLAG_F17_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS_FLAG_F17_PRIORITY 7
+#endif
+
+/**
+ * @brief ICUD12 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS_FLAG_F18_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS_FLAG_F18_PRIORITY 7
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if !SPC5_HAS_EMIOS
+#error "EMIOS not present in the selected device"
+#endif
+
+#define SPC5_ICU_USE_EMIOS (SPC5_ICU_USE_EMIOS_CH0 || \
+ SPC5_ICU_USE_EMIOS_CH1 || \
+ SPC5_ICU_USE_EMIOS_CH2 || \
+ SPC5_ICU_USE_EMIOS_CH3 || \
+ SPC5_ICU_USE_EMIOS_CH4 || \
+ SPC5_ICU_USE_EMIOS_CH5 || \
+ SPC5_ICU_USE_EMIOS_CH6 || \
+ SPC5_ICU_USE_EMIOS_CH7 || \
+ SPC5_ICU_USE_EMIOS_CH8 || \
+ SPC5_ICU_USE_EMIOS_CH16 || \
+ SPC5_ICU_USE_EMIOS_CH17 || \
+ SPC5_ICU_USE_EMIOS_CH18)
+
+#if !SPC5_ICU_USE_EMIOS
+#error "ICU driver activated but no Channels assigned"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief ICU driver mode.
+ */
+typedef enum {
+ ICU_INPUT_ACTIVE_HIGH = 0, /**< Trigger on rising edge. */
+ ICU_INPUT_ACTIVE_LOW = 1, /**< Trigger on falling edge. */
+} icumode_t;
+
+/**
+ * @brief ICU frequency type.
+ */
+typedef uint32_t icufreq_t;
+
+/**
+ * @brief ICU counter type.
+ */
+typedef uint32_t icucnt_t;
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+ /**
+ * @brief Driver mode.
+ */
+ icumode_t mode;
+ /**
+ * @brief Timer clock in Hz.
+ * @note The low level can use assertions in order to catch invalid
+ * frequency specifications.
+ */
+ icufreq_t frequency;
+ /**
+ * @brief Callback for pulse width measurement.
+ */
+ icucallback_t width_cb;
+ /**
+ * @brief Callback for cycle period measurement.
+ */
+ icucallback_t period_cb;
+ /**
+ * @brief Callback for timer overflow.
+ */
+ icucallback_t overflow_cb;
+ /* End of the mandatory fields.*/
+} ICUConfig;
+
+/**
+ * @brief Structure representing an ICU driver.
+ */
+struct ICUDriver {
+ /**
+ * @brief Driver state.
+ */
+ icustate_t state;
+ /**
+ * @brief eMIOSx channel number.
+ */
+ uint32_t ch_number;
+ /**
+ * @brief Current configuration data.
+ */
+ const ICUConfig *config;
+ /**
+ * @brief CH Counter clock.
+ */
+ uint32_t clock;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the eMIOSx registers block.
+ */
+ volatile struct EMIOS_tag *emiosp;
+ /**
+ * @brief CCR register used for width capture.
+ */
+ volatile vuint32_t *wccrp;
+ /**
+ * @brief CCR register used for period capture.
+ */
+ volatile vuint32_t *pccrp;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Returns the width of the latest pulse.
+ * @details The pulse width is defined as number of ticks between the start
+ * edge and the stop edge.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ * @return The number of ticks.
+ *
+ * @notapi
+ */
+#define icu_lld_get_width(icup) (*((icup)->wccrp) + 1)
+
+/**
+ * @brief Returns the width of the latest cycle.
+ * @details The cycle width is defined as number of ticks between a start
+ * edge and the next start edge.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ * @return The number of ticks.
+ *
+ * @notapi
+ */
+#define icu_lld_get_period(icup) (*((icup)->pccrp) + 1)
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if SPC5_ICU_USE_EMIOS_CH0 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD1;
+#endif
+
+#if SPC5_ICU_USE_EMIOS_CH1 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD2;
+#endif
+
+#if SPC5_ICU_USE_EMIOS_CH2 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD3;
+#endif
+
+#if SPC5_ICU_USE_EMIOS_CH3 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD4;
+#endif
+
+#if SPC5_ICU_USE_EMIOS_CH4 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD5;
+#endif
+
+#if SPC5_ICU_USE_EMIOS_CH5 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD6;
+#endif
+
+#if SPC5_ICU_USE_EMIOS_CH6 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD7;
+#endif
+
+#if SPC5_ICU_USE_EMIOS_CH8 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD8;
+#endif
+
+#if SPC5_ICU_USE_EMIOS_CH7 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD9;
+#endif
+
+#if SPC5_ICU_USE_EMIOS_CH16 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD10;
+#endif
+
+#if SPC5_ICU_USE_EMIOS_CH17 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD11;
+#endif
+
+#if SPC5_ICU_USE_EMIOS_CH18 && !defined(__DOXYGEN__)
+extern ICUDriver ICUD12;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void icu_lld_init(void);
+ void icu_lld_start(ICUDriver *icup);
+ void icu_lld_stop(ICUDriver *icup);
+ void icu_lld_enable(ICUDriver *icup);
+ void icu_lld_disable(ICUDriver *icup);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_ICU */
+
+#endif /* _ICU_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.c b/os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.c new file mode 100644 index 000000000..ea07281a9 --- /dev/null +++ b/os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.c @@ -0,0 +1,951 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC5xx/eMIOS200_v1/pwm_lld.c
+ * @brief SPC5xx low level pwm driver code.
+ *
+ * @addtogroup PWM
+ * @{
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_PWM || defined(__DOXYGEN__)
+
+#include "spc5_emios.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief PWMD1 driver identifier.
+ * @note The driver PWMD1 allocates the unified channel EMIOS_CH9
+ * when enabled.
+ */
+#if SPC5_PWM_USE_EMIOS_CH9 || defined(__DOXYGEN__)
+PWMDriver PWMD1;
+#endif
+
+/**
+ * @brief PWMD2 driver identifier.
+ * @note The driver PWMD2 allocates the unified channel EMIOS_CH10
+ * when enabled.
+ */
+#if SPC5_PWM_USE_EMIOS_CH10 || defined(__DOXYGEN__)
+PWMDriver PWMD2;
+#endif
+
+/**
+ * @brief PWMD3 driver identifier.
+ * @note The driver PWMD3 allocates the unified channel EMIOS_CH11
+ * when enabled.
+ */
+#if SPC5_PWM_USE_EMIOS_CH11 || defined(__DOXYGEN__)
+PWMDriver PWMD3;
+#endif
+
+/**
+ * @brief PWMD4 driver identifier.
+ * @note The driver PWMD4 allocates the unified channel EMIOS_CH12
+ * when enabled.
+ */
+#if SPC5_PWM_USE_EMIOS_CH12 || defined(__DOXYGEN__)
+PWMDriver PWMD4;
+#endif
+
+/**
+ * @brief PWMD5 driver identifier.
+ * @note The driver PWMD5 allocates the unified channel EMIOS_CH13
+ * when enabled.
+ */
+#if SPC5_PWM_USE_EMIOS_CH13 || defined(__DOXYGEN__)
+PWMDriver PWMD5;
+#endif
+
+/**
+ * @brief PWMD6 driver identifier.
+ * @note The driver PWMD6 allocates the unified channel EMIOS_CH14
+ * when enabled.
+ */
+#if SPC5_PWM_USE_EMIOS_CH14 || defined(__DOXYGEN__)
+PWMDriver PWMD6;
+#endif
+
+/**
+ * @brief PWMD7 driver identifier.
+ * @note The driver PWMD7 allocates the unified channel EMIOS_CH15
+ * when enabled.
+ */
+#if SPC5_PWM_USE_EMIOS_CH15 || defined(__DOXYGEN__)
+PWMDriver PWMD7;
+#endif
+
+/**
+ * @brief PWMD8 driver identifier.
+ * @note The driver PWMD8 allocates the unified channel EMIOS_CH23
+ * when enabled.
+ */
+#if SPC5_PWM_USE_EMIOS_CH23 || defined(__DOXYGEN__)
+PWMDriver PWMD8;
+#endif
+
+/**
+ * @brief PWMD9 driver identifier.
+ * @note The driver PWMD9 allocates the unified channel EMIOS_CH19
+ * when enabled.
+ */
+#if SPC5_PWM_USE_EMIOS_CH19 || defined(__DOXYGEN__)
+PWMDriver PWMD9;
+#endif
+
+/**
+ * @brief PWMD10 driver identifier.
+ * @note The driver PWMD10 allocates the unified channel EMIOS_CH20
+ * when enabled.
+ */
+#if SPC5_PWM_USE_EMIOS_CH20 || defined(__DOXYGEN__)
+PWMDriver PWMD10;
+#endif
+
+/**
+ * @brief PWMD11 driver identifier.
+ * @note The driver PWMD11 allocates the unified channel EMIOS_CH21
+ * when enabled.
+ */
+#if SPC5_PWM_USE_EMIOS_CH21 || defined(__DOXYGEN__)
+PWMDriver PWMD11;
+#endif
+
+/**
+ * @brief PWMD12 driver identifier.
+ * @note The driver PWMD12 allocates the unified channel EMIOS_CH22
+ * when enabled.
+ */
+#if SPC5_PWM_USE_EMIOS_CH22 || defined(__DOXYGEN__)
+PWMDriver PWMD12;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief PWM IRQ handler.
+ *
+ * @param[in] pwmp pointer to the @p PWMDriver object
+ */
+static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
+
+ uint32_t sr = pwmp->emiosp->CH[pwmp->ch_number].CSR.R;
+
+ if(sr && EMIOSS_OVFL){
+ pwmp->emiosp->CH[pwmp->ch_number].CSR.R |= EMIOSS_OVFLC;
+ }
+ if(sr && EMIOSS_OVR){
+ pwmp->emiosp->CH[pwmp->ch_number].CSR.R |= EMIOSS_OVRC;
+ }
+ if (sr && EMIOSS_FLAG){
+ pwmp->emiosp->CH[pwmp->ch_number].CSR.R |= EMIOSS_FLAGC;
+
+ if (pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_HIGH) {
+ if (pwmp->emiosp->CH[pwmp->ch_number].CSR.B.UCOUT == 1U && \
+ pwmp->config->callback != NULL) {
+ pwmp->config->callback(pwmp);
+ } else if (pwmp->emiosp->CH[pwmp->ch_number].CSR.B.UCOUT == 0 && \
+ pwmp->config->channels[0].callback != NULL) {
+ pwmp->config->channels[0].callback(pwmp);
+ }
+ } else if (pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_LOW) {
+ if (pwmp->emiosp->CH[pwmp->ch_number].CSR.B.UCOUT == 0 && \
+ pwmp->config->callback != NULL) {
+ pwmp->config->callback(pwmp);
+ } else if (pwmp->emiosp->CH[pwmp->ch_number].CSR.B.UCOUT == 1U && \
+ pwmp->config->channels[0].callback != NULL) {
+ pwmp->config->channels[0].callback(pwmp);
+ }
+ }
+ }
+
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if SPC5_PWM_USE_EMIOS_CH9
+#if !defined(SPC5_EMIOS_FLAG_F9_HANDLER)
+#error "SPC5_EMIOS_FLAG_F9_HANDLER not defined"
+#endif
+/**
+ * @brief EMIOS Channel 9 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F9_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ pwm_lld_serve_interrupt(&PWMD1);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_PWM_USE_EMIOS_CH9 */
+
+#if SPC5_PWM_USE_EMIOS_CH10
+#if !defined(SPC5_EMIOS_FLAG_F10_HANDLER)
+#error "SPC5_EMIOS_FLAG_F10_HANDLER not defined"
+#endif
+/**
+ * @brief EMIOS Channel 10 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F10_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ pwm_lld_serve_interrupt(&PWMD2);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_PWM_USE_EMIOS_CH10 */
+
+#if SPC5_PWM_USE_EMIOS_CH11
+#if !defined(SPC5_EMIOS_FLAG_F11_HANDLER)
+#error "SPC5_EMIOS_FLAG_F11_HANDLER not defined"
+#endif
+/**
+ * @brief EMIOS Channel 11 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F11_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ pwm_lld_serve_interrupt(&PWMD3);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_PWM_USE_EMIOS_CH11 */
+
+#if SPC5_PWM_USE_EMIOS_CH12
+#if !defined(SPC5_EMIOS_FLAG_F12_HANDLER)
+#error "SPC5_EMIOS_FLAG_F12_HANDLER not defined"
+#endif
+/**
+ * @brief EMIOS Channel 12 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F12_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ pwm_lld_serve_interrupt(&PWMD4);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_PWM_USE_EMIOS_CH12 */
+
+#if SPC5_PWM_USE_EMIOS_CH13
+#if !defined(SPC5_EMIOS_FLAG_F13_HANDLER)
+#error "SPC5_EMIOS_FLAG_F13_HANDLER not defined"
+#endif
+/**
+ * @brief EMIOS Channel 13 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F13_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ pwm_lld_serve_interrupt(&PWMD5);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_PWM_USE_EMIOS_CH13 */
+
+#if SPC5_PWM_USE_EMIOS_CH14
+#if !defined(SPC5_EMIOS_FLAG_F14_HANDLER)
+#error "SPC5_EMIOS_FLAG_F14_HANDLER not defined"
+#endif
+/**
+ * @brief EMIOS Channel 14 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F14_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ pwm_lld_serve_interrupt(&PWMD6);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_PWM_USE_EMIOS_CH14 */
+
+#if SPC5_PWM_USE_EMIOS_CH15
+#if !defined(SPC5_EMIOS_FLAG_F15_HANDLER)
+#error "SPC5_EMIOS_FLAG_F15_HANDLER not defined"
+#endif
+/**
+ * @brief EMIOS Channel 15 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F15_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ pwm_lld_serve_interrupt(&PWMD7);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_PWM_USE_EMIOS_CH15 */
+
+#if SPC5_PWM_USE_EMIOS_CH19
+#if !defined(SPC5_EMIOS_FLAG_F19_HANDLER)
+#error "SPC5_EMIOS_FLAG_F19_HANDLER not defined"
+#endif
+/**
+ * @brief EMIOS Channel 19 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F19_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ pwm_lld_serve_interrupt(&PWMD9);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_PWM_USE_EMIOS_CH19 */
+
+#if SPC5_PWM_USE_EMIOS_CH20
+#if !defined(SPC5_EMIOS_FLAG_F20_HANDLER)
+#error "SPC5_EMIOS_FLAG_F20_HANDLER not defined"
+#endif
+/**
+ * @brief EMIOS Channel 20 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F20_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ pwm_lld_serve_interrupt(&PWMD10);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_PWM_USE_EMIOS_CH20 */
+
+#if SPC5_PWM_USE_EMIOS_CH21
+#if !defined(SPC5_EMIOS_FLAG_F21_HANDLER)
+#error "SPC5_EMIOS_FLAG_F21_HANDLER not defined"
+#endif
+/**
+ * @brief EMIOS Channel 21 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F21_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ pwm_lld_serve_interrupt(&PWMD11);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_PWM_USE_EMIOS_CH21 */
+
+#if SPC5_PWM_USE_EMIOS_CH22
+#if !defined(SPC5_EMIOS_FLAG_F22_HANDLER)
+#error "SPC5_EMIOS_FLAG_F22_HANDLER not defined"
+#endif
+/**
+ * @brief EMIOS Channel 22 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F22_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ pwm_lld_serve_interrupt(&PWMD12);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_PWM_USE_EMIOS_CH22 */
+
+#if SPC5_PWM_USE_EMIOS_CH23
+#if !defined(SPC5_EMIOS_FLAG_F23_HANDLER)
+#error "SPC5_EMIOS_FLAG_F23_HANDLER not defined"
+#endif
+/**
+ * @brief EMIOS Channel 23 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_EMIOS_FLAG_F23_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ pwm_lld_serve_interrupt(&PWMD8);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_PWM_USE_EMIOS_CH23 */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level PWM driver initialization.
+ *
+ * @notapi
+ */
+void pwm_lld_init(void) {
+ /* eMIOSx channels initially all not in use.*/
+ reset_emios_active_channels();
+
+#if SPC5_PWM_USE_EMIOS_CH9
+ /* Driver initialization.*/
+ pwmObjectInit(&PWMD1);
+ PWMD1.emiosp = &EMIOS;
+ PWMD1.ch_number = 9U;
+#endif /* SPC5_PWM_USE_EMIOS_CH9 */
+
+#if SPC5_PWM_USE_EMIOS_CH10
+ /* Driver initialization.*/
+ pwmObjectInit(&PWMD2);
+ PWMD2.emiosp = &EMIOS;
+ PWMD2.ch_number = 10U;
+#endif /* SPC5_PWM_USE_EMIOS_CH10 */
+
+#if SPC5_PWM_USE_EMIOS_CH11
+ /* Driver initialization.*/
+ pwmObjectInit(&PWMD3);
+ PWMD3.emiosp = &EMIOS;
+ PWMD3.ch_number = 11U;
+#endif /* SPC5_PWM_USE_EMIOS_CH11 */
+
+#if SPC5_PWM_USE_EMIOS_CH12
+ /* Driver initialization.*/
+ pwmObjectInit(&PWMD4);
+ PWMD4.emiosp = &EMIOS;
+ PWMD4.ch_number = 12U;
+#endif /* SPC5_PWM_USE_EMIOS_CH12 */
+
+#if SPC5_PWM_USE_EMIOS_CH13
+ /* Driver initialization.*/
+ pwmObjectInit(&PWMD5);
+ PWMD5.emiosp = &EMIOS;
+ PWMD5.ch_number = 13U;
+#endif /* SPC5_PWM_USE_EMIOS_CH13 */
+
+#if SPC5_PWM_USE_EMIOS_CH14
+ /* Driver initialization.*/
+ pwmObjectInit(&PWMD6);
+ PWMD6.emiosp = &EMIOS;
+ PWMD6.ch_number = 14U;
+#endif /* SPC5_PWM_USE_EMIOS_CH14 */
+
+#if SPC5_PWM_USE_EMIOS_CH15
+ /* Driver initialization.*/
+ pwmObjectInit(&PWMD7);
+ PWMD7.emiosp = &EMIOS;
+ PWMD7.ch_number = 15U;
+#endif /* SPC5_PWM_USE_EMIOS_CH15 */
+
+#if SPC5_PWM_USE_EMIOS_CH23
+ /* Driver initialization.*/
+ pwmObjectInit(&PWMD8);
+ PWMD8.emiosp = &EMIOS;
+ PWMD8.ch_number = 23U;
+#endif /* SPC5_PWM_USE_EMIOS_CH23 */
+
+#if SPC5_PWM_USE_EMIOS_CH19
+ /* Driver initialization.*/
+ pwmObjectInit(&PWMD9);
+ PWMD9.emiosp = &EMIOS;
+ PWMD9.ch_number = 19U;
+#endif /* SPC5_PWM_USE_EMIOS_CH19 */
+
+#if SPC5_PWM_USE_EMIOS_CH20
+ /* Driver initialization.*/
+ pwmObjectInit(&PWMD10);
+ PWMD10.emiosp = &EMIOS;
+ PWMD10.ch_number = 20U;
+#endif /* SPC5_PWM_USE_EMIOS_CH20 */
+
+#if SPC5_PWM_USE_EMIOS_CH21
+ /* Driver initialization.*/
+ pwmObjectInit(&PWMD11);
+ PWMD11.emiosp = &EMIOS;
+ PWMD11.ch_number = 21U;
+#endif /* SPC5_PWM_USE_EMIOS_CH21 */
+
+#if SPC5_PWM_USE_EMIOS_CH22
+ /* Driver initialization.*/
+ pwmObjectInit(&PWMD12);
+ PWMD12.emiosp = &EMIOS;
+ PWMD12.ch_number = 22U;
+#endif /* SPC5_PWM_USE_EMIOS_CH22 */
+
+#if SPC5_PWM_USE_EMIOS
+
+#if SPC5_EMIOS_NUM_CHANNELS == 16
+ INTC.PSR[SPC5_EMIOS_FLAG_F9_NUMBER].R = SPC5_EMIOS_FLAG_F9_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F10_NUMBER].R = SPC5_EMIOS_FLAG_F10_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F11_NUMBER].R = SPC5_EMIOS_FLAG_F11_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F12_NUMBER].R = SPC5_EMIOS_FLAG_F12_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F13_NUMBER].R = SPC5_EMIOS_FLAG_F13_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F14_NUMBER].R = SPC5_EMIOS_FLAG_F14_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F15_NUMBER].R = SPC5_EMIOS_FLAG_F15_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F23_NUMBER].R = SPC5_EMIOS_FLAG_F23_PRIORITY;
+#endif
+
+#if SPC5_EMIOS_NUM_CHANNELS == 24
+ INTC.PSR[SPC5_EMIOS_FLAG_F9_NUMBER].R = SPC5_EMIOS_FLAG_F9_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F10_NUMBER].R = SPC5_EMIOS_FLAG_F10_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F11_NUMBER].R = SPC5_EMIOS_FLAG_F11_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F12_NUMBER].R = SPC5_EMIOS_FLAG_F12_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F13_NUMBER].R = SPC5_EMIOS_FLAG_F13_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F14_NUMBER].R = SPC5_EMIOS_FLAG_F14_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F15_NUMBER].R = SPC5_EMIOS_FLAG_F15_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F19_NUMBER].R = SPC5_EMIOS_FLAG_F19_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F20_NUMBER].R = SPC5_EMIOS_FLAG_F20_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F21_NUMBER].R = SPC5_EMIOS_FLAG_F21_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F22_NUMBER].R = SPC5_EMIOS_FLAG_F22_PRIORITY;
+ INTC.PSR[SPC5_EMIOS_FLAG_F23_NUMBER].R = SPC5_EMIOS_FLAG_F23_PRIORITY;
+#endif
+
+#endif
+
+}
+
+/**
+ * @brief Configures and activates the PWM peripheral.
+ *
+ * @param[in] pwmp pointer to the @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_start(PWMDriver *pwmp) {
+
+ uint32_t psc = 0;
+
+ chDbgAssert(get_emios_active_channels() < SPC5_EMIOS_NUM_CHANNELS,
+ "pwm_lld_start(), #1", "too many channels");
+
+ if (pwmp->state == PWM_STOP) {
+#if SPC5_PWM_USE_EMIOS_CH9
+ if (&PWMD1 == pwmp) {
+ increase_emios_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS_CH9 */
+
+#if SPC5_PWM_USE_EMIOS_CH10
+ if (&PWMD2 == pwmp) {
+ increase_emios_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS_CH10 */
+
+#if SPC5_PWM_USE_EMIOS_CH11
+ if (&PWMD3 == pwmp) {
+ increase_emios_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS_CH11 */
+
+#if SPC5_PWM_USE_EMIOS_CH12
+ if (&PWMD4 == pwmp) {
+ increase_emios_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS_CH12 */
+
+#if SPC5_PWM_USE_EMIOS_CH13
+ if (&PWMD5 == pwmp) {
+ increase_emios_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS_CH13 */
+
+#if SPC5_PWM_USE_EMIOS_CH14
+ if (&PWMD6 == pwmp) {
+ increase_emios_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS_CH14 */
+
+#if SPC5_PWM_USE_EMIOS_CH15
+ if (&PWMD7 == pwmp) {
+ increase_emios_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS_CH15 */
+
+#if SPC5_PWM_USE_EMIOS_CH23
+ if (&PWMD8 == pwmp) {
+ increase_emios_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS_CH23 */
+
+#if SPC5_PWM_USE_EMIOS_CH19
+ if (&PWMD9 == pwmp) {
+ increase_emios_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS_CH19 */
+
+#if SPC5_PWM_USE_EMIOS_CH20
+ if (&PWMD10 == pwmp) {
+ increase_emios_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS_CH20 */
+
+#if SPC5_PWM_USE_EMIOS_CH21
+ if (&PWMD11 == pwmp) {
+ increase_emios_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS_CH21 */
+
+#if SPC5_PWM_USE_EMIOS_CH22
+ if (&PWMD12 == pwmp) {
+ increase_emios_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS_CH22 */
+
+ /* Set eMIOS Clock.*/
+#if SPC5_PWM_USE_EMIOS
+ active_emios_clock(NULL, pwmp);
+#endif
+
+ }
+ /* Configures the peripheral.*/
+
+ /* Channel enables.*/
+ pwmp->emiosp->UCDIS.R &= ~(1 << pwmp->ch_number);
+
+ /* Clear pending IRQs (if any).*/
+ pwmp->emiosp->CH[pwmp->ch_number].CSR.R = EMIOSS_OVRC |
+ EMIOSS_OVFLC | EMIOSS_FLAGC;
+
+ /* Set clock prescaler and control register.*/
+ psc = (SPC5_EMIOS_CLK / pwmp->config->frequency);
+ chDbgAssert((psc <= 0xFFFF) &&
+ (((psc) * pwmp->config->frequency) == SPC5_EMIOS_CLK) &&
+ ((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)),
+ "pwm_lld_start(), #1", "invalid frequency");
+
+ if (pwmp->config->mode == PWM_ALIGN_EDGE) {
+ pwmp->emiosp->CH[pwmp->ch_number].CCR.B.UCPREN = 0;
+ pwmp->emiosp->CH[pwmp->ch_number].CCR.B.UCPRE = psc - 1U;
+ pwmp->emiosp->CH[pwmp->ch_number].CCR.B.UCPREN = 1U;
+ pwmp->emiosp->CH[pwmp->ch_number].CCNTR.R = 1U;
+ pwmp->emiosp->CH[pwmp->ch_number].CADR.R = 0U;
+ pwmp->emiosp->CH[pwmp->ch_number].CBDR.R = pwmp->config->period;
+ pwmp->emiosp->CH[pwmp->ch_number].CCR.R |=
+ EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER) | EMIOS_CCR_MODE_OPWFMB | 2U;
+ pwmp->emiosp->CH[pwmp->ch_number].CCR.R |= EMIOSC_UCPREN;;
+
+ /* Set output polarity.*/
+ if(pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_LOW) {
+ pwmp->emiosp->CH[pwmp->ch_number].CCR.R |= EMIOSC_EDPOL;
+ } else if(pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_HIGH) {
+ pwmp->emiosp->CH[pwmp->ch_number].CCR.R &= ~EMIOSC_EDPOL;
+ }
+
+ /* Channel disables.*/
+ pwmp->emiosp->UCDIS.R |= (1 << pwmp->ch_number);
+
+ } else if (pwmp->config->mode == PWM_ALIGN_CENTER){
+ /* Not implemented.*/
+ }
+
+}
+
+/**
+ * @brief Deactivates the PWM peripheral.
+ *
+ * @param[in] pwmp pointer to the @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_stop(PWMDriver *pwmp) {
+
+ chDbgAssert(get_emios_active_channels() < SPC5_EMIOS_NUM_CHANNELS,
+ "pwm_lld_stop(), #1", "too many channels");
+
+ if (pwmp->state == PWM_READY) {
+
+ /* Disables the peripheral.*/
+#if SPC5_PWM_USE_EMIOS_CH9
+ if (&PWMD1 == pwmp) {
+ /* Reset UC Control Register.*/
+ pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
+
+ decrease_emios_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS_CH9 */
+
+#if SPC5_PWM_USE_EMIOS_CH10
+ if (&PWMD2 == pwmp) {
+ /* Reset UC Control Register.*/
+ pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
+
+ decrease_emios_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS_CH10 */
+
+#if SPC5_PWM_USE_EMIOS_CH11
+ if (&PWMD3 == pwmp) {
+ /* Reset UC Control Register.*/
+ pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
+
+ decrease_emios_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS_CH11 */
+
+#if SPC5_PWM_USE_EMIOS_CH12
+ if (&PWMD4 == pwmp) {
+ /* Reset UC Control Register.*/
+ pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
+
+ decrease_emios_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS_CH12 */
+
+#if SPC5_PWM_USE_EMIOS_CH13
+ if (&PWMD5 == pwmp) {
+ /* Reset UC Control Register.*/
+ pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
+
+ decrease_emios_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS_CH13 */
+
+#if SPC5_PWM_USE_EMIOS_CH14
+ if (&PWMD6 == pwmp) {
+ /* Reset UC Control Register.*/
+ pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
+
+ decrease_emios_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS_CH14 */
+
+#if SPC5_PWM_USE_EMIOS_CH15
+ if (&PWMD7 == pwmp) {
+ /* Reset UC Control Register.*/
+ pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
+
+ decrease_emios_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS_CH15 */
+
+#if SPC5_PWM_USE_EMIOS_CH23
+ if (&PWMD8 == pwmp) {
+ /* Reset UC Control Register.*/
+ pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
+
+ decrease_emios_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS_CH23 */
+
+#if SPC5_PWM_USE_EMIOS_CH19
+ if (&PWMD9 == pwmp) {
+ /* Reset UC Control Register.*/
+ pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
+
+ decrease_emios_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS_CH19 */
+
+#if SPC5_PWM_USE_EMIOS_CH20
+ if (&PWMD10 == pwmp) {
+ /* Reset UC Control Register.*/
+ pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
+
+ decrease_emios_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS_CH20 */
+
+#if SPC5_PWM_USE_EMIOS_CH21
+ if (&PWMD11 == pwmp) {
+ /* Reset UC Control Register.*/
+ pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
+
+ decrease_emios_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS_CH21 */
+
+#if SPC5_PWM_USE_EMIOS_CH22
+ if (&PWMD12 == pwmp) {
+ /* Reset UC Control Register.*/
+ pwmp->emiosp->CH[pwmp->ch_number].CCR.R = 0;
+
+ decrease_emios_active_channels();
+ }
+#endif /* SPC5_PWM_USE_EMIOS_CH22 */
+
+ /* eMIOS clock deactivation.*/
+#if SPC5_PWM_USE_EMIOS
+ deactive_emios_clock();
+#endif
+
+ }
+}
+
+/**
+ * @brief Changes the period the PWM peripheral.
+ * @details This function changes the period of a PWM unit that has already
+ * been activated using @p pwmStart().
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The PWM unit period is changed to the new value.
+ * @note The function has effect at the next cycle start.
+ * @note If a period is specified that is shorter than the pulse width
+ * programmed in one of the channels then the behavior is not
+ * guaranteed.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] period new cycle time in ticks
+ *
+ * @notapi
+ */
+void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period) {
+
+ pwmp->period = period;
+ pwmp->emiosp->CH[pwmp->ch_number].CBDR.R = period;
+
+}
+
+/**
+ * @brief Enables a PWM channel.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The channel is active using the specified configuration.
+ * @note Depending on the hardware implementation this function has
+ * effect starting on the next cycle (recommended implementation)
+ * or immediately (fallback implementation).
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
+ * @param[in] width PWM pulse width as clock pulses number
+ *
+ * @notapi
+ */
+void pwm_lld_enable_channel(PWMDriver *pwmp,
+ pwmchannel_t channel,
+ pwmcnt_t width) {
+
+ (void)channel;
+
+ /* Clear pending IRQs (if any).*/
+ pwmp->emiosp->CH[pwmp->ch_number].CSR.R = EMIOSS_OVRC |
+ EMIOSS_OVFLC | EMIOSS_FLAGC;
+
+ /* Set pwm width.*/
+ pwmp->emiosp->CH[pwmp->ch_number].CADR.R = width;
+
+ /* Active interrupts.*/
+ if (pwmp->config->callback != NULL || \
+ pwmp->config->channels[0].callback != NULL) {
+ pwmp->emiosp->CH[pwmp->ch_number].CCR.B.FEN = 1U;
+ }
+
+ /* Channel enables.*/
+ pwmp->emiosp->UCDIS.R &= ~(1 << pwmp->ch_number);
+
+}
+
+/**
+ * @brief Disables a PWM channel.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The channel is disabled and its output line returned to the
+ * idle state.
+ * @note Depending on the hardware implementation this function has
+ * effect starting on the next cycle (recommended implementation)
+ * or immediately (fallback implementation).
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
+ *
+ * @notapi
+ */
+void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
+
+ (void)channel;
+ /* Clear pending IRQs (if any).*/
+ pwmp->emiosp->CH[pwmp->ch_number].CSR.R = EMIOSS_OVRC |
+ EMIOSS_OVFLC | EMIOSS_FLAGC;
+
+ /* Disable interrupts.*/
+ pwmp->emiosp->CH[pwmp->ch_number].CCR.B.FEN = 0;
+
+ /* Channel disables.*/
+ pwmp->emiosp->UCDIS.R |= (1 << pwmp->ch_number);
+
+}
+
+#endif /* HAL_USE_PWM */
+
+/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.h b/os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.h new file mode 100644 index 000000000..c344a2006 --- /dev/null +++ b/os/hal/platforms/SPC5xx/eMIOS200_v1/pwm_lld.h @@ -0,0 +1,457 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC5xx/eMIOS200_v1/pwm_lld.h
+ * @brief SPC5xx low level pwm driver header.
+ *
+ * @addtogroup PWM
+ * @{
+ */
+
+#ifndef _PWM_LLD_H_
+#define _PWM_LLD_H_
+
+#if HAL_USE_PWM || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of PWM channels per PWM driver.
+ */
+#define PWM_CHANNELS 1
+
+/**
+ * @brief Edge-Aligned PWM functional mode.
+ * @note This is an SPC5-specific setting.
+ */
+#define PWM_ALIGN_EDGE 0x00
+
+/**
+ * @brief Center-Aligned PWM functional mode.
+ * @note This is an SPC5-specific setting.
+ */
+#define PWM_ALIGN_CENTER 0x01
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief PWMD1 driver enable switch.
+ * @details If set to @p TRUE the support for PWMD1 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_PWM_USE_EMIOS_CH9) || defined(__DOXYGEN__)
+#define SPC5_PWM_USE_EMIOS_CH9 FALSE
+#endif
+
+/**
+ * @brief PWMD2 driver enable switch.
+ * @details If set to @p TRUE the support for PWMD2 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_PWM_USE_EMIOS_CH10) || defined(__DOXYGEN__)
+#define SPC5_PWM_USE_EMIOS_CH10 FALSE
+#endif
+
+/**
+ * @brief PWMD3 driver enable switch.
+ * @details If set to @p TRUE the support for PWMD3 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_PWM_USE_EMIOS_CH11) || defined(__DOXYGEN__)
+#define SPC5_PWM_USE_EMIOS_CH11 FALSE
+#endif
+
+/**
+ * @brief PWMD4 driver enable switch.
+ * @details If set to @p TRUE the support for PWMD4 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_PWM_USE_EMIOS_CH12) || defined(__DOXYGEN__)
+#define SPC5_PWM_USE_EMIOS_CH12 FALSE
+#endif
+
+/**
+ * @brief PWMD5 driver enable switch.
+ * @details If set to @p TRUE the support for PWMD5 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_PWM_USE_EMIOS_CH13) || defined(__DOXYGEN__)
+#define SPC5_PWM_USE_EMIOS_CH13 FALSE
+#endif
+
+/**
+ * @brief PWMD6 driver enable switch.
+ * @details If set to @p TRUE the support for PWMD6 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_PWM_USE_EMIOS_CH14) || defined(__DOXYGEN__)
+#define SPC5_PWM_USE_EMIOS_CH14 FALSE
+#endif
+
+/**
+ * @brief PWMD7 driver enable switch.
+ * @details If set to @p TRUE the support for PWMD7 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_PWM_USE_EMIOS_CH15) || defined(__DOXYGEN__)
+#define SPC5_PWM_USE_EMIOS_CH15 FALSE
+#endif
+
+/**
+ * @brief PWMD8 driver enable switch.
+ * @details If set to @p TRUE the support for PWMD8 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_PWM_USE_EMIOS_CH23) || defined(__DOXYGEN__)
+#define SPC5_PWM_USE_EMIOS_CH23 FALSE
+#endif
+
+/**
+ * @brief PWMD9 driver enable switch.
+ * @details If set to @p TRUE the support for PWMD9 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_PWM_USE_EMIOS_CH19) || defined(__DOXYGEN__)
+#define SPC5_PWM_USE_EMIOS_CH19 FALSE
+#endif
+
+/**
+ * @brief PWMD10 driver enable switch.
+ * @details If set to @p TRUE the support for PWMD10 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_PWM_USE_EMIOS_CH20) || defined(__DOXYGEN__)
+#define SPC5_PWM_USE_EMIOS_CH20 FALSE
+#endif
+
+/**
+ * @brief PWMD11 driver enable switch.
+ * @details If set to @p TRUE the support for PWMD11 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_PWM_USE_EMIOS_CH21) || defined(__DOXYGEN__)
+#define SPC5_PWM_USE_EMIOS_CH21 FALSE
+#endif
+
+/**
+ * @brief PWMD12 driver enable switch.
+ * @details If set to @p TRUE the support for PWMD12 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(SPC5_PWM_USE_EMIOS_CH22) || defined(__DOXYGEN__)
+#define SPC5_PWM_USE_EMIOS_CH22 FALSE
+#endif
+
+/**
+ * @brief PWMD1 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS_FLAG_F9_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS_FLAG_F9_PRIORITY 7
+#endif
+
+/**
+ * @brief PWMD2 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS_FLAG_F10_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS_FLAG_F10_PRIORITY 7
+#endif
+
+/**
+ * @brief PWMD3 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS_FLAG_F11_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS_FLAG_F11_PRIORITY 7
+#endif
+
+/**
+ * @brief PWMD4 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS_FLAG_F12_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS_FLAG_F12_PRIORITY 7
+#endif
+
+/**
+ * @brief PWMD5 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS_FLAG_F13_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS_FLAG_F13_PRIORITY 7
+#endif
+
+/**
+ * @brief PWMD6 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS_FLAG_F14_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS_FLAG_F14_PRIORITY 7
+#endif
+
+/**
+ * @brief PWMD7 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS_FLAG_F15_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS_FLAG_F15_PRIORITY 7
+#endif
+
+/**
+ * @brief PWMD8 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS_FLAG_F23_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS_FLAG_F23_PRIORITY 7
+#endif
+
+/**
+ * @brief PWMD9 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS_FLAG_F19_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS_FLAG_F19_PRIORITY 7
+#endif
+
+/**
+ * @brief PWMD10 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS_FLAG_F20_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS_FLAG_F20_PRIORITY 7
+#endif
+
+/**
+ * @brief PWMD11 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS_FLAG_F21_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS_FLAG_F21_PRIORITY 7
+#endif
+
+/**
+ * @brief PWMD12 interrupt priority level setting.
+ */
+#if !defined(SPC5_EMIOS_FLAG_F22_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_EMIOS_FLAG_F22_PRIORITY 7
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if !SPC5_HAS_EMIOS
+#error "EMIOS not present in the selected device"
+#endif
+
+#define SPC5_PWM_USE_EMIOS (SPC5_PWM_USE_EMIOS_CH9 || \
+ SPC5_PWM_USE_EMIOS_CH10 || \
+ SPC5_PWM_USE_EMIOS_CH11 || \
+ SPC5_PWM_USE_EMIOS_CH12 || \
+ SPC5_PWM_USE_EMIOS_CH13 || \
+ SPC5_PWM_USE_EMIOS_CH14 || \
+ SPC5_PWM_USE_EMIOS_CH15 || \
+ SPC5_PWM_USE_EMIOS_CH19 || \
+ SPC5_PWM_USE_EMIOS_CH20 || \
+ SPC5_PWM_USE_EMIOS_CH21 || \
+ SPC5_PWM_USE_EMIOS_CH22 || \
+ SPC5_PWM_USE_EMIOS_CH23)
+
+#if !SPC5_PWM_USE_EMIOS
+#error "PWM driver activated but no Channels assigned"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief PWM mode type.
+ */
+typedef uint32_t pwmmode_t;
+
+/**
+ * @brief PWM channel type.
+ */
+typedef uint8_t pwmchannel_t;
+
+/**
+ * @brief PWM counter type.
+ */
+typedef uint32_t pwmcnt_t;
+
+/**
+ * @brief PWM driver channel configuration structure.
+ * @note Some architectures may not be able to support the channel mode
+ * or the callback, in this case the fields are ignored.
+ */
+typedef struct {
+ /**
+ * @brief Channel active logic level.
+ */
+ pwmmode_t mode;
+ /**
+ * @brief Channel callback pointer.
+ * @note This callback is invoked on the channel compare event. If set to
+ * @p NULL then the callback is disabled.
+ */
+ pwmcallback_t callback;
+ /* End of the mandatory fields.*/
+} PWMChannelConfig;
+
+/**
+ * @brief Driver configuration structure.
+ * @note Implementations may extend this structure to contain more,
+ * architecture dependent, fields.
+ */
+typedef struct {
+ /**
+ * @brief Timer clock in Hz.
+ * @note The low level can use assertions in order to catch invalid
+ * frequency specifications.
+ */
+ uint32_t frequency;
+ /**
+ * @brief PWM period in ticks.
+ * @note The low level can use assertions in order to catch invalid
+ * period specifications.
+ */
+ pwmcnt_t period;
+ /**
+ * @brief Periodic callback pointer.
+ * @note This callback is invoked on PWM counter reset. If set to
+ * @p NULL then the callback is disabled.
+ */
+ pwmcallback_t callback;
+ /**
+ * @brief Channels configurations.
+ */
+ PWMChannelConfig channels[PWM_CHANNELS];
+ /* End of the mandatory fields.*/
+ /**
+ * @brief PWM functional mode.
+ */
+ pwmmode_t mode;
+} PWMConfig;
+
+/**
+ * @brief Structure representing an PWM driver.
+ * @note Implementations may extend this structure to contain more,
+ * architecture dependent, fields.
+ */
+struct PWMDriver {
+ /**
+ * @brief Driver state.
+ */
+ pwmstate_t state;
+ /**
+ * @brief eMIOSx channel number.
+ */
+ uint8_t ch_number;
+ /**
+ * @brief Current configuration data.
+ */
+ const PWMConfig *config;
+ /**
+ * @brief Current PWM period in ticks.
+ */
+ pwmcnt_t period;
+#if defined(PWM_DRIVER_EXT_FIELDS)
+ PWM_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the eMIOSx registers block.
+ */
+ volatile struct EMIOS_tag *emiosp;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if SPC5_PWM_USE_EMIOS_CH9 && !defined(__DOXYGEN__)
+extern PWMDriver PWMD1;
+#endif
+
+#if SPC5_PWM_USE_EMIOS_CH10 && !defined(__DOXYGEN__)
+extern PWMDriver PWMD2;
+#endif
+
+#if SPC5_PWM_USE_EMIOS_CH11 && !defined(__DOXYGEN__)
+extern PWMDriver PWMD3;
+#endif
+
+#if SPC5_PWM_USE_EMIOS_CH12 && !defined(__DOXYGEN__)
+extern PWMDriver PWMD4;
+#endif
+
+#if SPC5_PWM_USE_EMIOS_CH13 && !defined(__DOXYGEN__)
+extern PWMDriver PWMD5;
+#endif
+
+#if SPC5_PWM_USE_EMIOS_CH14 && !defined(__DOXYGEN__)
+extern PWMDriver PWMD6;
+#endif
+
+#if SPC5_PWM_USE_EMIOS_CH15 && !defined(__DOXYGEN__)
+extern PWMDriver PWMD7;
+#endif
+
+#if SPC5_PWM_USE_EMIOS_CH23 && !defined(__DOXYGEN__)
+extern PWMDriver PWMD8;
+#endif
+
+#if SPC5_PWM_USE_EMIOS_CH19 && !defined(__DOXYGEN__)
+extern PWMDriver PWMD9;
+#endif
+
+#if SPC5_PWM_USE_EMIOS_CH20 && !defined(__DOXYGEN__)
+extern PWMDriver PWMD10;
+#endif
+
+#if SPC5_PWM_USE_EMIOS_CH21 && !defined(__DOXYGEN__)
+extern PWMDriver PWMD11;
+#endif
+
+#if SPC5_PWM_USE_EMIOS_CH22 && !defined(__DOXYGEN__)
+extern PWMDriver PWMD12;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void pwm_lld_init(void);
+ void pwm_lld_start(PWMDriver *pwmp);
+ void pwm_lld_stop(PWMDriver *pwmp);
+ void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period);
+ void pwm_lld_enable_channel(PWMDriver *pwmp,
+ pwmchannel_t channel,
+ pwmcnt_t width);
+ void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_PWM */
+
+#endif /* _PWM_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.c b/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.c new file mode 100644 index 000000000..0533b50e3 --- /dev/null +++ b/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.c @@ -0,0 +1,117 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC5xx/eMIOS200_v1/spc5_emios.c
+ * @brief eMIOS200 helper driver code.
+ *
+ * @addtogroup SPC5xx_eMIOS200
+ * @{
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)
+
+#include "spc5_emios.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of active eMIOSx Channels.
+ */
+static uint32_t emios_active_channels;
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+void reset_emios_active_channels() {
+ emios_active_channels = 0;
+}
+
+uint32_t get_emios_active_channels() {
+ return emios_active_channels;
+}
+
+void increase_emios_active_channels() {
+ emios_active_channels++;
+}
+
+void decrease_emios_active_channels() {
+ emios_active_channels--;
+}
+
+void active_emios_clock(ICUDriver *icup, PWMDriver *pwmp) {
+ /* If this is the first Channel activated then the eMIOS0 is enabled.*/
+ if (emios_active_channels == 1) {
+ SPC5_EMIOS_ENABLE_CLOCK();
+
+ /* Disable all unified channels.*/
+ if (icup != NULL) {
+ icup->emiosp->MCR.B.GPREN = 0;
+ icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS_GLOBAL_PRESCALER);
+ icup->emiosp->MCR.R |= EMIOSMCR_GPREN;
+
+ icup->emiosp->MCR.B.GTBE = 1U;
+
+ icup->emiosp->UCDIS.R = 0xFFFFFFFF;
+
+ } else if (pwmp != NULL) {
+ pwmp->emiosp->MCR.B.GPREN = 0;
+ pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS_GLOBAL_PRESCALER);
+ pwmp->emiosp->MCR.R |= EMIOSMCR_GPREN;
+
+ pwmp->emiosp->MCR.B.GTBE = 1U;
+
+ pwmp->emiosp->UCDIS.R = 0xFFFFFFFF;
+
+ }
+
+ }
+}
+
+void deactive_emios_clock() {
+ /* If it is the last active channels then the eMIOS0 is disabled.*/
+ if (emios_active_channels == 0) {
+ SPC5_EMIOS_DISABLE_CLOCK();
+
+ }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+
+#endif /* HAL_USE_ICU || HAL_USE_PWM */
+
+/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.h b/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.h new file mode 100644 index 000000000..2a93f1184 --- /dev/null +++ b/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.h @@ -0,0 +1,114 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC5xx/eMIOS200_v1/spc5_emios.h
+ * @brief eMIOS200 helper driver header.
+ *
+ * @addtogroup SPC5xx_eMIOS200
+ * @{
+ */
+
+#ifndef _SPC5_EMIOS_H_
+#define _SPC5_EMIOS_H_
+
+#if HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+#define EMIOSMCR_MDIS (1 << 30)
+#define EMIOSMCR_FRZ (1 << 29)
+#define EMIOSMCR_GTBE (1 << 28)
+#define EMIOSMCR_GPREN (1 << 26)
+#define EMIOSMCR_GPRE(n) ((n) << 8)
+
+#define EMIOSC_FREN (1 << 31)
+#define EMIOSC_UCPRE(n) ((n) << 26)
+#define EMIOSC_UCPREN (1 << 25)
+#define EMIOSC_DMA (1 << 24)
+#define EMIOSC_IF(n) ((n) << 19)
+#define EMIOSC_FCK (1 << 18)
+#define EMIOSC_FEN (1 << 17)
+#define EMIOSC_FORCMA (1 << 13)
+#define EMIOSC_FORCMB (1 << 12)
+#define EMIOSC_BSL(n) ((n) << 9)
+#define EMIOSC_EDSEL (1 << 8)
+#define EMIOSC_EDPOL (1 << 7)
+#define EMIOSC_MODE(n) ((n) << 0)
+
+#define EMIOS_BSL_COUNTER_BUS_A 0
+#define EMIOS_BSL_COUNTER_BUS_2 1
+#define EMIOS_BSL_INTERNAL_COUNTER 3
+
+#define EMIOS_CCR_MODE_GPIO_IN 0
+#define EMIOS_CCR_MODE_GPIO_OUT 1
+#define EMIOS_CCR_MODE_SAIC 2
+#define EMIOS_CCR_MODE_SAOC 3
+#define EMIOS_CCR_MODE_IPWM 4
+#define EMIOS_CCR_MODE_IPM 5
+#define EMIOS_CCR_MODE_DAOC_B_MATCH 6
+#define EMIOS_CCR_MODE_DAOC_BOTH_MATCH 7
+#define EMIOS_CCR_MODE_MC_CMS 16
+#define EMIOS_CCR_MODE_MC_CME 17
+#define EMIOS_CCR_MODE_MC_UP_DOWN 18
+#define EMIOS_CCR_MODE_OPWMT 38
+#define EMIOS_CCR_MODE_MCB 84
+#define EMIOS_CCR_MODE_OPWFMB 88
+#define EMIOS_CCR_MODE_OPWMCB_TE 92
+#define EMIOS_CCR_MODE_OPWMCB_LE 93
+#define EMIOS_CCR_MODE_OPWMB 96
+
+#define EMIOSS_OVR (1 << 31)
+#define EMIOSS_OVRC (1 << 31)
+#define EMIOSS_OVFL (1 << 15)
+#define EMIOSS_OVFLC (1 << 15)
+#define EMIOSS_FLAG (1 << 0)
+#define EMIOSS_FLAGC (1 << 0)
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+void reset_emios_active_channels(void);
+uint32_t get_emios_active_channels(void);;
+void increase_emios_active_channels(void);
+void decrease_emios_active_channels(void);
+void active_emios_clock(ICUDriver *icup, PWMDriver *pwmp);
+void deactive_emios_clock(void);
+
+#endif /* HAL_USE_ICU || HAL_USE_PWM */
+
+#endif /* _SPC5_EMIOS_H_ */
+
+/** @} */
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