diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-03-17 07:37:18 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-03-17 07:37:18 +0000 |
| commit | 3fc18fd71fd1d3266b4c606db52e2404b7bc9d77 (patch) | |
| tree | 557c149bea01ba712132505870eea0948150494a /os | |
| parent | 1f6edfef775e68d713346b9a536e0df3b9e73161 (diff) | |
| download | ChibiOS-3fc18fd71fd1d3266b4c606db52e2404b7bc9d77.tar.gz ChibiOS-3fc18fd71fd1d3266b4c606db52e2404b7bc9d77.tar.bz2 ChibiOS-3fc18fd71fd1d3266b4c606db52e2404b7bc9d77.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5445 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
| -rw-r--r-- | os/hal/platforms/STM32F30x/adc_lld.h | 8 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F37x/adc_lld.c | 737 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F37x/adc_lld.h | 696 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F37x/platform.mk | 1 |
4 files changed, 1438 insertions, 4 deletions
diff --git a/os/hal/platforms/STM32F30x/adc_lld.h b/os/hal/platforms/STM32F30x/adc_lld.h index 06039b850..7f45fb1de 100644 --- a/os/hal/platforms/STM32F30x/adc_lld.h +++ b/os/hal/platforms/STM32F30x/adc_lld.h @@ -191,28 +191,28 @@ * @brief ADC1/ADC2 interrupt priority level setting.
*/
#if !defined(STM32_ADC_ADC12_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC12_IRQ_PRIORITY 2
+#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#endif
/**
* @brief ADC3/ADC4 interrupt priority level setting.
*/
#if !defined(STM32_ADC34_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC34_IRQ_PRIORITY 2
+#define STM32_ADC_ADC34_IRQ_PRIORITY 5
#endif
/**
* @brief ADC1/ADC2 DMA interrupt priority level setting.
*/
#if !defined(STM32_ADC_ADC12_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 2
+#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 5
#endif
/**
* @brief ADC3/ADC4 DMA interrupt priority level setting.
*/
#if !defined(STM32_ADC_ADC34_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 2
+#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5
#endif
/**
diff --git a/os/hal/platforms/STM32F37x/adc_lld.c b/os/hal/platforms/STM32F37x/adc_lld.c new file mode 100644 index 000000000..a416e1eb7 --- /dev/null +++ b/os/hal/platforms/STM32F37x/adc_lld.c @@ -0,0 +1,737 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file STM32F4xx/adc_lld.c
+ * @brief STM32F4xx/STM32F2xx ADC subsystem low level driver source.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_ADC || defined(__DOXYGEN__)
+
+int debugzero = 0;
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#define ADC1_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_CHN)
+
+#define ADC2_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_CHN)
+
+#define ADC3_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_CHN)
+
+#define SDADC1_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_ADC_SDADC1_DMA_STREAM, STM32_SDADC1_DMA_CHN)
+
+#define SDADC2_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_ADC_SDADC2_DMA_STREAM, STM32_SDADC2_DMA_CHN)
+
+#define SDADC3_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_ADC_SDADC3_DMA_STREAM, STM32_SDADC3_DMA_CHN)
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief ADC1 driver identifier.*/
+#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
+ADCDriver ADCD1;
+#endif
+
+/** @brief ADC2 driver identifier.*/
+#if STM32_ADC_USE_ADC2 || defined(__DOXYGEN__)
+ADCDriver ADCD2;
+#endif
+
+/** @brief ADC3 driver identifier.*/
+#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__)
+ADCDriver ADCD3;
+#endif
+
+/** @brief SDADC1 driver identifier.*/
+#if STM32_ADC_USE_SDADC1 || defined(__DOXYGEN__)
+ADCDriver SDADCD1;
+#endif
+
+/** @brief SDADC2 driver identifier.*/
+#if STM32_ADC_USE_SDADC2 || defined(__DOXYGEN__)
+ADCDriver SDADCD2;
+#endif
+
+/** @brief SDADC3 driver identifier.*/
+#if STM32_ADC_USE_SDADC3 || defined(__DOXYGEN__)
+ADCDriver SDADCD3;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+static bool_t isADCDriverForSigmaDeltaADC(ADCDriver *adcp);
+static bool_t isADCDriverForSuccApproxADC(ADCDriver *adcp);
+
+/**
+ * @brief ADC DMA ISR service routine.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ * @param[in] flags pre-shifted content of the ISR register
+ */
+static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
+ /* DMA errors handling.*/
+ if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+ /* DMA, this could help only if the DMA tries to access an unmapped
+ address space or violates alignment rules.*/
+ _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
+ }
+ else {
+ /* It is possible that the conversion group has already be reset by the
+ ADC error handler, in this case this interrupt is spurious.*/
+ if (adcp->grpp != NULL) {
+ if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+ /* Half transfer processing.*/
+ _adc_isr_half_code(adcp);
+ }
+ if ((flags & STM32_DMA_ISR_TCIF) != 0) {
+ /* Transfer complete processing.*/
+ _adc_isr_full_code(adcp);
+ }
+ }
+ }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2 || STM32_ADC_USE_ADC3 || \
+ defined(__DOXYGEN__)
+/**
+ * @brief ADC interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) {
+ CH_IRQ_PROLOGUE();
+
+#if STM32_ADC_USE_ADC1
+ /* TODO: Add here analog watchdog handling.*/
+#endif /* STM32_ADC_USE_ADC1 */
+
+ CH_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level ADC driver initialization.
+ *
+ * @notapi
+ */
+void adc_lld_init(void) {
+
+#if STM32_ADC_USE_ADC1
+ /* Driver initialization.*/
+ adcObjectInit(&ADCD1);
+ ADCD1.adc = ADC1;
+ ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM);
+ ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
+ STM32_DMA_CR_DIR_P2M |
+ STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
+ STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+#endif
+
+#if STM32_ADC_USE_ADC2
+ /* Driver initialization.*/
+ adcObjectInit(&ADCD2);
+ ADCD2.adc = ADC2;
+ ADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM);
+ ADCD2.dmamode = STM32_DMA_CR_CHSEL(ADC2_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) |
+ STM32_DMA_CR_DIR_P2M |
+ STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
+ STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+#endif
+
+#if STM32_ADC_USE_ADC3
+ /* Driver initialization.*/
+ adcObjectInit(&ADCD3);
+ ADCD3.adc = ADC3;
+ ADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_STREAM);
+ ADCD3.dmamode = STM32_DMA_CR_CHSEL(ADC3_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) |
+ STM32_DMA_CR_DIR_P2M |
+ STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
+ STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+#endif
+
+ /* The shared vector is initialized on driver initialization and never
+ disabled.*/
+ nvicEnableVector(ADC1_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY));
+
+#if STM32_ADC_USE_SDADC1
+ /* Driver initialization.*/
+ adcObjectInit(&SDADCD1);
+ SDADCD1.sdadc = SDADC1;
+ SDADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_SDADC1_DMA_STREAM);
+ SDADCD1.dmamode = STM32_DMA_CR_CHSEL(SDADC1_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_ADC_SDADC1_DMA_PRIORITY) |
+ STM32_DMA_CR_DIR_P2M |
+ STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
+ STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+#endif
+
+#if STM32_ADC_USE_SDADC2
+ /* Driver initialization.*/
+ adcObjectInit(&SDADCD2);
+ SDADCD2.sdadc = SDADC2;
+ SDADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_SDADC2_DMA_STREAM);
+ SDADCD2.dmamode = STM32_DMA_CR_CHSEL(SDADC2_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_ADC_SDADC2_DMA_PRIORITY) |
+ STM32_DMA_CR_DIR_P2M |
+ STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
+ STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+#endif
+
+#if STM32_ADC_USE_SDADC3
+ /* Driver initialization.*/
+ adcObjectInit(&SDADCD3);
+ SDADCD3.sdadc = SDADC3;
+ SDADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_SDADC3_DMA_STREAM);
+ SDADCD3.dmamode = STM32_DMA_CR_CHSEL(SDADC3_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_ADC_SDADC3_DMA_PRIORITY) |
+ STM32_DMA_CR_DIR_P2M |
+ STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
+ STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+#endif
+
+
+ nvicEnableVector(SDADC1_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_SDADC1_IRQ_PRIORITY));
+ nvicEnableVector(SDADC2_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_SDADC2_IRQ_PRIORITY));
+ nvicEnableVector(SDADC3_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_SDADC3_IRQ_PRIORITY));
+}
+
+/**
+ * @brief Initial config for SDADC peripheral.
+ *
+ * @param[in] adcdp pointer to the @p ADCDriver object
+ * @param[in] dmaPriority priority for the dma channel 0..3
+ * @param[in] rxIsrFunc isr handler for dma,
+ * @param[in] dmaSrcLoc pointer to the @p SDADC data
+ * @param[in] periphEnableBit SDADC bit in rcc APB2 Enable register
+ *
+ * @notapi
+ */
+void sdadc_lld_start_cr_init_helper(ADCDriver* adcdp,
+ uint32_t dmaPriority,
+ stm32_dmaisr_t rxIsrFunc,
+ volatile void* dmaSrcLoc,
+ uint32_t periphEnableBit) {
+ bool_t b;
+ b = dmaStreamAllocate(adcdp->dmastp,
+ dmaPriority,
+ rxIsrFunc,
+ adcdp);
+ chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated");
+ dmaStreamSetPeripheral(adcdp->dmastp, dmaSrcLoc);
+ rccEnableAPB2(periphEnableBit, FALSE);
+ rccResetAPB2(periphEnableBit);
+
+ /* SDADC initial setup, starting the analog part here in order to reduce
+ the latency when starting a conversion.*/
+
+ /*
+ ====== SDADC CR1 settings breakdown =====
+ Initialization mode request : disabled
+ DMA Enabled to read data for reg ch. grp : disabled
+ DMA Enabled to read data for inj ch. grp : disabled
+ Launch reg conv sync w SDADC1 : Do not
+ Launch injected conv sync w SDADC1 : Do not
+ Enter power down mode when idle : False
+ Enter standby mode when idle : False
+ Slow clock mode : fast mode
+ Reference voltage selection : external Vref
+ reg data overrun interrupt : disabled
+ reg data end of conversion interrupt : disabled
+ injected data overrun interrupt : disabled
+ injected data end of conversion interrupt : disabled
+ end of calibration interrupt : disabled
+ */
+ adcdp->sdadc->CR1 = 0;
+
+ /*
+ ====== SDADC CR1 settings breakdown =====
+ SDADC enable : X
+ Number of calibration sequences to be performed : 0
+ Start calibration : NO
+ Continuous mode selection for injected conv : once
+ Delay start of injected conversions : asap
+ Trig sig sel for launching inj conv : TIM13_CH1,TIM17_CH1, TIM16_CH1
+ Trig en and trig edge sel for injected conv : disabled
+ Start a conv of the inj group of ch : 0
+ Regular channel sel (0-8) : 0
+ Continuous mode sel for regular conv : once
+ Software start of a conversion on the regular ch: 0
+ Fast conv mode sel : disabled
+ */
+ adcdp->sdadc->CR2 = 0;
+ adcdp->sdadc->CR2 = SDADC_CR2_ADON;
+}
+
+
+
+/**
+ * @brief Configures and activates the ADC peripheral.
+ *
+ * @param[in] adcdp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start(ADCDriver *adcdp) {
+
+ /* If in stopped state then enables the ADC and DMA clocks.*/
+ if (adcdp->state == ADC_STOP) {
+#if STM32_ADC_USE_ADC1
+ if (&ADCD1 == adcdp) {
+ bool_t b;
+ b = dmaStreamAllocate(adcdp->dmastp,
+ STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
+ (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
+ (void *)adcdp);
+ chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated");
+ dmaStreamSetPeripheral(adcdp->dmastp, &ADC1->DR);
+ rccEnableADC1(FALSE);
+
+ /* ADC initial setup, starting the analog part here in order to reduce
+ the latency when starting a conversion.*/
+ adcdp->adc->CR1 = 0;
+ adcdp->adc->CR2 = 0;
+ adcdp->adc->CR2 = ADC_CR2_ADON;
+ }
+#endif /* STM32_ADC_USE_ADC1 */
+
+#if STM32_ADC_USE_SDADC1
+ if (&SDADCD1 == adcdp) {
+ sdadc_lld_start_cr_init_helper(adcdp,
+ STM32_ADC_SDADC1_DMA_IRQ_PRIORITY,
+ (stm32_dmaisr_t) adc_lld_serve_rx_interrupt,
+ &SDADC1->RDATAR,
+ RCC_APB2ENR_SDADC1EN);
+ rccEnablePWRInterface(FALSE);
+ PWR->CR |= PWR_CR_SDADC1EN;
+
+ }
+#endif /* STM32_ADC_USE_SDADC1 */
+
+#if STM32_ADC_USE_SDADC2
+ if (&SDADCD2 == adcdp) {
+ sdadc_lld_start_cr_init_helper(adcdp,
+ STM32_ADC_SDADC2_DMA_IRQ_PRIORITY,
+ (stm32_dmaisr_t) adc_lld_serve_rx_interrupt,
+ &SDADC2->RDATAR,
+ RCC_APB2ENR_SDADC2EN);
+
+ rccEnablePWRInterface(FALSE);
+ PWR->CR |= PWR_CR_SDADC2EN;
+ }
+#endif /* STM32_ADC_USE_SDADC2 */
+
+#if STM32_ADC_USE_SDADC3
+ if (&SDADCD3 == adcdp) {
+ sdadc_lld_start_cr_init_helper(adcdp,
+ STM32_ADC_SDADC3_DMA_IRQ_PRIORITY,
+ (stm32_dmaisr_t) adc_lld_serve_rx_interrupt,
+ &SDADC3->RDATAR,
+ RCC_APB2ENR_SDADC3EN);
+ rccEnablePWRInterface(FALSE);
+ PWR->CR |= PWR_CR_SDADC3EN;
+ }
+#endif /* STM32_ADC_USE_SDADC3 */
+
+ }
+}
+
+/**
+ * @brief Deactivates the ADC peripheral.
+ *
+ * @param[in] adcdp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop(ADCDriver *adcdp) {
+
+ /* If in ready state then disables the ADC clock.*/
+ if (adcdp->state == ADC_READY) {
+ dmaStreamRelease(adcdp->dmastp);
+ adcdp->adc->CR1 = 0;
+ adcdp->adc->CR2 = 0;
+
+#if STM32_ADC_USE_ADC1
+ if (&ADCD1 == adcdp)
+ rccDisableADC1(FALSE);
+#endif
+
+#if STM32_ADC_USE_ADC2
+ if (&ADCD2 == adcdp)
+ rccDisableADC2(FALSE);
+#endif
+
+#if STM32_ADC_USE_ADC3
+ if (&ADCD3 == adcdp)
+ rccDisableADC3(FALSE);
+#endif
+ }
+
+#if STM32_ADC_USE_SDADC1
+ if (&SDADCD1 == adcdp)
+ rccDisableSDADC1(FALSE);
+#endif
+
+#if STM32_ADC_USE_SDADC2
+ if (&SDADCD2 == adcdp)
+ rccDisableSDADC2(FALSE);
+#endif
+
+#if STM32_ADC_USE_SDADC3
+ if (&SDADCD3 == adcdp)
+ rccDisableSDADC3(FALSE);
+#endif
+
+
+}
+
+/**
+ * @brief Starts an ADC conversion.
+ *
+ * @param[in] adcdp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start_conversion(ADCDriver *adcdp) {
+ uint32_t mode;
+
+ const ADCConversionGroup* grpp = adcdp->grpp;
+
+ /* DMA setup.*/
+ mode = adcdp->dmamode;
+ if (grpp->circular) {
+ mode |= STM32_DMA_CR_CIRC;
+ }
+ if (adcdp->depth > 1) {
+ /* If the buffer depth is greater than one then the half transfer interrupt
+ interrupt is enabled in order to allows streaming processing.*/
+ mode |= STM32_DMA_CR_HTIE;
+ }
+ dmaStreamSetMemory0(adcdp->dmastp, adcdp->samples);
+ dmaStreamSetTransactionSize(adcdp->dmastp,
+ (uint32_t)grpp->num_channels *
+ (uint32_t)adcdp->depth);
+ dmaStreamSetMode(adcdp->dmastp, mode);
+ dmaStreamEnable(adcdp->dmastp);
+
+ if (isADCDriverForSuccApproxADC(adcdp)) {
+ /* ADC setup.*/
+ adcdp->adc->SR = 0;
+ adcdp->adc->SMPR1 = grpp->ll.adc.smpr1;
+ adcdp->adc->SMPR2 = grpp->ll.adc.smpr2;
+ adcdp->adc->SQR1 = grpp->ll.adc.sqr1;
+ adcdp->adc->SQR2 = grpp->ll.adc.sqr2;
+ adcdp->adc->SQR3 = grpp->ll.adc.sqr3;
+
+ /* ADC configuration and start, the start is performed using the method
+ specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/
+ adcdp->adc->CR1 = grpp->ll.adc.cr1 | ADC_CR1_SCAN;
+ if ((grpp->ll.adc.cr2 & ADC_CR2_SWSTART) != 0)
+ adcdp->adc->CR2 = grpp->ll.adc.cr2 | ADC_CR2_CONT
+ | ADC_CR2_DMA | ADC_CR2_ADON;
+ else
+ adcdp->adc->CR2 = grpp->ll.adc.cr2 | ADC_CR2_DMA | ADC_CR2_ADON;
+ }
+ else if (isADCDriverForSigmaDeltaADC(adcdp)) {
+ /* For Sigma-Delta ADC */
+
+ sdadcSTM32SetInitializationMode(adcdp, true);
+
+ /* SDADC setup.*/
+ adcdp->sdadc->CONF0R = grpp->ll.sdadc.conf0r;
+ adcdp->sdadc->CONF1R = grpp->ll.sdadc.conf1r;
+ adcdp->sdadc->CONF2R = grpp->ll.sdadc.conf2r;
+ adcdp->sdadc->CONFCHR1 = grpp->ll.sdadc.confchr1;
+ adcdp->sdadc->CONFCHR2 = grpp->ll.sdadc.confchr2;
+
+ sdadcSTM32SetInitializationMode(adcdp, false);
+
+ /* SDADC configuration and start, the start is performed using the method
+ specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/
+ adcdp->sdadc->CR1 = grpp->ll.sdadc.cr1 | SDADC_CR1_RDMAEN;
+ adcdp->sdadc->CR2 = grpp->ll.sdadc.cr2 | SDADC_CR2_ADON;
+
+ }
+}
+bool_t stopconv = FALSE;
+
+/**
+ * @brief Stops an ongoing conversion.
+ *
+ * @param[in] adcdp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop_conversion(ADCDriver *adcdp) {
+ dmaStreamDisable(adcdp->dmastp);
+
+ if (isADCDriverForSuccApproxADC(adcdp)) {
+ adcdp->adc->CR1 = 0;
+ adcdp->adc->CR2 = 0;
+ adcdp->adc->CR2 = ADC_CR2_ADON;
+ }
+ else if (isADCDriverForSigmaDeltaADC(adcdp)) {
+ adcdp->sdadc->CR1 = 0;
+ adcdp->sdadc->CR2 = 0;
+ adcdp->sdadc->CR2 = ADC_CR2_ADON;
+ }
+}
+
+#if 0
+/**
+ * @brief Enables the TSVREFE bit.
+ * @details The TSVREFE bit is required in order to sample the internal
+ * temperature sensor and internal reference voltage.
+ * @note This is an STM32-only functionality.
+ */
+void adcSTM32EnableTSVREFE(void) {
+
+ ADC->CCR |= ADC_CCR_TSVREFE;
+}
+
+/**
+ * @brief Disables the TSVREFE bit.
+ * @details The TSVREFE bit is required in order to sample the internal
+ * temperature sensor and internal reference voltage.
+ * @note This is an STM32-only functionality.
+ */
+void adcSTM32DisableTSVREFE(void) {
+
+ ADC->CCR &= ~ADC_CCR_TSVREFE;
+}
+
+/**
+ * @brief Enables the VBATE bit.
+ * @details The VBATE bit is required in order to sample the VBAT channel.
+ * @note This is an STM32-only functionality.
+ * @note This function is meant to be called after @p adcStart().
+ */
+void adcSTM32EnableVBATE(void) {
+
+ ADC->CCR |= ADC_CCR_VBATE;
+}
+
+/**
+ * @brief Disables the VBATE bit.
+ * @details The VBATE bit is required in order to sample the VBAT channel.
+ * @note This is an STM32-only functionality.
+ * @note This function is meant to be called after @p adcStart().
+ */
+void adcSTM32DisableVBATE(void) {
+
+ ADC->CCR &= ~ADC_CCR_VBATE;
+}
+#endif
+
+/**
+ * @brief Sets the VREF for the 3 Sigma-Delta ADC Converters
+ * @details VREF can be changed only when all SDADCs are disabled. Disables all SDADCs, sets the value and then sleeps 5 ms waiting for the change to occur.
+ * @note This is an STM32-only functionality.
+ * @param[in] adcdp pointer to the @p ADCDriver object
+ * @param[in] enable true means init mode, false means exit init mode
+ *
+ */
+void sdadcSTM32VREFSelect(SDADC_VREF_SEL svs)
+{
+ uint32_t tmpcr1, sdadc1_adon, sdadc2_adon, sdadc3_adon;
+
+ sdadc1_adon = SDADC1->CR2 & SDADC_CR2_ADON;
+ sdadc2_adon = SDADC2->CR2 & SDADC_CR2_ADON;
+ sdadc3_adon = SDADC3->CR2 & SDADC_CR2_ADON;
+
+ SDADC1->CR2 &= ~SDADC_CR2_ADON;
+ SDADC2->CR2 &= ~SDADC_CR2_ADON;
+ SDADC3->CR2 &= ~SDADC_CR2_ADON;
+
+ /* Get SDADC1_CR1 register value */
+ tmpcr1 = SDADC1->CR1;
+
+ /* Clear the SDADC1_CR1_REFV bits */
+ tmpcr1 &= (uint32_t) (~SDADC_CR1_REFV);
+
+ /* Select the external reference voltage */
+ tmpcr1 |= svs;
+
+ /* Write in SDADC_CR1 */
+ SDADC1->CR1 = tmpcr1;
+
+ /* Insert delay equal to ~10 ms (4 ms required) */
+ chThdSleepMilliseconds(5);
+
+ SDADC1->CR2 |= sdadc1_adon;
+ SDADC2->CR2 |= sdadc2_adon;
+ SDADC3->CR2 |= sdadc3_adon;
+}
+
+/**
+ * @brief Sets the Sigma-Delta ADC Converter into initialization mode
+ * @details The sdadc is either put into init mode or exits init mode.
+ * @note This is an STM32-only functionality.
+ * @note This function is meant to be called after @p adcStart().
+ * @param[in] adcdp pointer to the @p ADCDriver object
+ * @param[in] enable true means init mode, false means exit init mode
+ *
+ */
+void sdadcSTM32SetInitializationMode(ADCDriver* adcdp, bool_t enterInitMode)
+{
+ uint32_t SDADCTimeout = 300000;
+
+ if ((adcdp == &SDADCD1) ||
+ (adcdp == &SDADCD2) ||
+ (adcdp == &SDADCD3)) {
+
+ if (enterInitMode) {
+ adcdp->sdadc->CR1 |= SDADC_CR1_INIT;
+
+ /* wait for INITRDY flag to be set */
+ while (((adcdp->sdadc->ISR & SDADC_ISR_INITRDY) == 0) &&
+ (--SDADCTimeout != 0));
+
+ if (SDADCTimeout == 0)
+ {
+ /* INITRDY flag can not set */
+ port_halt();
+ }
+ }
+ else {
+ adcdp->sdadc->CR1 &= ~SDADC_CR1_INIT;
+ }
+ }
+}
+
+/**
+ * @brief Configures the calibration sequence.
+ * @note TODO - UPDATE
+ * @param ADCDriver* one of &SDADCD1, &SDADCD2, &SDADCD3
+ * @param SDADC_CalibrationSequence: Number of calibration sequence to be performed.
+ * This parameter can be one of the following values:
+ * @arg SDADC_CalibrationSequence_1: One calibration sequence will be performed
+ * to calculate OFFSET0[11:0] (offset that corresponds to conf0)
+ * @arg SDADC_CalibrationSequence_2: Two calibration sequences will be performed
+ * to calculate OFFSET0[11:0] and OFFSET1[11:0]
+ * (offsets that correspond to conf0 and conf1)
+ * @arg SDADC_CalibrationSequence_3: Three calibration sequences will be performed
+ * to calculate OFFSET0[11:0], OFFSET1[11:0],
+ * and OFFSET2[11:0] (offsets that correspond to conf0, conf1 and conf2)
+ * @retval None
+ */
+void sdadcSTM32Calibrate(ADCDriver* adcdp,
+ SDADC_NUM_CALIB_SEQ numCalibSequences,
+ ADCConversionGroup* grpp)
+{
+ uint32_t SDADCTimeout = 0;
+ uint32_t tmpcr2 = 0;
+
+ if (!(adcdp == &SDADCD1 ||
+ adcdp == &SDADCD2 ||
+ adcdp == &SDADCD3))
+ return;
+
+ sdadcSTM32SetInitializationMode(adcdp, true);
+
+ /* SDADC setup.*/
+ adcdp->sdadc->CR2 = grpp->ll.sdadc.cr2;
+ adcdp->sdadc->CONF0R = grpp->ll.sdadc.conf0r;
+ adcdp->sdadc->CONF1R = grpp->ll.sdadc.conf1r;
+ adcdp->sdadc->CONF2R = grpp->ll.sdadc.conf2r;
+ adcdp->sdadc->CONFCHR1 = grpp->ll.sdadc.confchr1;
+ adcdp->sdadc->CONFCHR2 = grpp->ll.sdadc.confchr2;
+
+ sdadcSTM32SetInitializationMode(adcdp, false);
+
+ /* configure calibration to be performed on conf0 */
+ /* Get SDADC_CR2 register value */
+ tmpcr2 = adcdp->sdadc->CR2;
+
+ /* Clear the SDADC_CR2_CALIBCNT bits */
+ tmpcr2 &= (uint32_t) (~SDADC_CR2_CALIBCNT);
+ /* Set the calibration sequence */
+ tmpcr2 |= numCalibSequences;
+
+ /*
+ Write in SDADC_CR2 and
+ start calibration
+ */
+ adcdp->sdadc->CR2 = tmpcr2 | SDADC_CR2_STARTCALIB;
+
+ /* Set calibration timeout: 5.12 ms at 6 MHz in a single calibration sequence */
+ SDADCTimeout = SDADC_CAL_TIMEOUT;
+
+ /* wait for SDADC Calibration process to end */
+ while (((adcdp->sdadc->ISR & SDADC_ISR_EOCALF) == 0) && (--SDADCTimeout != 0));
+
+ if(SDADCTimeout == 0)
+ {
+ /* Calib timeout */
+ port_halt();
+ return;
+ }
+
+ /* cleanup by clearing EOCALF flag */
+ adcdp->sdadc->CLRISR |= SDADC_ISR_CLREOCALF;
+}
+
+static bool_t isADCDriverForSigmaDeltaADC(ADCDriver *adcdp) {
+ return (adcdp->sdadc != NULL);
+}
+
+static bool_t isADCDriverForSuccApproxADC(ADCDriver *adcdp) {
+ return (adcdp->adc != NULL);
+}
+
+#endif /* HAL_USE_ADC */
+
+/** @} */
diff --git a/os/hal/platforms/STM32F37x/adc_lld.h b/os/hal/platforms/STM32F37x/adc_lld.h new file mode 100644 index 000000000..b39053114 --- /dev/null +++ b/os/hal/platforms/STM32F37x/adc_lld.h @@ -0,0 +1,696 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file STM32F37x/adc_lld.h
+ * @brief STM32F37x ADC subsystem low level driver header.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#ifndef _ADC_LLD_H_
+#define _ADC_LLD_H_
+
+#if HAL_USE_ADC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name Triggers selection
+ * @{
+ */
+#define ADC_CR2_EXTSEL_SRC(n) ((n) << 24) /**< @brief Trigger source. */
+/** @} */
+
+/**
+ * @name ADC clock divider settings
+ * @{
+ */
+#define ADC_CCR_ADCPRE_DIV2 0
+#define ADC_CCR_ADCPRE_DIV4 1
+#define ADC_CCR_ADCPRE_DIV6 2
+#define ADC_CCR_ADCPRE_DIV8 3
+/** @} */
+
+/**
+ * @name Available analog channels
+ * @{
+ */
+#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */
+#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */
+#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */
+#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */
+#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */
+#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */
+#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */
+#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */
+#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */
+#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */
+#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */
+#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */
+#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */
+#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */
+#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */
+#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */
+#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.*/
+#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. */
+#define ADC_CHANNEL_VBAT 18 /**< @brief VBAT. */
+/** @} */
+
+/**
+ * @name Sampling rates
+ * @{
+ */
+#define ADC_SAMPLE_1P5 0 /**< @brief 1.5 cycles sampling time. */
+#define ADC_SAMPLE_7P5 1 /**< @brief 7.5 cycles sampling time. */
+#define ADC_SAMPLE_13P5 2 /**< @brief 13.5 cycles sampling time. */
+#define ADC_SAMPLE_28P5 3 /**< @brief 28.5 cycles sampling time. */
+#define ADC_SAMPLE_41P5 4 /**< @brief 41.5 cycles sampling time. */
+#define ADC_SAMPLE_55P5 5 /**< @brief 55.5 cycles sampling time. */
+#define ADC_SAMPLE_71P5 6 /**< @brief 71.5 cycles sampling time. */
+#define ADC_SAMPLE_239P5 7 /**< @brief 239.5 cycles sampling time. */
+/** @} */
+
+/**
+ * @name SDADC Channels
+ * The SDADC channels are defined as follow:
+ * - in 16-bit LSB the channel mask is set
+ * - in 16-bit MSB the channel number is set
+ * e.g. for channel 5 definition:
+ * - the channel mask is 0x00000020 (bit 5 is set)
+ * - the channel number 5 is 0x00050000
+ * --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020
+ * @{*/
+
+#define SDADC_Channel_0 ((uint32_t)0x00000001)
+#define SDADC_Channel_1 ((uint32_t)0x00010002)
+#define SDADC_Channel_2 ((uint32_t)0x00020004)
+#define SDADC_Channel_3 ((uint32_t)0x00030008)
+#define SDADC_Channel_4 ((uint32_t)0x00040010)
+#define SDADC_Channel_5 ((uint32_t)0x00050020)
+#define SDADC_Channel_6 ((uint32_t)0x00060040)
+#define SDADC_Channel_7 ((uint32_t)0x00070080)
+#define SDADC_Channel_8 ((uint32_t)0x00080100)
+
+/* Just one channel of the 9 channels can be selected for regular conversion */
+#define IS_SDADC_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == SDADC_Channel_0) || \
+ ((CHANNEL) == SDADC_Channel_1) || \
+ ((CHANNEL) == SDADC_Channel_2) || \
+ ((CHANNEL) == SDADC_Channel_3) || \
+ ((CHANNEL) == SDADC_Channel_4) || \
+ ((CHANNEL) == SDADC_Channel_5) || \
+ ((CHANNEL) == SDADC_Channel_6) || \
+ ((CHANNEL) == SDADC_Channel_7) || \
+ ((CHANNEL) == SDADC_Channel_8))
+
+/* Any or all of the 9 channels can be selected for injected conversion */
+#define IS_SDADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F01FF))
+
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief ADC common clock divider.
+ * @note This setting is influenced by the VDDA voltage and other
+ * external conditions, please refer to the datasheet for more
+ * info.<br>
+ * See section 5.3.20 "12-bit ADC characteristics".
+ */
+#if !defined(STM32_ADC_ADCPRE) || defined(__DOXYGEN__)
+#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV2
+#endif
+
+/**
+ * @brief ADC1 driver enable switch.
+ * @details If set to @p TRUE the support for ADC1 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
+#define STM32_ADC_USE_ADC1 FALSE
+#endif
+
+#if !defined(STM32_ADC_USE_SDADC1) || defined(__DOXYGEN__)
+#define STM32_ADC_USE_SDADC1 FALSE
+#endif
+
+#if !defined(STM32_ADC_USE_SDADC2) || defined(__DOXYGEN__)
+#define STM32_ADC_USE_SDADC2 FALSE
+#endif
+
+#if !defined(STM32_ADC_USE_SDADC3) || defined(__DOXYGEN__)
+#define STM32_ADC_USE_SDADC3 FALSE
+#endif
+
+/**
+ * @brief DMA stream used for ADC1 operations.
+ */
+#if !defined(STM32_ADC_ADC1_DMA_STREAM) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#endif
+
+/**
+ * @brief DMA stream used for SDADC1 operations.
+ */
+#if !defined(STM32_ADC_SDADC1_DMA_STREAM) || defined(__DOXYGEN__)
+#define STM32_ADC_SDADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#endif
+
+/**
+ * @brief DMA stream used for SDADC2 operations.
+ */
+#if !defined(STM32_ADC_SDADC2_DMA_STREAM) || defined(__DOXYGEN__)
+#define STM32_ADC_SDADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+#endif
+
+/**
+ * @brief DMA stream used for SDADC3 operations.
+ */
+#if !defined(STM32_ADC_SDADC3_DMA_STREAM) || defined(__DOXYGEN__)
+#define STM32_ADC_SDADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#endif
+
+/**
+ * @brief ADC1 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#endif
+
+/**
+ * @brief SDADC1 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_ADC_SDADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_SDADC1_DMA_PRIORITY 2
+#endif
+
+/**
+ * @brief SDADC2 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_ADC_SDADC2_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_SDADC2_DMA_PRIORITY 2
+#endif
+
+/**
+ * @brief SDADC3 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_ADC_SDADC3_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_SDADC3_DMA_PRIORITY 2
+#endif
+
+/**
+ * @brief ADC interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_IRQ_PRIORITY 5
+#endif
+
+/**
+ * @brief SDADC1 interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_SDADC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_SDADC1_IRQ_PRIORITY 5
+#endif
+
+/**
+ * @brief SDADC2 interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_SDADC2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_SDADC2_IRQ_PRIORITY 5
+#endif
+
+/**
+ * @brief SDADC3 interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_SDADC3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_SDADC3_IRQ_PRIORITY 5
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
+#error "ADC1 not present in the selected device"
+#endif
+
+#if STM32_ADC_USE_ADC2 && !STM32_HAS_ADC2
+#error "ADC2 not present in the selected device"
+#endif
+
+#if STM32_ADC_USE_ADC3 && !STM32_HAS_ADC3
+#error "ADC3 not present in the selected device"
+#endif
+
+#if STM32_ADC_USE_SDADC1 && !STM32_HAS_SDADC1
+#error "SDADC1 not present in the selected device"
+#endif
+
+#if STM32_ADC_USE_SDADC2 && !STM32_HAS_SDADC2
+#error "SDADC2 not present in the selected device"
+#endif
+
+#if STM32_ADC_USE_SDADC3 && !STM32_HAS_SDADC3
+#error "SDADC3 not present in the selected device"
+#endif
+
+#if !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC2 && !STM32_ADC_USE_ADC3
+#error "ADC driver activated but no ADC peripheral assigned"
+#endif
+
+#if STM32_ADC_USE_ADC1 && \
+ !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_MSK)
+#error "invalid DMA stream associated to ADC1"
+#endif
+
+#if STM32_ADC_USE_ADC2 && \
+ !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_MSK)
+#error "invalid DMA stream associated to ADC2"
+#endif
+
+#if STM32_ADC_USE_ADC3 && \
+ !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_MSK)
+#error "invalid DMA stream associated to ADC3"
+#endif
+
+#if STM32_ADC_USE_SDADC1 && \
+ !STM32_DMA_IS_VALID_ID(STM32_ADC_SDADC1_DMA_STREAM, STM32_SDADC1_DMA_MSK)
+#error "invalid DMA stream associated to SDADC1"
+#endif
+
+#if STM32_ADC_USE_SDADC2 && \
+ !STM32_DMA_IS_VALID_ID(STM32_ADC_SDADC2_DMA_STREAM, STM32_SDADC2_DMA_MSK)
+#error "invalid DMA stream associated to SDADC2"
+#endif
+
+#if STM32_ADC_USE_SDADC3 && \
+ !STM32_DMA_IS_VALID_ID(STM32_ADC_SDADC3_DMA_STREAM, STM32_SDADC3_DMA_MSK)
+#error "invalid DMA stream associated to SDADC3"
+#endif
+
+
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief ADC sample data type.
+ */
+typedef uint16_t adcsample_t;
+
+/**
+ * @brief Channels number in a conversion group.
+ */
+typedef uint16_t adc_channels_num_t;
+
+/**
+ * @brief Possible ADC failure causes.
+ * @note Error codes are architecture dependent and should not relied
+ * upon.
+ */
+typedef enum {
+ ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
+ ADC_ERR_OVERFLOW = 1 /**< ADC overflow condition. */
+} adcerror_t;
+
+/**
+ * @brief Type of a structure representing an ADC driver.
+ */
+typedef struct ADCDriver ADCDriver;
+
+/**
+ * @brief ADC notification callback type.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object triggering the
+ * callback
+ * @param[in] buffer pointer to the most recent samples data
+ * @param[in] n number of buffer rows available starting from @p buffer
+ */
+typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
+
+/**
+ * @brief ADC error callback type.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object triggering the
+ * callback
+ * @param[in] err ADC error code
+ */
+typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
+
+/**
+ * @brief Conversion group configuration structure.
+ * @details This implementation-dependent structure describes a conversion
+ * operation.
+ * @note The use of this configuration structure requires knowledge of
+ * STM32 ADC cell registers interface, please refer to the STM32
+ * reference manual for details.
+ */
+typedef struct {
+ /**
+ * @brief Enables the circular buffer mode for the group.
+ */
+ bool_t circular;
+ /**
+ * @brief Number of the analog channels belonging to the conversion group.
+ */
+ adc_channels_num_t num_channels;
+ /**
+ * @brief Callback function associated to the group or @p NULL.
+ */
+ adccallback_t end_cb;
+ /**
+ * @brief Error callback or @p NULL.
+ */
+ adcerrorcallback_t error_cb;
+ /* End of the mandatory fields.*/
+
+ /**
+ * @brief Union of ADC and SDADC config parms. The decision of which struct
+ * union to use is determined by the ADCDriver. If the ADCDriver adc parm
+ * is not NULL, then use the adc struct, otherwise if the ADCDriver sdadc parm
+ * is not NULL, then use the sdadc struct.
+ */
+ union {
+ struct {
+ /**
+ * @brief ADC CR1 register initialization data.
+ * @note All the required bits must be defined into this field except
+ * @p ADC_CR1_SCAN that is enforced inside the driver.
+ */
+ uint32_t cr1;
+ /**
+ * @brief ADC CR2 register initialization data.
+ * @note All the required bits must be defined into this field except
+ * @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are
+ * enforced inside the driver.
+ */
+ uint32_t cr2;
+ /**
+ * @brief ADC SMPR1 register initialization data.
+ * @details In this field must be specified the sample times for channels
+ * 10...18.
+ */
+ uint32_t smpr1;
+ /**
+ * @brief ADC SMPR2 register initialization data.
+ * @details In this field must be specified the sample times for channels
+ * 0...9.
+ */
+ uint32_t smpr2;
+ /**
+ * @brief ADC SQR1 register initialization data.
+ * @details Conversion group sequence 13...16 + sequence length.
+ */
+ uint32_t sqr1;
+ /**
+ * @brief ADC SQR2 register initialization data.
+ * @details Conversion group sequence 7...12.
+ */
+ uint32_t sqr2;
+ /**
+ * @brief ADC SQR3 register initialization data.
+ * @details Conversion group sequence 1...6.
+ */
+ uint32_t sqr3;
+ } adc;
+ struct {
+ /**
+ * @brief SDADC CR1 register initialization data.
+ * @note All the required bits must be defined into this field
+ */
+ uint32_t cr1;
+ /**
+ * @brief SDADC CR2 register initialization data.
+ * @note All the required bits must be defined into this field except
+ * @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are
+ * enforced inside the driver.
+ */
+ uint32_t cr2;
+ /**
+ * @brief SDADC JCHGR register initialization data.
+ * @details Bitfield indicating whether channel i is part of the injected group.
+ * 0 <= i <= 8. Highest channel, (8), is converted first
+ */
+ uint32_t jchgr;
+ /**
+ * @brief SDADC CONF0R register initialization data.
+ * @details In this field are the parameters for configuration 0
+ */
+ uint32_t conf0r;
+ /**
+ * @brief SDADC CONF1R register initialization data.
+ * @details In this field are the parameters for configuration 1
+ */
+ uint32_t conf1r;
+ /**
+ * @brief SDADC CONF2R register initialization data.
+ * @details In this field are the parameters for configuration 2
+ */
+ uint32_t conf2r;
+ /**
+ * @brief SDADC CONFCH1R register initialization data.
+ * @details In this field channels 0-7 are assigned to a configuration.
+ */
+ uint32_t confchr1;
+ /**
+ * @brief SDADC CONFCH2R register initialization data.
+ * @details In this field channel 8 is assigned to a configuration.
+ * @details In this field are the parameters for configuration 2
+ */
+ uint32_t confchr2;
+
+ } sdadc;
+ } ll; /* union */
+} ADCConversionGroup;
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+ uint32_t dummy;
+} ADCConfig;
+
+/**
+ * @brief Structure representing an ADC driver.
+ */
+struct ADCDriver {
+ /**
+ * @brief Driver state.
+ */
+ adcstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const ADCConfig *config;
+ /**
+ * @brief Current samples buffer pointer or @p NULL.
+ */
+ adcsample_t *samples;
+ /**
+ * @brief Current samples buffer depth or @p 0.
+ */
+ size_t depth;
+ /**
+ * @brief Current conversion group pointer or @p NULL.
+ */
+ const ADCConversionGroup *grpp;
+
+#if ADC_USE_WAIT || defined(__DOXYGEN__)
+ /**
+ * @brief Waiting thread.
+ */
+ Thread *thread;
+#endif
+#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+#if CH_USE_MUTEXES || defined(__DOXYGEN__)
+ /**
+ * @brief Mutex protecting the peripheral.
+ */
+ Mutex mutex;
+#elif CH_USE_SEMAPHORES
+ Semaphore semaphore;
+#endif
+#endif /* ADC_USE_MUTUAL_EXCLUSION */
+#if defined(ADC_DRIVER_EXT_FIELDS)
+ ADC_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the ADCx registers block.
+ */
+ ADC_TypeDef *adc;
+
+ /**
+ * @brief Pointer to the SDADCx registers block.
+ */
+ SDADC_TypeDef *sdadc;
+
+ /**
+ * @brief Pointer to associated DMA channel.
+ */
+ const stm32_dma_stream_t *dmastp;
+ /**
+ * @brief DMA mode bit mask.
+ */
+ uint32_t dmamode;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name Sequences building helper macros
+ * @{
+ */
+/**
+ * @brief Number of channels in a conversion sequence.
+ */
+#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20)
+
+#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */
+#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */
+#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */
+#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */
+#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */
+#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */
+
+#define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */
+#define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */
+#define ADC_SQR2_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */
+#define ADC_SQR2_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/
+#define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/
+#define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/
+
+#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/
+#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/
+#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/
+#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/
+/** @} */
+
+/**
+ * @name Sampling rate settings helper macros
+ * @{
+ */
+#define ADC_SMPR2_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */
+#define ADC_SMPR2_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */
+#define ADC_SMPR2_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */
+#define ADC_SMPR2_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */
+#define ADC_SMPR2_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */
+#define ADC_SMPR2_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */
+#define ADC_SMPR2_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */
+#define ADC_SMPR2_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */
+#define ADC_SMPR2_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */
+#define ADC_SMPR2_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */
+
+#define ADC_SMPR1_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */
+#define ADC_SMPR1_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */
+#define ADC_SMPR1_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */
+#define ADC_SMPR1_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */
+#define ADC_SMPR1_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */
+#define ADC_SMPR1_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */
+#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor
+ sampling time. */
+#define ADC_SMPR1_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference
+ sampling time. */
+#define ADC_SMPR1_SMP_VBAT(n) ((n) << 24) /**< @brief VBAT sampling time. */
+/** @} */
+
+/**
+ * @name Channel config settings helper macros
+ * @{
+ */
+#define sdadcSTM32Channel1TO7Config(SDADC_Channel, SDADC_Conf) ((uint32_t) (SDADC_Conf << (( SDADC_Channel >> 16) << 2)))
+#define sdadcSTM32Channel8Config(SDADC_Channel, SDADC_Conf) ((uint32_t) SDADC_CONF)
+
+#define sdadcSTM32ChannelSelect(SDADC_Channel) ((uint32_t) (SDADC_Channel & 0xffff0000))
+
+/** @} */
+
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
+extern ADCDriver ADCD1;
+#endif
+
+#if STM32_ADC_USE_ADC2 && !defined(__DOXYGEN__)
+extern ADCDriver ADCD2;
+#endif
+
+#if STM32_ADC_USE_ADC3 && !defined(__DOXYGEN__)
+extern ADCDriver ADCD3;
+#endif
+
+#if STM32_ADC_USE_SDADC1 && !defined(__DOXYGEN__)
+extern ADCDriver SDADCD1;
+#endif
+
+#if STM32_ADC_USE_SDADC2 && !defined(__DOXYGEN__)
+extern ADCDriver SDADCD2;
+#endif
+
+#if STM32_ADC_USE_SDADC3 && !defined(__DOXYGEN__)
+extern ADCDriver SDADCD3;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void adc_lld_init(void);
+ void adc_lld_start(ADCDriver *adcp);
+ void adc_lld_stop(ADCDriver *adcp);
+ void adc_lld_start_conversion(ADCDriver *adcp);
+ void adc_lld_stop_conversion(ADCDriver *adcp);
+ void adcSTM32EnableTSVREFE(void);
+ void adcSTM32DisableTSVREFE(void);
+ void adcSTM32EnableVBATE(void);
+ void adcSTM32DisableVBATE(void);
+ void sdadcSTM32SetInitializationMode(ADCDriver* adcdp, bool_t enterInitMode);
+ void sdadcSTM32VREFSelect(SDADC_VREF_SEL svs);
+ void sdadcSTM32Calibrate(ADCDriver* adcdp, SDADC_NUM_CALIB_SEQ numCalibSequences,
+ ADCConversionGroup* grpp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_ADC */
+
+#endif /* _ADC_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/STM32F37x/platform.mk b/os/hal/platforms/STM32F37x/platform.mk index 9475796a0..325af13b1 100644 --- a/os/hal/platforms/STM32F37x/platform.mk +++ b/os/hal/platforms/STM32F37x/platform.mk @@ -1,6 +1,7 @@ # List of all the STM32F37x platform files.
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F37x/stm32_dma.c \
${CHIBIOS}/os/hal/platforms/STM32F37x/hal_lld.c \
+ ${CHIBIOS}/os/hal/platforms/STM32F37x/adc_lld.c \
${CHIBIOS}/os/hal/platforms/STM32F37x/ext_lld_isr.c \
${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \
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