Now STM32L1xx uses the common DMAv1 driver.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8168 35acf78f-673a-0410-8e92-d51de3d6d3f4

4 files changed, 54 insertions, 743 deletions

diff --git a/os/hal/ports/STM32/STM32L1xx/platform.mk b/os/hal/ports/STM32/STM32L1xx/platform.mk
index 673edb3b0..88969b8c5 100644
--- a/os/hal/ports/STM32/STM32L1xx/platform.mk
+++ b/os/hal/ports/STM32/STM32L1xx/platform.mk
@@ -3,8 +3,8 @@ ifeq ($(USE_SMART_BUILD),yes)
 HALCONF := $(strip $(shell cat halconf.h | egrep -e "define"))

 

 PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \

-               $(CHIBIOS)/os/hal/ports/STM32/STM32L1xx/stm32_dma.c \

                $(CHIBIOS)/os/hal/ports/STM32/STM32L1xx/hal_lld.c \

+               $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c

 ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)

 PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32L1xx/adc_lld.c

@@ -48,12 +48,12 @@ PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/usb_lld.c
 endif

 else

 PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \

-               $(CHIBIOS)/os/hal/ports/STM32/STM32L1xx/stm32_dma.c \

                $(CHIBIOS)/os/hal/ports/STM32/STM32L1xx/hal_lld.c \

                $(CHIBIOS)/os/hal/ports/STM32/STM32L1xx/adc_lld.c \

                $(CHIBIOS)/os/hal/ports/STM32/STM32L1xx/ext_lld_isr.c \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c \

+               $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.c \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/spi_lld.c \

@@ -72,6 +72,7 @@ PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
                $(CHIBIOS)/os/hal/ports/STM32/STM32L1xx \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1 \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1 \

+               $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1 \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2 \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1 \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2 \

diff --git a/os/hal/ports/STM32/STM32L1xx/stm32_dma.c b/os/hal/ports/STM32/STM32L1xx/stm32_dma.c
deleted file mode 100644
index 76dc5c6d0..000000000
--- a/os/hal/ports/STM32/STM32L1xx/stm32_dma.c
+++ /dev/null
@@ -1,343 +0,0 @@
-/*

-    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio

-

-    Licensed under the Apache License, Version 2.0 (the "License");

-    you may not use this file except in compliance with the License.

-    You may obtain a copy of the License at

-

-        http://www.apache.org/licenses/LICENSE-2.0

-

-    Unless required by applicable law or agreed to in writing, software

-    distributed under the License is distributed on an "AS IS" BASIS,

-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

-    See the License for the specific language governing permissions and

-    limitations under the License.

-*/

-

-/**

- * @file    STM32L1xx/stm32_dma.c

- * @brief   DMA helper driver code.

- *

- * @addtogroup STM32L1xx_DMA

- * @details DMA sharing helper driver. In the STM32 the DMA streams are a

- *          shared resource, this driver allows to allocate and free DMA

- *          streams at runtime in order to allow all the other device

- *          drivers to coordinate the access to the resource.

- * @note    The DMA ISR handlers are all declared into this module because

- *          sharing, the various device drivers can associate a callback to

- *          ISRs when allocating streams.

- * @{

- */

-

-#include "hal.h"

-

-/* The following macro is only defined if some driver requiring DMA services

-   has been enabled.*/

-#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)

-

-/*===========================================================================*/

-/* Driver local definitions.                                                 */

-/*===========================================================================*/

-

-/**

- * @brief   Mask of the DMA1 streams in @p dma_streams_mask.

- */

-#define STM32_DMA1_STREAMS_MASK     0x0000007F

-

-/**

- * @brief   Mask of the DMA2 streams in @p dma_streams_mask.

- */

-#define STM32_DMA2_STREAMS_MASK     0x00000F80

-

-/**

- * @brief   Post-reset value of the stream CCR register.

- */

-#define STM32_DMA_CCR_RESET_VALUE   0x00000000

-

-/*===========================================================================*/

-/* Driver exported variables.                                                */

-/*===========================================================================*/

-

-/**

- * @brief   DMA streams descriptors.

- * @details This table keeps the association between an unique stream

- *          identifier and the involved physical registers.

- * @note    Don't use this array directly, use the appropriate wrapper macros

- *          instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc.

- */

-const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {

-  {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn},

-  {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_IRQn},

-  {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel3_IRQn},

-  {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_IRQn},

-  {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel5_IRQn},

-  {DMA1_Channel6, &DMA1->IFCR, 20, 5, DMA1_Channel6_IRQn},

-  {DMA1_Channel7, &DMA1->IFCR, 24, 6, DMA1_Channel7_IRQn}

-};

-

-/*===========================================================================*/

-/* Driver local variables and types.                                         */

-/*===========================================================================*/

-

-/**

- * @brief   DMA ISR redirector type.

- */

-typedef struct {

-  stm32_dmaisr_t        dma_func;       /**< @brief DMA callback function.  */

-  void                  *dma_param;     /**< @brief DMA callback parameter. */

-} dma_isr_redir_t;

-

-/**

- * @brief   Mask of the allocated streams.

- */

-static uint32_t dma_streams_mask;

-

-/**

- * @brief   DMA IRQ redirectors.

- */

-static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];

-

-/*===========================================================================*/

-/* Driver local functions.                                                   */

-/*===========================================================================*/

-

-/*===========================================================================*/

-/* Driver interrupt handlers.                                                */

-/*===========================================================================*/

-

-/**

- * @brief   DMA1 stream 1 shared interrupt handler.

- *

- * @isr

- */

-OSAL_IRQ_HANDLER(Vector6C) {

-  uint32_t flags;

-

-  OSAL_IRQ_PROLOGUE();

-

-  flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;

-  DMA1->IFCR = flags << 0;

-  if (dma_isr_redir[0].dma_func)

-    dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);

-

-  OSAL_IRQ_EPILOGUE();

-}

-

-/**

- * @brief   DMA1 stream 2 shared interrupt handler.

- *

- * @isr

- */

-OSAL_IRQ_HANDLER(Vector70) {

-  uint32_t flags;

-

-  OSAL_IRQ_PROLOGUE();

-

-  flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;

-  DMA1->IFCR = flags << 4;

-  if (dma_isr_redir[1].dma_func)

-    dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);

-

-  OSAL_IRQ_EPILOGUE();

-}

-

-/**

- * @brief   DMA1 stream 3 shared interrupt handler.

- *

- * @isr

- */

-OSAL_IRQ_HANDLER(Vector74) {

-  uint32_t flags;

-

-  OSAL_IRQ_PROLOGUE();

-

-  flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;

-  DMA1->IFCR = flags << 8;

-  if (dma_isr_redir[2].dma_func)

-    dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);

-

-  OSAL_IRQ_EPILOGUE();

-}

-

-/**

- * @brief   DMA1 stream 4 shared interrupt handler.

- *

- * @isr

- */

-OSAL_IRQ_HANDLER(Vector78) {

-  uint32_t flags;

-

-  OSAL_IRQ_PROLOGUE();

-

-  flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;

-  DMA1->IFCR = flags << 12;

-  if (dma_isr_redir[3].dma_func)

-    dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);

-

-  OSAL_IRQ_EPILOGUE();

-}

-

-/**

- * @brief   DMA1 stream 5 shared interrupt handler.

- *

- * @isr

- */

-OSAL_IRQ_HANDLER(Vector7C) {

-  uint32_t flags;

-

-  OSAL_IRQ_PROLOGUE();

-

-  flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;

-  DMA1->IFCR = flags << 16;

-  if (dma_isr_redir[4].dma_func)

-    dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);

-

-  OSAL_IRQ_EPILOGUE();

-}

-

-/**

- * @brief   DMA1 stream 6 shared interrupt handler.

- *

- * @isr

- */

-OSAL_IRQ_HANDLER(Vector80) {

-  uint32_t flags;

-

-  OSAL_IRQ_PROLOGUE();

-

-  flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;

-  DMA1->IFCR = flags << 20;

-  if (dma_isr_redir[5].dma_func)

-    dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);

-

-  OSAL_IRQ_EPILOGUE();

-}

-

-/**

- * @brief   DMA1 stream 7 shared interrupt handler.

- *

- * @isr

- */

-OSAL_IRQ_HANDLER(Vector84) {

-  uint32_t flags;

-

-  OSAL_IRQ_PROLOGUE();

-

-  flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;

-  DMA1->IFCR = flags << 24;

-  if (dma_isr_redir[6].dma_func)

-    dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);

-

-  OSAL_IRQ_EPILOGUE();

-}

-

-/*===========================================================================*/

-/* Driver exported functions.                                                */

-/*===========================================================================*/

-

-/**

- * @brief   STM32 DMA helper initialization.

- *

- * @init

- */

-void dmaInit(void) {

-  int i;

-

-  dma_streams_mask = 0;

-  for (i = 0; i < STM32_DMA_STREAMS; i++) {

-    _stm32_dma_streams[i].channel->CCR = 0;

-    dma_isr_redir[i].dma_func = NULL;

-  }

-  DMA1->IFCR = 0xFFFFFFFF;

-}

-

-/**

- * @brief   Allocates a DMA stream.

- * @details The stream is allocated and, if required, the DMA clock enabled.

- *          The function also enables the IRQ vector associated to the stream

- *          and initializes its priority.

- * @pre     The stream must not be already in use or an error is returned.

- * @post    The stream is allocated and the default ISR handler redirected

- *          to the specified function.

- * @post    The stream ISR vector is enabled and its priority configured.

- * @post    The stream must be freed using @p dmaStreamRelease() before it can

- *          be reused with another peripheral.

- * @post    The stream is in its post-reset state.

- * @note    This function can be invoked in both ISR or thread context.

- *

- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

- * @param[in] priority  IRQ priority mask for the DMA stream

- * @param[in] func      handling function pointer, can be @p NULL

- * @param[in] param     a parameter to be passed to the handling function

- * @return              The operation status.

- * @retval FALSE        no error, stream taken.

- * @retval TRUE         error, stream already taken.

- *

- * @special

- */

-bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,

-                       uint32_t priority,

-                       stm32_dmaisr_t func,

-                       void *param) {

-

-  osalDbgCheck(dmastp != NULL);

-

-  /* Checks if the stream is already taken.*/

-  if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)

-    return TRUE;

-

-  /* Marks the stream as allocated.*/

-  dma_isr_redir[dmastp->selfindex].dma_func  = func;

-  dma_isr_redir[dmastp->selfindex].dma_param = param;

-  dma_streams_mask |= (1 << dmastp->selfindex);

-

-  /* Enabling DMA clocks required by the current streams set.*/

-  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)

-    rccEnableDMA1(FALSE);

-

-  /* Putting the stream in a safe state.*/

-  dmaStreamDisable(dmastp);

-  dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE;

-

-  /* Enables the associated IRQ vector if a callback is defined.*/

-  if (func != NULL)

-    nvicEnableVector(dmastp->vector, priority);

-

-  return FALSE;

-}

-

-/**

- * @brief   Releases a DMA stream.

- * @details The stream is freed and, if required, the DMA clock disabled.

- *          Trying to release a unallocated stream is an illegal operation

- *          and is trapped if assertions are enabled.

- * @pre     The stream must have been allocated using @p dmaStreamAllocate().

- * @post    The stream is again available.

- * @note    This function can be invoked in both ISR or thread context.

- *

- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

- *

- * @special

- */

-void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {

-

-  osalDbgCheck(dmastp != NULL);

-

-  /* Check if the streams is not taken.*/

-  osalDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,

-                "not allocated");

-

-  /* Disables the associated IRQ vector.*/

-  nvicDisableVector(dmastp->vector);

-

-  /* Marks the stream as not allocated.*/

-  dma_streams_mask &= ~(1 << dmastp->selfindex);

-

-  /* Shutting down clocks that are no more required, if any.*/

-  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)

-    rccDisableDMA1(FALSE);

-}

-

-#endif /* STM32_DMA_REQUIRED */

-

-/** @} */

diff --git a/os/hal/ports/STM32/STM32L1xx/stm32_dma.h b/os/hal/ports/STM32/STM32L1xx/stm32_dma.h
deleted file mode 100644
index e9877ea89..000000000
--- a/os/hal/ports/STM32/STM32L1xx/stm32_dma.h
+++ /dev/null
@@ -1,396 +0,0 @@
-/*

-    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio

-

-    Licensed under the Apache License, Version 2.0 (the "License");

-    you may not use this file except in compliance with the License.

-    You may obtain a copy of the License at

-

-        http://www.apache.org/licenses/LICENSE-2.0

-

-    Unless required by applicable law or agreed to in writing, software

-    distributed under the License is distributed on an "AS IS" BASIS,

-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

-    See the License for the specific language governing permissions and

-    limitations under the License.

-*/

-

-/**

- * @file    STM32L1xx/stm32_dma.h

- * @brief   DMA helper driver header.

- * @note    This file requires definitions from the ST header file stm32l1xx.h.

- * @note    This driver uses the new naming convention used for the STM32F2xx

- *          so the "DMA channels" are referred as "DMA streams".

- *

- * @addtogroup STM32L1xx_DMA

- * @{

- */

-

-#ifndef _STM32_DMA_H_

-#define _STM32_DMA_H_

-

-/*===========================================================================*/

-/* Driver constants.                                                         */

-/*===========================================================================*/

-

-/**

- * @brief   Total number of DMA streams.

- * @note    This is the total number of streams among all the DMA units.

- */

-#define STM32_DMA_STREAMS           7

-

-/**

- * @brief   Mask of the ISR bits passed to the DMA callback functions.

- */

-#define STM32_DMA_ISR_MASK          0x0F

-

-/**

- * @brief   Returns the channel associated to the specified stream.

- *

- * @param[in] n         the stream number (0...STM32_DMA_STREAMS-1)

- * @param[in] c         a stream/channel association word, one channel per

- *                      nibble, not associated channels must be set to 0xF

- * @return              Always zero, in this platform there is no dynamic

- *                      association between streams and channels.

- */

-#define STM32_DMA_GETCHANNEL(n, c)  0

-

-/**

- * @brief   Checks if a DMA priority is within the valid range.

- * @param[in] prio      DMA priority

- *

- * @retval              The check result.

- * @retval FALSE        invalid DMA priority.

- * @retval TRUE         correct DMA priority.

- */

-#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3))

-

-/**

- * @brief   Returns an unique numeric identifier for a DMA stream.

- *

- * @param[in] dma       the DMA unit number

- * @param[in] stream    the stream number

- * @return              An unique numeric stream identifier.

- */

-#define STM32_DMA_STREAM_ID(dma, stream) ((stream) - 1)

-

-/**

- * @brief   Returns a DMA stream identifier mask.

- *

- *

- * @param[in] dma       the DMA unit number

- * @param[in] stream    the stream number

- * @return              A DMA stream identifier mask.

- */

-#define STM32_DMA_STREAM_ID_MSK(dma, stream)                                \

-  (1 << STM32_DMA_STREAM_ID(dma, stream))

-

-/**

- * @brief   Checks if a DMA stream unique identifier belongs to a mask.

- * @param[in] id        the stream numeric identifier

- * @param[in] mask      the stream numeric identifiers mask

- *

- * @retval              The check result.

- * @retval FALSE        id does not belong to the mask.

- * @retval TRUE         id belongs to the mask.

- */

-#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask)))

-

-/**

- * @name    DMA streams identifiers

- * @{

- */

-/**

- * @brief   Returns a pointer to a stm32_dma_stream_t structure.

- *

- * @param[in] id        the stream numeric identifier

- * @return              A pointer to the stm32_dma_stream_t constant structure

- *                      associated to the DMA stream.

- */

-#define STM32_DMA_STREAM(id)        (&_stm32_dma_streams[id])

-

-#define STM32_DMA1_STREAM1          STM32_DMA_STREAM(0)

-#define STM32_DMA1_STREAM2          STM32_DMA_STREAM(1)

-#define STM32_DMA1_STREAM3          STM32_DMA_STREAM(2)

-#define STM32_DMA1_STREAM4          STM32_DMA_STREAM(3)

-#define STM32_DMA1_STREAM5          STM32_DMA_STREAM(4)

-#define STM32_DMA1_STREAM6          STM32_DMA_STREAM(5)

-#define STM32_DMA1_STREAM7          STM32_DMA_STREAM(6)

-/** @} */

-

-/**

- * @name    CR register constants common to all DMA types

- * @{

- */

-#define STM32_DMA_CR_EN             DMA_CCR_EN

-#define STM32_DMA_CR_TEIE           DMA_CCR_TEIE

-#define STM32_DMA_CR_HTIE           DMA_CCR_HTIE

-#define STM32_DMA_CR_TCIE           DMA_CCR_TCIE

-#define STM32_DMA_CR_DIR_MASK       (DMA_CCR_DIR | DMA_CCR_MEM2MEM)

-#define STM32_DMA_CR_DIR_P2M        0

-#define STM32_DMA_CR_DIR_M2P        DMA_CCR_DIR

-#define STM32_DMA_CR_DIR_M2M        DMA_CCR_MEM2MEM

-#define STM32_DMA_CR_CIRC           DMA_CCR_CIRC

-#define STM32_DMA_CR_PINC           DMA_CCR_PINC

-#define STM32_DMA_CR_MINC           DMA_CCR_MINC

-#define STM32_DMA_CR_PSIZE_MASK     DMA_CCR_PSIZE

-#define STM32_DMA_CR_PSIZE_BYTE     0

-#define STM32_DMA_CR_PSIZE_HWORD    DMA_CCR_PSIZE_0

-#define STM32_DMA_CR_PSIZE_WORD     DMA_CCR_PSIZE_1

-#define STM32_DMA_CR_MSIZE_MASK     DMA_CCR_MSIZE

-#define STM32_DMA_CR_MSIZE_BYTE     0

-#define STM32_DMA_CR_MSIZE_HWORD    DMA_CCR_MSIZE_0

-#define STM32_DMA_CR_MSIZE_WORD     DMA_CCR_MSIZE_1

-#define STM32_DMA_CR_SIZE_MASK      (STM32_DMA_CR_PSIZE_MASK |              \

-                                     STM32_DMA_CR_MSIZE_MASK)

-#define STM32_DMA_CR_PL_MASK        DMA_CCR_PL

-#define STM32_DMA_CR_PL(n)          ((n) << 12)

-/** @} */

-

-/**

- * @name    CR register constants only found in enhanced DMA

- * @{

- */

-#define STM32_DMA_CR_DMEIE          0   /**< @brief Ignored by normal DMA.  */

-#define STM32_DMA_CR_CHSEL_MASK     0   /**< @brief Ignored by normal DMA.  */

-#define STM32_DMA_CR_CHSEL(n)       0   /**< @brief Ignored by normal DMA.  */

-/** @} */

-

-/**

- * @name    Status flags passed to the ISR callbacks

- * @{

- */

-#define STM32_DMA_ISR_FEIF          0

-#define STM32_DMA_ISR_DMEIF         0

-#define STM32_DMA_ISR_TEIF          DMA_ISR_TEIF1

-#define STM32_DMA_ISR_HTIF          DMA_ISR_HTIF1

-#define STM32_DMA_ISR_TCIF          DMA_ISR_TCIF1

-/** @} */

-

-/*===========================================================================*/

-/* Driver pre-compile time settings.                                         */

-/*===========================================================================*/

-

-/*===========================================================================*/

-/* Derived constants and error checks.                                       */

-/*===========================================================================*/

-

-/*===========================================================================*/

-/* Driver data structures and types.                                         */

-/*===========================================================================*/

-

-/**

- * @brief   STM32 DMA stream descriptor structure.

- */

-typedef struct {

-  DMA_Channel_TypeDef   *channel;       /**< @brief Associated DMA channel. */

-  volatile uint32_t     *ifcr;          /**< @brief Associated IFCR reg.    */

-  uint8_t               ishift;         /**< @brief Bits offset in xIFCR

-                                             register.                      */

-  uint8_t               selfindex;      /**< @brief Index to self in array. */

-  uint8_t               vector;         /**< @brief Associated IRQ vector.  */

-} stm32_dma_stream_t;

-

-/**

- * @brief   STM32 DMA ISR function type.

- *

- * @param[in] p         parameter for the registered function

- * @param[in] flags     pre-shifted content of the ISR register, the bits

- *                      are aligned to bit zero

- */

-typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);

-

-/*===========================================================================*/

-/* Driver macros.                                                            */

-/*===========================================================================*/

-

-/**

- * @name    Macro Functions

- * @{

- */

-/**

- * @brief   Associates a peripheral data register to a DMA stream.

- * @note    This function can be invoked in both ISR or thread context.

- * @pre     The stream must have been allocated using @p dmaStreamAllocate().

- * @post    After use the stream can be released using @p dmaStreamRelease().

- *

- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

- * @param[in] addr      value to be written in the CPAR register

- *

- * @special

- */

-#define dmaStreamSetPeripheral(dmastp, addr) {                              \

-  (dmastp)->channel->CPAR  = (uint32_t)(addr);                              \

-}

-

-/**

- * @brief   Associates a memory destination to a DMA stream.

- * @note    This function can be invoked in both ISR or thread context.

- * @pre     The stream must have been allocated using @p dmaStreamAllocate().

- * @post    After use the stream can be released using @p dmaStreamRelease().

- *

- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

- * @param[in] addr      value to be written in the CMAR register

- *

- * @special

- */

-#define dmaStreamSetMemory0(dmastp, addr) {                                 \

-  (dmastp)->channel->CMAR  = (uint32_t)(addr);                              \

-}

-

-/**

- * @brief   Sets the number of transfers to be performed.

- * @note    This function can be invoked in both ISR or thread context.

- * @pre     The stream must have been allocated using @p dmaStreamAllocate().

- * @post    After use the stream can be released using @p dmaStreamRelease().

- *

- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

- * @param[in] size      value to be written in the CNDTR register

- *

- * @special

- */

-#define dmaStreamSetTransactionSize(dmastp, size) {                         \

-  (dmastp)->channel->CNDTR  = (uint32_t)(size);                             \

-}

-

-/**

- * @brief   Returns the number of transfers to be performed.

- * @note    This function can be invoked in both ISR or thread context.

- * @pre     The stream must have been allocated using @p dmaStreamAllocate().

- * @post    After use the stream can be released using @p dmaStreamRelease().

- *

- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

- * @return              The number of transfers to be performed.

- *

- * @special

- */

-#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR))

-

-/**

- * @brief   Programs the stream mode settings.

- * @note    This function can be invoked in both ISR or thread context.

- * @pre     The stream must have been allocated using @p dmaStreamAllocate().

- * @post    After use the stream can be released using @p dmaStreamRelease().

- *

- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

- * @param[in] mode      value to be written in the CCR register

- *

- * @special

- */

-#define dmaStreamSetMode(dmastp, mode) {                                    \

-  (dmastp)->channel->CCR  = (uint32_t)(mode);                               \

-}

-

-/**

- * @brief   DMA stream enable.

- * @note    This function can be invoked in both ISR or thread context.

- * @pre     The stream must have been allocated using @p dmaStreamAllocate().

- * @post    After use the stream can be released using @p dmaStreamRelease().

- *

- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

- *

- * @special

- */

-#define dmaStreamEnable(dmastp) {                                           \

-  (dmastp)->channel->CCR |= STM32_DMA_CR_EN;                                \

-}

-

-/**

- * @brief   DMA stream disable.

- * @details The function disables the specified stream and then clears any

- *          pending interrupt.

- * @note    This function can be invoked in both ISR or thread context.

- * @note    Interrupts enabling flags are set to zero after this call, see

- *          bug 3607518.

- * @pre     The stream must have been allocated using @p dmaStreamAllocate().

- * @post    After use the stream can be released using @p dmaStreamRelease().

- *

- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

- *

- * @special

- */

-#define dmaStreamDisable(dmastp) {                                          \

-  (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE |       \

-                              STM32_DMA_CR_TEIE | STM32_DMA_CR_EN);         \

-  dmaStreamClearInterrupt(dmastp);                                          \

-}

-

-/**

- * @brief   DMA stream interrupt sources clear.

- * @note    This function can be invoked in both ISR or thread context.

- * @pre     The stream must have been allocated using @p dmaStreamAllocate().

- * @post    After use the stream can be released using @p dmaStreamRelease().

- *

- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

- *

- * @special

- */

-#define dmaStreamClearInterrupt(dmastp) {                                   \

-  *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift;                 \

-}

-

-/**

- * @brief   Starts a memory to memory operation using the specified stream.

- * @note    The default transfer data mode is "byte to byte" but it can be

- *          changed by specifying extra options in the @p mode parameter.

- * @pre     The stream must have been allocated using @p dmaStreamAllocate().

- * @post    After use the stream can be released using @p dmaStreamRelease().

- *

- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

- * @param[in] mode      value to be written in the CCR register, this value

- *                      is implicitly ORed with:

- *                      - @p STM32_DMA_CR_MINC

- *                      - @p STM32_DMA_CR_PINC

- *                      - @p STM32_DMA_CR_DIR_M2M

- *                      - @p STM32_DMA_CR_EN

- *                      .

- * @param[in] src       source address

- * @param[in] dst       destination address

- * @param[in] n         number of data units to copy

- */

-#define dmaStartMemCopy(dmastp, mode, src, dst, n) {                        \

-  dmaStreamSetPeripheral(dmastp, src);                                      \

-  dmaStreamSetMemory0(dmastp, dst);                                         \

-  dmaStreamSetTransactionSize(dmastp, n);                                   \

-  dmaStreamSetMode(dmastp, (mode) |                                         \

-                           STM32_DMA_CR_MINC | STM32_DMA_CR_PINC |          \

-                           STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN);         \

-}

-

-/**

- * @brief   Polled wait for DMA transfer end.

- * @pre     The stream must have been allocated using @p dmaStreamAllocate().

- * @post    After use the stream can be released using @p dmaStreamRelease().

- *

- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

- */

-#define dmaWaitCompletion(dmastp) {                                         \

-  while ((dmastp)->channel->CNDTR > 0)                                      \

-    ;                                                                       \

-  dmaStreamDisable(dmastp);                                                 \

-}

-/** @} */

-

-/*===========================================================================*/

-/* External declarations.                                                    */

-/*===========================================================================*/

-

-#if !defined(__DOXYGEN__)

-extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];

-#endif

-

-#ifdef __cplusplus

-extern "C" {

-#endif

-  void dmaInit(void);

-  bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,

-                         uint32_t priority,

-                         stm32_dmaisr_t func,

-                         void *param);

-  void dmaStreamRelease(const stm32_dma_stream_t *dmastp);

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* _STM32_DMA_H_ */

-

-/** @} */

diff --git a/os/hal/ports/STM32/STM32L1xx/stm32_registry.h b/os/hal/ports/STM32/STM32L1xx/stm32_registry.h
index 49e0e3ece..34699084d 100644
--- a/os/hal/ports/STM32/STM32L1xx/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32L1xx/stm32_registry.h
@@ -83,6 +83,28 @@
 #define STM32_HAS_DMA1                      TRUE

 #define STM32_HAS_DMA2                      FALSE

 

+/* DMA attributes.*/

+#define STM32_ADVANCED_DMA                  FALSE

+

+#define STM32_DMA_SUPPORTS_CSELR            FALSE

+#define STM32_DMA1_NUM_CHANNELS             7

+#define STM32_DMA1_CH1_HANDLER              Vector6C

+#define STM32_DMA1_CH2_HANDLER              Vector70

+#define STM32_DMA1_CH3_HANDLER              Vector74

+#define STM32_DMA1_CH4_HANDLER              Vector78

+#define STM32_DMA1_CH5_HANDLER              Vector7C

+#define STM32_DMA1_CH6_HANDLER              Vector80

+#define STM32_DMA1_CH7_HANDLER              Vector84

+#define STM32_DMA1_CH1_NUMBER               11

+#define STM32_DMA1_CH2_NUMBER               12

+#define STM32_DMA1_CH3_NUMBER               13

+#define STM32_DMA1_CH4_NUMBER               14

+#define STM32_DMA1_CH5_NUMBER               15

+#define STM32_DMA1_CH6_NUMBER               16

+#define STM32_DMA1_CH7_NUMBER               17

+

+#define STM32_DMA2_NUM_CHANNELS             0

+

 /* ETH attributes.*/

 #define STM32_HAS_ETH                       FALSE

 

@@ -266,8 +288,35 @@
 

 /* DMA attributes.*/

 #define STM32_ADVANCED_DMA                  FALSE

-#define STM32_HAS_DMA1                      TRUE

-#define STM32_HAS_DMA2                      TRUE

+

+#define STM32_DMA_SUPPORTS_CSELR            FALSE

+#define STM32_DMA1_NUM_CHANNELS             7

+#define STM32_DMA1_CH1_HANDLER              Vector6C

+#define STM32_DMA1_CH2_HANDLER              Vector70

+#define STM32_DMA1_CH3_HANDLER              Vector74

+#define STM32_DMA1_CH4_HANDLER              Vector78

+#define STM32_DMA1_CH5_HANDLER              Vector7C

+#define STM32_DMA1_CH6_HANDLER              Vector80

+#define STM32_DMA1_CH7_HANDLER              Vector84

+#define STM32_DMA1_CH1_NUMBER               11

+#define STM32_DMA1_CH2_NUMBER               12

+#define STM32_DMA1_CH1_NUMBER               13

+#define STM32_DMA1_CH1_NUMBER               14

+#define STM32_DMA1_CH5_NUMBER               15

+#define STM32_DMA1_CH6_NUMBER               16

+#define STM32_DMA1_CH7_NUMBER               17

+

+#define STM32_DMA2_NUM_CHANNELS             5

+#define STM32_DMA2_CH1_HANDLER              Vector108

+#define STM32_DMA2_CH2_HANDLER              Vector10C

+#define STM32_DMA2_CH3_HANDLER              Vector110

+#define STM32_DMA2_CH4_HANDLER              Vector114

+#define STM32_DMA2_CH5_HANDLER              Vector118

+#define STM32_DMA2_CH1_NUMBER               50

+#define STM32_DMA2_CH2_NUMBER               51

+#define STM32_DMA2_CH1_NUMBER               52

+#define STM32_DMA2_CH1_NUMBER               53

+#define STM32_DMA2_CH5_NUMBER               54

 

 /* ETH attributes.*/

 #define STM32_HAS_ETH                       FALSE