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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-03-14 15:25:03 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-03-14 15:25:03 +0000 |
| commit | 3133defc42d84cc8d03ed270a9407578dae54ad6 (patch) | |
| tree | 5e419777eb5ce53a0a22e96f786a0fb3fa355580 /os | |
| parent | 2f5f9bd3807ff1bf5932bcb8fbd7bca3bddd99d0 (diff) | |
| download | ChibiOS-3133defc42d84cc8d03ed270a9407578dae54ad6.tar.gz ChibiOS-3133defc42d84cc8d03ed270a9407578dae54ad6.tar.bz2 ChibiOS-3133defc42d84cc8d03ed270a9407578dae54ad6.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5429 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
| -rw-r--r-- | os/hal/platforms/SPC564Axx/hal_lld.c | 40 |
1 files changed, 21 insertions, 19 deletions
diff --git a/os/hal/platforms/SPC564Axx/hal_lld.c b/os/hal/platforms/SPC564Axx/hal_lld.c index 0f4dbc0cf..f7fa9548b 100644 --- a/os/hal/platforms/SPC564Axx/hal_lld.c +++ b/os/hal/platforms/SPC564Axx/hal_lld.c @@ -52,29 +52,31 @@ void hal_lld_init(void) { extern void _vectors(void);
uint32_t n;
-#if 0
/* FLASH wait states and prefetching setup.*/
- CFLASH0.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
- CFLASH0.BIUCR2.R = 0;
- CFLASH0.PFCR3.R = 0;
-
- /* Optimal crossbar settings. The DMA priority is placed above the CPU
- priority in order to not starve I/O activities while the CPU is
- executing tight loops (FLASH and SRAM slave ports only).
- The SRAM is parked on the load/store port, for some unknown reason it
+ FLASH_A.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
+ FLASH_A.BIUCR2.R = 0;
+ FLASH_B.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
+ FLASH_B.BIUCR2.R = 0;
+
+ /* The SRAM is parked on the load/store port, for some unknown reason it
is defaulted on the instructions port and this kills performance.*/
- XBAR.SGPCR3.B.PARK = 4; /* RAM slave on load/store port.*/
- XBAR.MPR0.R = 0x00030201; /* Flash slave port priorities:
- eDMA (1): 0 (highest)
+ XBAR.SGPCR2.B.PARK = 1; /* RAM slave on load/store port.*/
+
+ /* The DMA priority is placed above the CPU priority in order to not
+ starve I/O activities while the CPU is executing tight loops (FLASH
+ and SRAM slave ports only).*/
+ XBAR.MPR0.R = 0x34000021; /* Flash slave port priorities:
+ eDMA (4): 0 (highest)
Core Instructions (0): 1
- Undocumented (2): 2
- Core Data (4): 3 */
- XBAR.MPR3.R = 0x00030201; /* SRAM slave port priorities:
- eDMA (1): 0 (highest)
+ Core Data (1): 2
+ EBI (7): 3
+ Flexray (6): 4 */
+ XBAR.MPR2.R = 0x34000021; /* SRAM slave port priorities:
+ eDMA (4): 0 (highest)
Core Instructions (0): 1
- Undocumented (2): 2
- Core Data (4): 3 */
-#endif
+ Core Data (1): 2
+ EBI (7): 3
+ FlexRay (6): 4 */
/* Downcounter timer initialized for system tick use, TB enabled for debug
and measurements.*/
|