More H7 code, not functional yet.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11178 35acf78f-673a-0410-8e92-d51de3d6d3f4

3 files changed, 803 insertions, 580 deletions

diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.c b/os/hal/ports/STM32/STM32H7xx/hal_lld.c
index c174c859e..1fd2f9aa5 100644
--- a/os/hal/ports/STM32/STM32H7xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.c
@@ -51,7 +51,7 @@ uint32_t SystemCoreClock = STM32_HCLK;
  * @note    WARNING! Changing clock source impossible without resetting

  *          of the whole BKP domain.

  */

-static void hal_lld_backup_domain_init(void) {

+static inline void init_bkp_domain(void) {

 

   /* Backup domain access enabled and left open.*/

   PWR->CR1 |= PWR_CR1_DBP;

@@ -86,16 +86,30 @@ static void hal_lld_backup_domain_init(void) {
     RCC->BDCR |= RCC_BDCR_RTCEN;

   }

 #endif /* HAL_USE_RTC */

+}

 

-#if STM32_BKPRAM_ENABLE

+/**

+ * @brief   Initializes the PWR unit.

+ */

+static inline void init_pwr(void) {

+

+  PWR->CR1   = STM32_PWR_CR1;

+  PWR->CR2   = STM32_PWR_CR2;

+  PWR->CR3   = STM32_PWR_CR3;

+  PWR->CR1   = STM32_PWR_CR1;

+  PWR->CPUCR = STM32_PWR_CPUCR;

+  PWR->D3CR  = STM32_VOS;

+  while ((PWR->CSR1 & PWR_CSR1_ACTVOS) == 0)

+    ;

+#if STM32_PWR_CR2 & PWR_CR2_BREN

+  while ((PWR->CR2 & PWR_CR2_BRRDY) == 0)

+    ;

   rccEnableBKPSRAM(false);

-

-  PWR->CSR1 |= PWR_CSR1_BRE;

-  while ((PWR->CSR1 & PWR_CSR1_BRR) == 0)

-    ;                                /* Waits until the regulator is stable */

-#else

-  PWR->CSR1 &= ~PWR_CSR1_BRE;

-#endif /* STM32_BKPRAM_ENABLE */

+#endif

+#if STM32_PWR_CR3 & PWR_CR3_USB33DEN

+  while ((PWR->CR3 & PWR_CR3_USB33RDY) == 0)

+    ;

+#endif

 }

 

 /*===========================================================================*/

@@ -113,17 +127,22 @@ static void hal_lld_backup_domain_init(void) {
  */

 void hal_lld_init(void) {

 

-  /* Reset of all peripherals. AHB3 is not reseted because it could have

-     been initialized in the board initialization file (board.c).

+  /* Reset of all peripherals. AHB3 is not reset entirely because FMC could

+     have been initialized in the board initialization file (board.c).

      Note, GPIOs are not reset because initialized before this point in

      board files.*/

-  rccResetAHB1(~STM32_GPIO_EN_MASK);

+  rccResetAHB1(~0);

   rccResetAHB2(~0);

-  rccResetAPB1(~RCC_APB1RSTR_PWRRST);

+  rccResetAHB3(~(RCC_AHB3RSTR_CPURST | RCC_AHB3RSTR_FMCRST));

+  rccResetAHB4(~STM32_GPIO_EN_MASK);

+  rccResetAPB1L(~0);

+  rccResetAPB1H(~0);

   rccResetAPB2(~0);

+  rccResetAPB3(~0);

+  rccResetAPB4(~0);

 

-  /* Initializes the backup domain.*/

-  hal_lld_backup_domain_init();

+  /* Backup domain initialization.*/

+  init_bkp_domain();

 

   /* DMA subsystems initialization.*/

 #if defined(STM32_DMA_REQUIRED)

@@ -132,27 +151,6 @@ void hal_lld_init(void) {
 

   /* IRQ subsystem initialization.*/

   irqInit();

-

-#if STM32_SRAM2_NOCACHE

-  /* The SRAM2 bank can optionally made a non cache-able area for use by

-     DMA engines.*/

-  mpuConfigureRegion(MPU_REGION_7,

-                     SRAM2_BASE,

-                     MPU_RASR_ATTR_AP_RW_RW |

-                     MPU_RASR_ATTR_NON_CACHEABLE |

-                     MPU_RASR_SIZE_16K |

-                     MPU_RASR_ENABLE);

-  mpuEnable(MPU_CTRL_PRIVDEFENA);

-

-  /* Invalidating data cache to make sure that the MPU settings are taken

-     immediately.*/

-  SCB_CleanInvalidateDCache();

-#endif

-

-  /* Programmable voltage detector enable.*/

-#if STM32_PVD_ENABLE

-  PWR->CR1 |= PWR_CR1_PVDE | (STM32_PLS & STM32_PLS_MASK);

-#endif /* STM32_PVD_ENABLE */

 }

 

 /**

@@ -164,16 +162,9 @@ void hal_lld_init(void) {
  */

 void stm32_clock_init(void) {

 

-#if !STM32_NO_INIT

-  /* PWR clock enabled.*/

-#if defined(HAL_USE_RTC) && defined(RCC_APB1ENR_RTCEN)

-  RCC->APB1ENR = RCC_APB1ENR_PWREN | RCC_APB1ENR_RTCEN;

-#else

-  RCC->APB1ENR = RCC_APB1ENR_PWREN;

-#endif

-

+#if STM32_NO_INIT == FALSE

   /* PWR initialization.*/

-  PWR->CR1 = STM32_VOS;

+  init_pwr();

 

   /* HSI setup, it enforces the reset situation in order to handle possible

      problems with JTAG probes and re-initializations.*/

@@ -184,100 +175,124 @@ void stm32_clock_init(void) {
   /* HSI is selected as new source without touching the other fields in

      CFGR. Clearing the register has to be postponed after HSI is the

      new source.*/

-  RCC->CFGR &= ~RCC_CFGR_SW;                /* Reset SW */

-  RCC->CFGR |= RCC_CFGR_SWS_HSI;            /* Select HSI as internal*/

+  RCC->CFGR &= ~RCC_CFGR_SW;                /* Reset SW to HSI.             */

   while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)

     ;                                       /* Wait until HSI is selected.  */

 

-  /* Registers finally cleared to reset values.*/

-  RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value.              */

-  RCC->CFGR = 0;                            /* CFGR reset value.            */

+  /* Registers cleared to reset values.*/

+  RCC->CR    = RCC_CR_HSION;               /* CR Reset value.              */

+  RCC->ICSCR = 0x40000000;                 /* ICSCR Reset value.           */

+  RCC->CFGR  = 0x00000000;                 /* CFGR reset value.            */

+  RCC->CSR   = 0x00000000;                 /* CSR reset value.             */

 

-#if STM32_HSE_ENABLED

-  /* HSE activation.*/

+  /* HSE activation with optional bypass.*/

+#if STM32_HSE_ENABLED == TRUE

 #if defined(STM32_HSE_BYPASS)

-  /* HSE Bypass.*/

   RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;

 #else

-  /* No HSE Bypass.*/

   RCC->CR |= RCC_CR_HSEON;

 #endif

   while ((RCC->CR & RCC_CR_HSERDY) == 0)

     ;                           /* Waits until HSE is stable.               */

 #endif

 

-#if STM32_LSI_ENABLED

+  /* CSI activation.*/

+#if STM32_CSI_ENABLED == TRUE

+  RCC->CR |= RCC_CR_CSION;

+  while ((RCC->CR & RCC_CR_CSIRDY) == 0)

+    ;                           /* Waits until CSI is stable.               */

+#endif /* STM32_HSE_ENABLED == TRUE */

+

   /* LSI activation.*/

+#if STM32_LSI_ENABLED == TRUE

   RCC->CSR |= RCC_CSR_LSION;

   while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)

     ;                           /* Waits until LSI is stable.               */

+#endif /* STM32_LSI_ENABLED == TRUE */

+

+  /* PLLs activation, it happens in parallel in order to

+     reduce boot time.*/

+#if (STM32_PLL1_ENABLED == TRUE) ||                                         \

+    (STM32_PLL2_ENABLED == TRUE) ||                                         \

+    (STM32_PLL3_ENABLED == TRUE)

+  {

+    uint32_t onmask = 0;

+    uint32_t rdymask = 0;

+    uint32_t cfgmask = 0;

+

+    RCC->PLLCKSELR = RCC_PLLCKSELR_DIVM3_VALUE(STM32_PLL3_DIVM_VALUE) |

+                     RCC_PLLCKSELR_DIVM2_VALUE(STM32_PLL2_DIVM_VALUE) |

+                     RCC_PLLCKSELR_DIVM1_VALUE(STM32_PLL1_DIVM_VALUE) |

+                     RCC_PLLCKSELR_PLLSRC_VALUE(STM32_PLLSRC);

+

+#if STM32_PLL1_ENABLED == TRUE

+    RCC->PLL1DIVR  = STM32_PLL1_DIVR | STM32_PLL1_DIVQ |

+                     STM32_PLL1_DIVP | STM32_PLL1_DIVN;

+    RCC->PLL1FRACR = STM32_PLL1_FRACN;

+    RCC->CR       |= RCC_CR_PLL1ON;

 #endif

 

-#if STM32_ACTIVATE_PLL

-  /* PLL activation.*/

-  RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN |

-                 STM32_PLLM;

-  RCC->CR |= RCC_CR_PLLON;

-

-  /* Synchronization with voltage regulator stabilization.*/

-  while ((PWR->CSR1 & PWR_CSR1_VOSRDY) == 0)

-    ;                           /* Waits until power regulator is stable.   */

-

-#if STM32_OVERDRIVE_REQUIRED

-  /* Overdrive activation performed after activating the PLL in order to save

-     time as recommended in RM in "Entering Over-drive mode" paragraph.*/

-  PWR->CR1 |= PWR_CR1_ODEN;

-  while (!(PWR->CSR1 & PWR_CSR1_ODRDY))

-      ;

-  PWR->CR1 |= PWR_CR1_ODSWEN;

-  while (!(PWR->CSR1 & PWR_CSR1_ODSWRDY))

-      ;

-#endif /* STM32_OVERDRIVE_REQUIRED */

+#if STM32_PLL2_ENABLED == TRUE

+    RCC->PLL2DIVR  = STM32_PLL2_DIVR | STM32_PLL2_DIVQ |

+                     STM32_PLL2_DIVP | STM32_PLL2_DIVN;

+    RCC->PLL2FRACR = STM32_PLL2_FRACN;

+    RCC->CR       |= RCC_CR_PLL2ON;

+#endif

 

-  /* Waiting for PLL lock.*/

-  while (!(RCC->CR & RCC_CR_PLLRDY))

-    ;

-#endif /* STM32_OVERDRIVE_REQUIRED */

+#if STM32_PLL3_ENABLED == TRUE

+    RCC->PLL3DIVR  = STM32_PLL3_DIVR | STM32_PLL3_DIVQ |

+                     STM32_PLL3_DIVP | STM32_PLL3_DIVN;

+    RCC->PLL3FRACR = STM32_PLL3_FRACN;

+    RCC->CR       |= RCC_CR_PLL3ON;

+#endif

 

-#if STM32_ACTIVATE_PLLI2S

-  /* PLLI2S activation.*/

-  RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN;

-  RCC->CR |= RCC_CR_PLLI2SON;

+   cfgmask = STM32_PLLCFGR_PLL3RGE | STM32_PLLCFGR_PLL3VCOSEL | RCC_PLLCFGR_PLL3FRACEN |

+             STM32_PLLCFGR_PLL2RGE | STM32_PLLCFGR_PLL2VCOSEL | RCC_PLLCFGR_PLL2FRACEN |

+             STM32_PLLCFGR_PLL1RGE | STM32_PLLCFGR_PLL1VCOSEL | RCC_PLLCFGR_PLL1FRACEN;

 

-  /* Waiting for PLL lock.*/

-  while (!(RCC->CR & RCC_CR_PLLI2SRDY))

-    ;

+#if STM32_PLL1_ENABLED == TRUE

+    onmask  |= RCC_CR_PLL1ON;

+    rdymask |= RCC_CR_PLL1RDY;

+    cfgmask |= RCC_PLLCFGR_DIVR1EN | RCC_PLLCFGR_DIVQ1EN | RCC_PLLCFGR_DIVP1EN;

 #endif

 

-#if STM32_ACTIVATE_PLLSAI

-  /* PLLSAI activation.*/

-  RCC->PLLSAICFGR = STM32_PLLSAIR | STM32_PLLSAIQ | STM32_PLLSAIP |

-                    STM32_PLLSAIN;

-  RCC->CR |= RCC_CR_PLLSAION;

-

-  /* Waiting for PLL lock.*/

-  while (!(RCC->CR & RCC_CR_PLLSAIRDY))

-    ;

+#if STM32_PLL2_ENABLED == TRUE

+    onmask  |= RCC_CR_PLL2ON;

+    rdymask |= RCC_CR_PLL2RDY;

+    cfgmask |= RCC_PLLCFGR_DIVR2EN | RCC_PLLCFGR_DIVQ2EN | RCC_PLLCFGR_DIVP2EN;

 #endif

 

-  /* Other clock-related settings (dividers, MCO etc).*/

-  RCC->CFGR = STM32_MCO2SEL | STM32_MCO2PRE | STM32_MCO1PRE | STM32_I2SSRC |

-              STM32_MCO1SEL | STM32_RTCPRE  | STM32_PPRE2   | STM32_PPRE1  |

-              STM32_HPRE;

+#if STM32_PLL3_ENABLED == TRUE

+    onmask  |= RCC_CR_PLL3ON;

+    rdymask |= RCC_CR_PLL3RDY;

+    cfgmask |= RCC_PLLCFGR_DIVR3EN | RCC_PLLCFGR_DIVQ3EN | RCC_PLLCFGR_DIVP3EN;

+#endif

 

-  /* DCKCFGR1 register initialization, note, must take care of the _OFF

-     pseudo settings.*/

-  {

-    uint32_t dckcfgr1 = STM32_PLLI2SDIVQ | STM32_PLLSAIDIVQ | STM32_PLLSAIDIVR;

-#if STM32_SAI2SEL != STM32_SAI2SEL_OFF

-    dckcfgr1 |= STM32_SAI2SEL;

+    /* Activating enabled PLLs and waiting for all of them to become ready.*/

+    RCC->PLLCFGR = cfgmask & STM32_PLLCFGR_MASK;

+    RCC->CR     |= onmask;

+    while ((RCC->CR & rdymask) != rdymask)

+      ;

+  }

 #endif

-#if STM32_SAI1SEL != STM32_SAI1SEL_OFF

-    dckcfgr1 |= STM32_SAI1SEL;

+

+  /* Other clock-related settings.*/

+  RCC->CFGR = STM32_MCO2SEL | RCC_CFGR_MCO2PRE_VALUE(STM32_MCO2PRE_VALUE) |

+              STM32_MCO1SEL | RCC_CFGR_MCO1PRE_VALUE(STM32_MCO1PRE_VALUE) |

+              RCC_CFGR_RTCPRE_VALUE(STM32_RTCPRE_VALUE);

+

+  /* Flash setup.*/

+  FLASH->ACR = FLASH_ACR_WRHIGHFREQ_2 | STM32_FLASHBITS;

+

+  /* Switching to the configured clock source if it is different

+     from HSI.*/

+#if STM32_SW != STM32_SW_HSI_CK

+  RCC->CFGR |= STM32_SW;        /* Switches on the selected clock source.   */

+  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))

+    ;

 #endif

-    RCC->DCKCFGR1 = dckcfgr1;

-  }

 

+#if 0

   /* Peripheral clock sources.*/

   RCC->DCKCFGR2 = STM32_SDMMCSEL  | STM32_CK48MSEL  | STM32_CECSEL    |

                   STM32_LPTIM1SEL | STM32_I2C4SEL   | STM32_I2C3SEL   |

@@ -285,21 +300,12 @@ void stm32_clock_init(void) {
                   STM32_UART7SEL  | STM32_USART6SEL | STM32_UART5SEL  |

                   STM32_UART4SEL  | STM32_USART3SEL | STM32_USART2SEL |

                   STM32_USART1SEL;

-

-  /* Flash setup.*/

-  FLASH->ACR = FLASH_ACR_ARTEN | FLASH_ACR_PRFTEN | STM32_FLASHBITS;

-

-  /* Switching to the configured clock source if it is different from HSI.*/

-#if (STM32_SW != STM32_SW_HSI)

-  RCC->CFGR |= STM32_SW;        /* Switches on the selected clock source.   */

-  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))

-    ;

 #endif

 #endif /* STM32_NO_INIT */

 

   /* SYSCFG clock enabled here because it is a multi-functional unit shared

      among multiple drivers.*/

-  rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);

+  rccEnableAPB4(RCC_APB4ENR_SYSCFGEN);

 }

 

 /** @} */

diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.h b/os/hal/ports/STM32/STM32H7xx/hal_lld.h
index 1913e9f1a..7308e65e7 100644
--- a/os/hal/ports/STM32/STM32H7xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.h
@@ -116,54 +116,44 @@
 #define STM32_LSECLK_MIN        32768

 

 /**

- * @brief   Maximum PLLs input clock frequency using VCOL.

+ * @brief   Minimum PLLs input clock frequency..

  */

-#define STM32_PLLINL_MAX        2000000

+#define STM32_PLLIN_MIN         1000000

 

 /**

- * @brief   Minimum PLLs input clock frequency using VCOL.

+ * @brief   PLLs input threshold frequency 1.

  */

-#define STM32_PLLINL_MIN        1000000

+#define STM32_PLLIN_THRESHOLD1  2000000

 

 /**

- * @brief   Maximum PLLs input clock frequency using VCOH.

+ * @brief   PLLs input threshold frequency 2.

  */

-#define STM32_PLLINH_MAX        16000000

+#define STM32_PLLIN_THRESHOLD2  4000000

 

 /**

- * @brief   Minimum PLLs input clock frequency using VCOH.

+ * @brief   PLLs input threshold frequency 3.

  */

-#define STM32_PLLINH_MIN        2000000

+#define STM32_PLLIN_THRESHOLD3  8000000

 

 /**

- * @brief   Maximum PLLs VCOL clock frequency.

+ * @brief   Maximum PLLs input clock frequency.

  */

-#define STM32_PLLVCOL_MAX       420000000

+#define STM32_PLLIN_MAX         16000000

 

 /**

- * @brief   Minimum PLLs VCOL clock frequency.

+ * @brief   Minimum PLLs VCO clock frequency.

  */

-#define STM32_PLLVCOL_MIN       150000000

+#define STM32_PLLVCO_MIN        150000000

 

 /**

- * @brief   Maximum PLLs VCOH clock frequency.

- */

-#define STM32_PLLVCOH_MAX       836000000

-

-/**

- * @brief   Minimum PLLs VCOH clock frequency.

+ * @brief   Threshold PLLs clock frequency.

  */

-#define STM32_PLLVCOH_MIN       192000000

+#define STM32_PLLVCO_THRESHOLD  420000000

 

 /**

- * @brief   Maximum PLL output clock frequency.

- */

-#define STM32_PLLOUT_MAX        400000000

-

-/**

- * @brief   Minimum PLL output clock frequency.

+ * @brief   Maximum PLLs VCOH clock frequency.

  */

-#define STM32_PLLOUT_MIN        1500000

+#define STM32_PLLVCO_MAX        836000000

 

 /**

  * @brief   Maximum APB1 clock frequency.

@@ -200,18 +190,16 @@
  * @name    Internal clock sources

  * @{

  */

-#define STM32_HSICLK            64000000    /**< High speed internal clock. */

-#define STM32_LSICLK            32000       /**< Low speed internal clock.  */

+#define STM32_HSICLK            64000000

+#define STM32_HSI48CLK          48000000

+#define STM32_CSICLK            4000000

+#define STM32_LSICLK            32000

 /** @} */

 

 /**

  * @name    Register helpers not found in ST headers

  * @{

  */

-#define PWR_D3CR_VOS_SCALE3             (PWR_D3CR_VOS_0)

-#define PWR_D3CR_VOS_SCALE2             (PWR_D3CR_VOS_1)

-#define PWR_D3CR_VOS_SCALE1             (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0)

-

 #define RCC_CR_HSIDIV_VALUE(n)          ((n) << 3U)

 

 #define RCC_CFGR_SW_VALUE(n)            ((n) << 0U)

@@ -221,8 +209,8 @@
 #define RCC_CFGR_MCO2PRE_VALUE(n)       ((n) << 25U)

 #define RCC_CFGR_MCO2_VALUE(n)          ((n) << 29U)

 

+#define RCC_D1CFGR_D1HPRE_VALUE(n)      ((n) << RCC_D1CFGR_HPRE_Pos)

 #define RCC_D1CFGR_D1CPRE_VALUE(n)      ((n) << RCC_D1CFGR_D1CPRE_Pos)

-#define RCC_D1CFGR_D1HPRE_VALUE(n)      ((n) << RCC_D1CFGR_D1HPRE_Pos)

 #define RCC_D1CFGR_D1PPRE3_VALUE(n)     ((n) << RCC_D1CFGR_D1PPRE_Pos)

 

 #define RCC_D2CFGR_D2PPRE1_VALUE(n)     ((n) << RCC_D2CFGR_D2PPRE1_Pos)

@@ -266,6 +254,10 @@
  * @name    Configuration switches to be used in @p mcuconf.h

  * @{

  */

+#define STM32_VOS_SCALE3                (PWR_D3CR_VOS_0)

+#define STM32_VOS_SCALE2                (PWR_D3CR_VOS_1)

+#define STM32_VOS_SCALE1                (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0)

+

 #define STM32_SW_HSI_CK                 RCC_CFGR_SW_VALUE(0U)

 #define STM32_SW_CSI_CK                 RCC_CFGR_SW_VALUE(1U)

 #define STM32_SW_HSE_CK                 RCC_CFGR_SW_VALUE(2U)

@@ -309,11 +301,11 @@
 #define STM32_D2PPRE2_DIV8              RCC_D2CFGR_D2PPRE2_VALUE(6U)

 #define STM32_D2PPRE2_DIV16             RCC_D2CFGR_D2PPRE2_VALUE(7U)

 

-#define STM32_D3PPRE4_DIV1              RCC_D1CFGR_D3PPRE4_VALUE(0U)

-#define STM32_D3PPRE4_DIV2              RCC_D1CFGR_D3PPRE4_VALUE(4U)

-#define STM32_D3PPRE4_DIV4              RCC_D1CFGR_D3PPRE4_VALUE(5U)

-#define STM32_D3PPRE4_DIV8              RCC_D1CFGR_D3PPRE4_VALUE(6U)

-#define STM32_D3PPRE4_DIV16             RCC_D1CFGR_D3PPRE4_VALUE(7U)

+#define STM32_D3PPRE4_DIV1              RCC_D3CFGR_D3PPRE4_VALUE(0U)

+#define STM32_D3PPRE4_DIV2              RCC_D3CFGR_D3PPRE4_VALUE(4U)

+#define STM32_D3PPRE4_DIV4              RCC_D3CFGR_D3PPRE4_VALUE(5U)

+#define STM32_D3PPRE4_DIV8              RCC_D3CFGR_D3PPRE4_VALUE(6U)

+#define STM32_D3PPRE4_DIV16             RCC_D3CFGR_D3PPRE4_VALUE(7U)

 

 #define STM32_HSIDIV_DIV1               RCC_CR_HSIDIV_VALUE(0U)

 #define STM32_HSIDIV_DIV2               RCC_CR_HSIDIV_VALUE(1U)

@@ -327,12 +319,13 @@
 #define STM32_MCO1SEL_HSI48_CK          RCC_CFGR_MCO1_VALUE(4U)

 

 #define STM32_MCO2SEL_SYS_CK            RCC_CFGR_MCO2_VALUE(0U)

-#define STM32_MCO2SEL_PLL2_Q_CK         RCC_CFGR_MCO2_VALUE(1U)

+#define STM32_MCO2SEL_PLL2_P_CK         RCC_CFGR_MCO2_VALUE(1U)

 #define STM32_MCO2SEL_HSE_CK            RCC_CFGR_MCO2_VALUE(2U)

 #define STM32_MCO2SEL_PLL1_P_CK         RCC_CFGR_MCO2_VALUE(3U)

 #define STM32_MCO2SEL_CSI_CK            RCC_CFGR_MCO2_VALUE(4U)

 #define STM32_MCO2SEL_LSI_CK            RCC_CFGR_MCO2_VALUE(5U)

 

+#define STM32_RTCSEL_MASK               RCC_BDCR_RTCSEL_Msk

 #define STM32_RTCSEL_NOCLK              RCC_BDCR_RTCSEL_VALUE(0U)

 #define STM32_RTCSEL_LSE_CK             RCC_BDCR_RTCSEL_VALUE(1U)

 #define STM32_RTCSEL_LSI_CK             RCC_BDCR_RTCSEL_VALUE(2U)

@@ -363,17 +356,19 @@
 #endif

 

 /**

- * @brief   HCLK value assumed if @p STM32_NO_INIT is enabled.

+ * @brief   SYS_CK value assumed if @p STM32_NO_INIT is enabled.

  */

-#if !defined(STM32_HCLK_ENFORCED_VALUE) || defined(__DOXYGEN__)

-#define STM32_HCLK_ENFORCED_VALUE           STM32_HSICLK

+#if !defined(STM32_SYS_CK_ENFORCED_VALUE) || defined(__DOXYGEN__)

+#define STM32_SYS_CK_ENFORCED_VALUE         STM32_HSICLK

 #endif

 

 /**

  * @brief   PWR CR1 initializer.

  */

 #if !defined(STM32_PWR_CR1) || defined(__DOXYGEN__)

-#define STM32_PWR_CR1                       (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)

+#define STM32_PWR_CR1                       (PWR_CR1_PVDEN |                \

+                                             PWR_CR1_SVOS_1 |               \

+                                             PWR_CR1_SVOS_0)

 #endif

 

 /**

@@ -387,7 +382,10 @@
  * @brief   PWR CR3 initializer.

  */

 #if !defined(STM32_PWR_CR3) || defined(__DOXYGEN__)

-#define STM32_PWR_CR3                       (PWR_CR3_SCUEN | PWR_CR3_LDOEN)

+#define STM32_PWR_CR3                       (PWR_CR3_SCUEN |                \

+                                             PWR_CR3_LDOEN |                \

+                                             PWR_CR3_USBREGEN |             \

+                                             PWR_CR3_USB33DEN)

 #endif

 

 /**

@@ -398,10 +396,10 @@
 #endif

 

 /**

- * @brief   PWR D3CR initializer.

+ * @brief   VOS setting.

  */

-#if !defined(STM32_PWR_D3CR) || defined(__DOXYGEN__)

-#define STM32_PWR_D3CR                      (PWR_D3CR_VOS_0)

+#if !defined(STM32_VOS) || defined(__DOXYGEN__)

+#define STM32_VOS                           STM32_VOS_SCALE1

 #endif

 

 /**

@@ -469,6 +467,16 @@
 #endif

 

 /**

+ * @brief   Masking of PLLCFGR register.

+ * @note    By default all options in PLLCFGR are enabled, this option

+ *          allows to mask specific bits for power saving reasons.

+ *          Use with caution.

+ */

+#if !defined(STM32_PLLCFGR_MASK) || defined(__DOXYGEN__)

+#define STM32_PLLCFGR_MASK                  ~0

+#endif

+

+/**

  * @brief   Enables or disables the PLL1.

  */

 #if !defined(STM32_PLL1_ENABLED) || defined(__DOXYGEN__)

@@ -650,8 +658,8 @@
 /**

  * @brief   MCO1 clock prescaler.

  */

-#if !defined(STM32_MCO1PRE) || defined(__DOXYGEN__)

-#define STM32_MCO1PRE                       4

+#if !defined(STM32_MCO1PRE_VALUE) || defined(__DOXYGEN__)

+#define STM32_MCO1PRE_VALUE                 4

 #endif

 

 /**

@@ -664,8 +672,8 @@
 /**

  * @brief   MCO2 clock prescaler.

  */

-#if !defined(STM32_MCO2PRE) || defined(__DOXYGEN__)

-#define STM32_MCO2PRE                       4

+#if !defined(STM32_MCO2PRE_VALUE) || defined(__DOXYGEN__)

+#define STM32_MCO2PRE_VALUE                 4

 #endif

 

 /**

@@ -1009,6 +1017,42 @@
 #error "STM32_VDD not defined in board.h"

 #endif

 

+/**

+ * @name    Constants depending on VOS setting

+ * @{

+ */

+#if (STM32_VOS == STM32_VOS_SCALE1) || defined(__DOXYGEN__)

+#define STM32_0WS_THRESHOLD         70000000

+#define STM32_1WS_THRESHOLD         140000000

+#define STM32_2WS_THRESHOLD         210000000

+#define STM32_3WS_THRESHOLD         0

+#define STM32_4WS_THRESHOLD         0

+#define STM32_PLLOUT_MAX            400000000

+#define STM32_PLLOUT_MIN            1500000

+

+#elif STM32_VOS == STM32_VOS_SCALE2

+#define STM32_0WS_THRESHOLD         55000000

+#define STM32_1WS_THRESHOLD         110000000

+#define STM32_2WS_THRESHOLD         165000000

+#define STM32_3WS_THRESHOLD         220000000

+#define STM32_4WS_THRESHOLD         0

+#define STM32_PLLOUT_MAX            300000000

+#define STM32_PLLOUT_MIN            1500000

+

+#elif STM32_VOS == STM32_VOS_SCALE3

+#define STM32_0WS_THRESHOLD         45000000

+#define STM32_1WS_THRESHOLD         90000000

+#define STM32_2WS_THRESHOLD         135000000

+#define STM32_3WS_THRESHOLD         180000000

+#define STM32_4WS_THRESHOLD         225000000

+#define STM32_PLLOUT_MAX            200000000

+#define STM32_PLLOUT_MIN            1500000

+

+#else

+#error "invalid STM32_VOS setting specified"

+#endif

+/** @} */

+

 /*

  * HSI related checks.

  */

@@ -1035,6 +1079,43 @@
 #endif /* !STM32_HSI_ENABLED */

 

 /*

+ * HSI48 related checks.

+ */

+#if STM32_HSI48_ENABLED

+#else /* !STM32_HSI48_ENABLED */

+

+#if STM32_MCO1SEL == STM32_MCO1SEL_HSI48_CK

+#error "HSI48 not enabled, required by STM32_MCO1SEL"

+#endif

+

+#endif /* !STM32_HSI48_ENABLED */

+

+/*

+ * CSI related checks.

+ */

+#if STM32_CSI_ENABLED

+#else /* !STM32_CSI_ENABLED */

+

+#if STM32_SW == STM32_SW_CSI_CK

+#error "CSI not enabled, required by STM32_SW"

+#endif

+

+#if (STM32_PLLSRC == STM32_PLLSRC_CSI_CK) &&                                \

+    (STM32_PLL1_ENABLED || STM32_PLL2_ENABLED || STM32_PLL3_ENABLED)

+#error "CSI not enabled, required by STM32_PLLSRC and STM32_PLLx_ENABLED"

+#endif

+

+#if STM32_CKPERSEL == STM32_CKPERSEL_CSI_CK

+#error "CSI not enabled, required by STM32_CKPERSEL"

+#endif

+

+#if STM32_MCO2SEL == STM32_MCO2SEL_CSI_CK

+#error "CSI not enabled, required by STM32_MCO2SEL"

+#endif

+

+#endif /* !STM32_CSI_ENABLED */

+

+/*

  * HSE related checks.

  */

 #if STM32_HSE_ENABLED

@@ -1044,11 +1125,11 @@
 #else /* STM32_HSECLK != 0 */

 #if defined(STM32_HSE_BYPASS)

 #if (STM32_HSECLK < STM32_HSECLK_BYP_MIN) || (STM32_HSECLK > STM32_HSECLK_BYP_MAX)

-#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_BYP_MIN...STM32_HSECLK_BYP_MAX)"

+#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_BYP_MIN..STM32_HSECLK_BYP_MAX)"

 #endif

 #else /* !defined(STM32_HSE_BYPASS) */

 #if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)

-#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"

+#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN..STM32_HSECLK_MAX)"

 #endif

 #endif /* !defined(STM32_HSE_BYPASS) */

 #endif /* STM32_HSECLK != 0 */

@@ -1104,11 +1185,11 @@
 

 #if defined(STM32_LSE_BYPASS)

 #if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_BYP_MAX)

-#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_BYP_MAX)"

+#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN..STM32_LSECLK_BYP_MAX)"

 #endif

 #else

 #if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)

-#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"

+#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN..STM32_LSECLK_MAX)"

 #endif

 #endif

 

@@ -1117,7 +1198,7 @@
 #endif

 

 #if (STM32_LSEDRV >> 3) > 3

-#error "STM32_LSEDRV outside acceptable range ((0<<3)...(3<<3))"

+#error "STM32_LSEDRV outside acceptable range ((0<<3)..(3<<3))"

 #endif

 

 #else /* !STM32_LSE_ENABLED */

@@ -1132,526 +1213,533 @@
 

 #endif /* !STM32_LSE_ENABLED */

 

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

+/**

+ * @brief   HSI divided clock.

+ */

+#if (STM32_HSIDIV == STM32_HSIDIV_DIV1) || defined(__DOXYGEN__)

+#define STM32_HSI_CK                (STM32_HSICLK / 1U)

+#elif STM32_HSIDIV == STM32_HSIDIV_DIV2

+#define STM32_HSI_CK                (STM32_HSICLK / 2U)

+#elif STM32_HSIDIV == STM32_HSIDIV_DIV4

+#define STM32_HSI_CK                (STM32_HSICLK / 4U)

+#elif STM32_HSIDIV == STM32_HSIDIV_DIV8

+#define STM32_HSI_CK                (STM32_HSICLK / 8U)

+#else

+#error "invalid STM32_HSIDIV value specified"

+#endif

 

 /**

- * @brief   STM32_PLLM field.

+ * @brief   HSE divided clock for RTC.

  */

-#if ((STM32_PLLM_VALUE >= 2) && (STM32_PLLM_VALUE <= 63)) ||                \

+#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 63)) ||            \

     defined(__DOXYGEN__)

-#define STM32_PLLM                  (STM32_PLLM_VALUE << 0)

+#define STM32_HSE_1M_CK             (STM32_HSECLK / STM32_RTCPRE_VALUE)

 #else

-#error "invalid STM32_PLLM_VALUE value specified"

+#error "invalid STM32_RTCPRE_VALUE value specified"

 #endif

 

 /**

  * @brief   PLLs input clock frequency.

  */

 #if (STM32_PLLSRC == STM32_PLLSRC_HSE_CK) || defined(__DOXYGEN__)

-#define STM32_PLLCLKIN              (STM32_HSECLK / STM32_PLLM_VALUE)

+#define STM32_PLLCLKIN              STM32_HSECLK

 

 #elif STM32_PLLSRC == STM32_PLLSRC_HSI_CK

-#define STM32_PLLCLKIN              (STM32_HSICLK / STM32_PLLM_VALUE)

+#define STM32_PLLCLKIN              STM32_HSI_CK

+

+#elif STM32_PLLSRC == STM32_PLLSRC_CSI_CK

+#define STM32_PLLCLKIN              STM32_CSICLK

 

 #else

 #error "invalid STM32_PLLSRC value specified"

 #endif

 

-/*

- * PLLs input frequency range check.

+/**

+ * @brief   PLL1 DIVM field.

  */

-#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)

-#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"

+#if ((STM32_PLL1_DIVM_VALUE >= 1) && (STM32_PLL1_DIVM_VALUE <= 63)) ||      \

+    defined(__DOXYGEN__)

+#define STM32_PLL1_DIVM             (STM32_PLL1_DIVM_VALUE << 4)

+#define STM32_PLL1_REF_CK           (STM32_PLLCLKIN / STM32_PLL1_DIVM_VALUE)

+#else

+#error "invalid STM32_PLL1_DIVM_VALUE value specified"

 #endif

 

 /*

- * PLL enable check.

+ * PLL1 input frequency range check.

  */

-#if (STM32_CLOCK48_REQUIRED && (STM32_CK48MSEL == STM32_CK48MSEL_PLL)) ||   \

-    (STM32_SW == STM32_SW_PLL1_P_CK) ||                                           \

-    (STM32_MCO1SEL == STM32_MCO1SEL_PLL) ||                                 \

-    (STM32_MCO2SEL == STM32_MCO2SEL_PLL) ||                                 \

-    defined(__DOXYGEN__)

+#if (STM32_PLL1_REF_CK < STM32_PLLIN_MIN) || (STM32_PLL1_REF_CK > STM32_PLLIN_MAX)

+#error "STM32_PLL1_REF_CK outside acceptable range (STM32_PLLIN_MIN..STM32_PLLIN_MAX)"

+#endif

+

 /**

- * @brief   PLL activation flag.

+ * @brief   PLL1 input range selector.

  */

-#define STM32_ACTIVATE_PLL          TRUE

+#if (STM32_PLL1_REF_CK < STM32_PLLIN_THRESHOLD1) || defined(__DOXYGEN__)

+#define STM32_PLLCFGR_PLL1RGE       RCC_PLLCFGR_PLL1RGE_0

+#elif STM32_PLL1_REF_CK < STM32_PLLIN_THRESHOLD2

+#define STM32_PLLCFGR_PLL1RGE       RCC_PLLCFGR_PLL1RGE_1

+#elif STM32_PLL1_REF_CK < STM32_PLLIN_THRESHOLD3

+#define STM32_PLLCFGR_PLL1RGE       RCC_PLLCFGR_PLL1RGE_2

 #else

-#define STM32_ACTIVATE_PLL          FALSE

+#define STM32_PLLCFGR_PLL1RGE       RCC_PLLCFGR_PLL1RGE_3

 #endif

 

 /**

- * @brief   STM32_PLLN field.

+ * @brief   PLL2 DIVM field.

  */

-#if ((STM32_PLLN_VALUE >= 64) && (STM32_PLLN_VALUE <= 432)) ||              \

+#if ((STM32_PLL2_DIVM_VALUE >= 1) && (STM32_PLL2_DIVM_VALUE <= 63)) ||      \

     defined(__DOXYGEN__)

-#define STM32_PLLN                  (STM32_PLLN_VALUE << 6)

+#define STM32_PLL2_DIVM             (STM32_PLL2_DIVM_VALUE << 12)

+#define STM32_PLL2_REF_CK           (STM32_PLLCLKIN / STM32_PLL2_DIVM_VALUE)

 #else

-#error "invalid STM32_PLLN_VALUE value specified"

+#error "invalid STM32_PLL2_DIVM_VALUE value specified"

 #endif

 

-/**

- * @brief   STM32_PLLP field.

+/*

+ * PLL2 input frequency range check.

  */

-#if (STM32_PLLP_VALUE == 2) || defined(__DOXYGEN__)

-#define STM32_PLLP                  (0 << 16)

-

-#elif STM32_PLLP_VALUE == 4

-#define STM32_PLLP                  (1 << 16)

-

-#elif STM32_PLLP_VALUE == 6

-#define STM32_PLLP                  (2 << 16)

-

-#elif STM32_PLLP_VALUE == 8

-#define STM32_PLLP                  (3 << 16)

-

-#else

-#error "invalid STM32_PLLP_VALUE value specified"

+#if (STM32_PLL2_REF_CK < STM32_PLLIN_MIN) || (STM32_PLL2_REF_CK > STM32_PLLIN_MAX)

+#error "STM32_PLL2_REF_CK outside acceptable range (STM32_PLLIN_MIN..STM32_PLLIN_MAX)"

 #endif

 

 /**

- * @brief   STM32_PLLQ field.

+ * @brief   PLL2 input range selector.

  */

-#if ((STM32_PLLQ_VALUE >= 2) && (STM32_PLLQ_VALUE <= 15)) ||                \

-    defined(__DOXYGEN__)

-#define STM32_PLLQ                  (STM32_PLLQ_VALUE << 24)

+#if (STM32_PLL2_REF_CK < STM32_PLLIN_THRESHOLD1) || defined(__DOXYGEN__)

+#define STM32_PLLCFGR_PLL2RGE       RCC_PLLCFGR_PLL2RGE_0

+#elif STM32_PLL2_REF_CK < STM32_PLLIN_THRESHOLD2

+#define STM32_PLLCFGR_PLL2RGE       RCC_PLLCFGR_PLL2RGE_1

+#elif STM32_PLL2_REF_CK < STM32_PLLIN_THRESHOLD3

+#define STM32_PLLCFGR_PLL2RGE       RCC_PLLCFGR_PLL2RGE_2

 #else

-#error "invalid STM32_PLLQ_VALUE value specified"

+#define STM32_PLLCFGR_PLL2RGE       RCC_PLLCFGR_PLL2RGE_3

 #endif

 

 /**

- * @brief   PLL VCO frequency.

+ * @brief   PLL3 DIVM field.

  */

-#define STM32_PLLVCO                (STM32_PLLCLKIN * STM32_PLLN_VALUE)

+#if ((STM32_PLL3_DIVM_VALUE >= 1) && (STM32_PLL3_DIVM_VALUE <= 63)) ||      \

+    defined(__DOXYGEN__)

+#define STM32_PLL3_DIVM             (STM32_PLL3_DIVM_VALUE << 20)

+#define STM32_PLL3_REF_CK           (STM32_PLLCLKIN / STM32_PLL3_DIVM_VALUE)

+#else

+#error "invalid STM32_PLL3_DIVM_VALUE value specified"

+#endif

 

 /*

- * PLL VCO frequency range check.

+ * PLL3 input frequency range check.

  */

-#if (STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX)

-#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"

+#if (STM32_PLL3_REF_CK < STM32_PLLIN_MIN) || (STM32_PLL3_REF_CK > STM32_PLLIN_MAX)

+#error "STM32_PLL3_REF_CK outside acceptable range (STM32_PLLIN_MIN..STM32_PLLIN_MAX)"

 #endif

 

 /**

- * @brief   PLL P output clock frequency.

+ * @brief   PLL3 input range selector.

  */

-#define STM32_PLL_P_CLKOUT          (STM32_PLLVCO / STM32_PLLP_VALUE)

+#if (STM32_PLL3_REF_CK < STM32_PLLIN_THRESHOLD1) || defined(__DOXYGEN__)

+#define STM32_PLLCFGR_PLL3RGE       RCC_PLLCFGR_PLL3RGE_0

+#elif STM32_PLL3_REF_CK < STM32_PLLIN_THRESHOLD2

+#define STM32_PLLCFGR_PLL3RGE       RCC_PLLCFGR_PLL3RGE_1

+#elif STM32_PLL3_REF_CK < STM32_PLLIN_THRESHOLD3

+#define STM32_PLLCFGR_PLL3RGE       RCC_PLLCFGR_PLL3RGE_2

+#else

+#define STM32_PLLCFGR_PLL3RGE       RCC_PLLCFGR_PLL3RGE_3

+#endif

 

 /**

- * @brief   PLL Q output clock frequency.

+ * @brief   PLL1 DIVN field.

  */

-#define STM32_PLL_Q_CLKOUT          (STM32_PLLVCO / STM32_PLLQ_VALUE)

-

-/*

- * PLL output frequency range check.

- */

-#if (STM32_PLL_P_CLKOUT < STM32_PLLOUT_MIN) || (STM32_PLL_P_CLKOUT > STM32_PLLOUT_MAX)

-#error "STM32_PLL_P_CLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"

+#if ((STM32_PLL1_DIVN_VALUE >= 4) && (STM32_PLL1_DIVN_VALUE <= 512)) ||    \

+    defined(__DOXYGEN__)

+#define STM32_PLL1_DIVN             ((STM32_PLL1_DIVN_VALUE - 1U) << 0U)

+#else

+#error "invalid STM32_PLL1_DIVN_VALUE value specified"

 #endif

 

 /**

- * @brief   System clock source.

+ * @brief   PLL2 DIVN field.

  */

-#if STM32_NO_INIT || defined(__DOXYGEN__)

-#define STM32_SYSCLK                STM32_HSICLK

-

-#elif (STM32_SW == STM32_SW_HSI_CK)

-#define STM32_SYSCLK                STM32_HSICLK

-

-#elif (STM32_SW == STM32_SW_HSE_CK)

-#define STM32_SYSCLK                STM32_HSECLK

-

-#elif (STM32_SW == STM32_SW_PLL1_P_CK)

-#define STM32_SYSCLK                STM32_PLL_P_CLKOUT

-

+#if ((STM32_PLL2_DIVN_VALUE >= 4) && (STM32_PLL2_DIVN_VALUE <= 512)) ||    \

+    defined(__DOXYGEN__)

+#define STM32_PLL2_DIVN             ((STM32_PLL2_DIVN_VALUE - 1U) << 0U)

 #else

-#error "invalid STM32_SW value specified"

+#error "invalid STM32_PLL2_DIVN_VALUE value specified"

 #endif

 

-/* Check on the system clock.*/

-#if STM32_SYSCLK > STM32_SYSCLK_MAX

-#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"

+/**

+ * @brief   PLL3 DIVN field.

+ */

+#if ((STM32_PLL3_DIVN_VALUE >= 4) && (STM32_PLL3_DIVN_VALUE <= 512)) ||    \

+    defined(__DOXYGEN__)

+#define STM32_PLL3_DIVN             ((STM32_PLL3_DIVN_VALUE - 1U) << 0U)

+#else

+#error "invalid STM32_PLL3_DIVN_VALUE value specified"

 #endif

 

-/* Calculating VOS settings.*/

-#if STM32_SYSCLK <= 144000000

-#define STM32_VOS                   STM32_VOS_SCALE3

-#define STM32_OVERDRIVE_REQUIRED    FALSE

-

-#elif STM32_SYSCLK <= 168000000

-#define STM32_VOS                   STM32_VOS_SCALE2

-#define STM32_OVERDRIVE_REQUIRED    FALSE

-

-#elif STM32_SYSCLK <= 180000000

-#define STM32_VOS                   STM32_VOS_SCALE1

-#define STM32_OVERDRIVE_REQUIRED    FALSE

-

+/**

+ * @brief   PLL1 FRACN field.

+ */

+#if ((STM32_PLL1_FRACN_VALUE >= 0) && (STM32_PLL1_FRACN_VALUE <= 8191)) ||  \

+    defined(__DOXYGEN__)

+#define STM32_PLL1_FRACN             (STM32_PLL1_FRACN_VALUE << 3U)

 #else

-#define STM32_VOS                   STM32_VOS_SCALE1

-#define STM32_OVERDRIVE_REQUIRED    TRUE

+#error "invalid STM32_PLL1_FRACN_VALUE value specified"

 #endif

 

 /**

- * @brief   AHB frequency.

+ * @brief   PLL2 FRACN field.

  */

-#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)

-#define STM32_HCLK                  (STM32_SYSCLK / 1)

-

-#elif STM32_HPRE == STM32_HPRE_DIV2

-#define STM32_HCLK                  (STM32_SYSCLK / 2)

-

-#elif STM32_HPRE == STM32_HPRE_DIV4

-#define STM32_HCLK                  (STM32_SYSCLK / 4)

-

-#elif STM32_HPRE == STM32_HPRE_DIV8

-#define STM32_HCLK                  (STM32_SYSCLK / 8)

-

-#elif STM32_HPRE == STM32_HPRE_DIV16

-#define STM32_HCLK                  (STM32_SYSCLK / 16)

-

-#elif STM32_HPRE == STM32_HPRE_DIV64

-#define STM32_HCLK                  (STM32_SYSCLK / 64)

-

-#elif STM32_HPRE == STM32_HPRE_DIV128

-#define STM32_HCLK                  (STM32_SYSCLK / 128)

-

-#elif STM32_HPRE == STM32_HPRE_DIV256

-#define STM32_HCLK                  (STM32_SYSCLK / 256)

-

-#elif STM32_HPRE == STM32_HPRE_DIV512

-#define STM32_HCLK                  (STM32_SYSCLK / 512)

-

+#if ((STM32_PLL2_FRACN_VALUE >= 0) && (STM32_PLL2_FRACN_VALUE <= 8191)) ||  \

+    defined(__DOXYGEN__)

+#define STM32_PLL2_FRACN             (STM32_PLL2_FRACN_VALUE << 3U)

 #else

-#error "invalid STM32_HPRE value specified"

+#error "invalid STM32_PLL2_FRACN_VALUE value specified"

 #endif

 

-/*

- * AHB frequency check.

+/**

+ * @brief   PLL3 FRACN field.

  */

-#if STM32_HCLK > STM32_SYSCLK_MAX

-#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"

+#if ((STM32_PLL3_FRACN_VALUE >= 0) && (STM32_PLL3_FRACN_VALUE <= 8191)) ||  \

+    defined(__DOXYGEN__)

+#define STM32_PLL3_FRACN             (STM32_PLL3_FRACN_VALUE << 3U)

+#else

+#error "invalid STM32_PLL3_FRACN_VALUE value specified"

 #endif

 

 /**

- * @brief   APB1 frequency.

+ * @brief   PLL1 DIVP field.

  */

-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)

-#define STM32_PCLK1                 (STM32_HCLK / 1)

-

-#elif STM32_PPRE1 == STM32_PPRE1_DIV2

-#define STM32_PCLK1                 (STM32_HCLK / 2)

-

-#elif STM32_PPRE1 == STM32_PPRE1_DIV4

-#define STM32_PCLK1                 (STM32_HCLK / 4)

-

-#elif STM32_PPRE1 == STM32_PPRE1_DIV8

-#define STM32_PCLK1                 (STM32_HCLK / 8)

-

-#elif STM32_PPRE1 == STM32_PPRE1_DIV16

-#define STM32_PCLK1                 (STM32_HCLK / 16)

-

+#if ((STM32_PLL1_DIVP_VALUE >= 2) && (STM32_PLL1_DIVP_VALUE <= 128) &&      \

+     ((STM32_PLL1_DIVP_VALUE & 1U) == 0U)) ||                               \

+    defined(__DOXYGEN__)

+#define STM32_PLL1_DIVP             ((STM32_PLL1_DIVP_VALUE - 1U) << 9U)

 #else

-#error "invalid STM32_PPRE1 value specified"

+#error "invalid STM32_PLL1_DIVP_VALUE value specified"

 #endif

 

-/*

- * APB1 frequency check.

+/**

+ * @brief   PLL2 DIVP field.

  */

-#if STM32_PCLK1 > STM32_PCLK1_MAX

-#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"

+#if ((STM32_PLL2_DIVP_VALUE >= 2) && (STM32_PLL2_DIVP_VALUE <= 128) &&      \

+     ((STM32_PLL2_DIVP_VALUE & 1U) == 0U)) ||                               \

+    defined(__DOXYGEN__)

+#define STM32_PLL2_DIVP             ((STM32_PLL2_DIVP_VALUE - 1U) << 9U)

+#else

+#error "invalid STM32_PLL2_DIVP_VALUE value specified"

 #endif

 

 /**

- * @brief   APB2 frequency.

+ * @brief   PLL3 DIVP field.

  */

-#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)

-#define STM32_PCLK2                 (STM32_HCLK / 1)

-

-#elif STM32_PPRE2 == STM32_PPRE2_DIV2

-#define STM32_PCLK2                 (STM32_HCLK / 2)

-

-#elif STM32_PPRE2 == STM32_PPRE2_DIV4

-#define STM32_PCLK2                 (STM32_HCLK / 4)

-

-#elif STM32_PPRE2 == STM32_PPRE2_DIV8

-#define STM32_PCLK2                 (STM32_HCLK / 8)

-

-#elif STM32_PPRE2 == STM32_PPRE2_DIV16

-#define STM32_PCLK2                 (STM32_HCLK / 16)

-

+#if ((STM32_PLL3_DIVP_VALUE >= 2) && (STM32_PLL3_DIVP_VALUE <= 128) &&      \

+     ((STM32_PLL3_DIVP_VALUE & 1U) == 0U)) ||                               \

+    defined(__DOXYGEN__)

+#define STM32_PLL3_DIVP             ((STM32_PLL3_DIVP_VALUE - 1U) << 9U)

 #else

-#error "invalid STM32_PPRE2 value specified"

+#error "invalid STM32_PLL3_DIVP_VALUE value specified"

 #endif

 

-/*

- * APB2 frequency check.

+/**

+ * @brief   PLL1 DIVQ field.

  */

-#if STM32_PCLK2 > STM32_PCLK2_MAX

-#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"

+#if ((STM32_PLL1_DIVQ_VALUE >= 1) && (STM32_PLL1_DIVQ_VALUE <= 128)) ||     \

+    defined(__DOXYGEN__)

+#define STM32_PLL1_DIVQ             ((STM32_PLL1_DIVQ_VALUE - 1U) << 16U)

+#else

+#error "invalid STM32_PLL1_DIVQ_VALUE value specified"

 #endif

 

-/*

- * PLLI2S enable check.

+/**

+ * @brief   PLL2 DIVQ field.

  */

-#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) ||                                \

-    (STM32_SAI1SEL == STM32_SAI1SEL_I2SPLL) ||                              \

-    (STM32_SAI2SEL == STM32_SAI2SEL_I2SPLL) ||                              \

+#if ((STM32_PLL2_DIVQ_VALUE >= 1) && (STM32_PLL2_DIVQ_VALUE <= 128)) ||     \

     defined(__DOXYGEN__)

+#define STM32_PLL2_DIVQ             ((STM32_PLL2_DIVQ_VALUE - 1U) << 16U)

+#else

+#error "invalid STM32_PLL2_DIVQ_VALUE value specified"

+#endif

+

 /**

- * @brief   PLLI2S activation flag.

+ * @brief   PLL3 DIVQ field.

  */

-#define STM32_ACTIVATE_PLLI2S       TRUE

+#if ((STM32_PLL3_DIVQ_VALUE >= 1) && (STM32_PLL3_DIVQ_VALUE <= 128)) ||     \

+    defined(__DOXYGEN__)

+#define STM32_PLL3_DIVQ             ((STM32_PLL3_DIVQ_VALUE - 1U) << 16U)

 #else

-#define STM32_ACTIVATE_PLLI2S       FALSE

+#error "invalid STM32_PLL3_DIVQ_VALUE value specified"

 #endif

 

 /**

- * @brief   STM32_PLLI2SN field.

+ * @brief   PLL1 DIVR field.

  */

-#if ((STM32_PLLI2SN_VALUE >= 49) && (STM32_PLLI2SN_VALUE <= 432)) ||       \

+#if ((STM32_PLL1_DIVR_VALUE >= 1) && (STM32_PLL1_DIVR_VALUE <= 128)) ||     \

     defined(__DOXYGEN__)

-#define STM32_PLLI2SN               (STM32_PLLI2SN_VALUE << 6)

+#define STM32_PLL1_DIVR             ((STM32_PLL1_DIVR_VALUE - 1U) << 24U)

 #else

-#error "invalid STM32_PLLI2SN_VALUE value specified"

+#error "invalid STM32_PLL1_DIVR_VALUE value specified"

 #endif

 

 /**

- * @brief   STM32_PLLI2SQ field.

+ * @brief   PLL2 DIVR field.

  */

-#if ((STM32_PLLI2SQ_VALUE >= 2) && (STM32_PLLI2SQ_VALUE <= 15)) ||          \

+#if ((STM32_PLL2_DIVR_VALUE >= 1) && (STM32_PLL2_DIVR_VALUE <= 128)) ||     \

     defined(__DOXYGEN__)

-#define STM32_PLLI2SQ               (STM32_PLLI2SQ_VALUE << 24)

+#define STM32_PLL2_DIVR             ((STM32_PLL2_DIVR_VALUE - 1U) << 24U)

 #else

-#error "invalid STM32_PLLI2SQ_VALUE value specified"

+#error "invalid STM32_PLL2_DIVR_VALUE value specified"

 #endif

 

 /**

- * @brief   STM32_PLLI2SR field.

+ * @brief   PLL3 DIVR field.

  */

-#if ((STM32_PLLI2SR_VALUE >= 2) && (STM32_PLLI2SR_VALUE <= 7)) ||           \

+#if ((STM32_PLL3_DIVR_VALUE >= 1) && (STM32_PLL3_DIVR_VALUE <= 128)) ||     \

     defined(__DOXYGEN__)

-#define STM32_PLLI2SR               (STM32_PLLI2SR_VALUE << 28)

+#define STM32_PLL3_DIVR             ((STM32_PLL3_DIVR_VALUE - 1U) << 24U)

 #else

-#error "invalid STM32_PLLI2SR_VALUE value specified"

+#error "invalid STM32_PLL3_DIVR_VALUE value specified"

 #endif

 

 /**

- * @brief   STM32_PLLI2SP field.

+ * @brief   PLL1 VCO frequency.

  */

-#if (STM32_PLLI2SP_VALUE == 2) || defined(__DOXYGEN__)

-#define STM32_PLLI2SP               (0 << 16)

+#define STM32_PLL1_VCO_CK           (STM32_PLL1_REF_CK * STM32_PLL1_DIVN_VALUE)

 

-#elif STM32_PLLI2SP_VALUE == 4

-#define STM32_PLLI2SP               (1 << 16)

-

-#elif STM32_PLLI2SP_VALUE == 6

-#define STM32_PLLI2SP               (2 << 16)

-

-#elif STM32_PLLI2SP_VALUE == 8

-#define STM32_PLLI2SP               (3 << 16)

+/*

+ * PLL1 VCO frequency range check.

+ */

+#if (STM32_PLL1_VCO_CK < STM32_PLLVCO_MIN) || (STM32_PLL1_VCO_CK > STM32_PLLVCO_MAX)

+#error "STM32_PLL1_VCO_CK outside acceptable range (STM32_PLLVCO_MIN..STM32_PLLVCO_MAX)"

+#endif

 

+/*

+ * PLL1 VCO mode.

+ */

+#if (STM32_PLL1_VCO_CK > STM32_PLLVCO_THRESHOLD) || defined(__DOXYGEN__)

+#define STM32_PLLCFGR_PLL1VCOSEL    0U

 #else

-#error "invalid STM32_PLLI2SP_VALUE value specified"

+#define STM32_PLLCFGR_PLL1VCOSEL    RCC_PLLCFGR_PLL1VCOSEL

 #endif

 

 /**

- * @brief   PLLI2S VCO frequency.

+ * @brief   PLL2 VCO frequency.

  */

-#define STM32_PLLI2SVCO             (STM32_PLLCLKIN * STM32_PLLI2SN_VALUE)

+#define STM32_PLL2_VCO_CK           (STM32_PLL2_REF_CK * STM32_PLL2_DIVN_VALUE)

 

 /*

- * PLLI2S VCO frequency range check.

+ * PLL2 VCO frequency range check.

  */

-#if (STM32_PLLI2SVCO < STM32_PLLVCO_MIN) ||                                 \

-    (STM32_PLLI2SVCO > STM32_PLLVCO_MAX)

-#error "STM32_PLLI2SVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"

+#if (STM32_PLL2_VCO_CK < STM32_PLLVCO_MIN) || (STM32_PLL2_VCO_CK > STM32_PLLVCO_MAX)

+#error "STM32_PLL2_VCO_CK outside acceptable range (STM32_PLLVCO_MIN..STM32_PLLVCO_MAX)"

 #endif

 

-/**

- * @brief   PLLI2S P output clock frequency.

+/*

+ * PLL2 VCO mode.

  */

-#define STM32_PLLI2S_P_CLKOUT       (STM32_PLLI2SVCO / STM32_PLLI2SP_VALUE)

+#if (STM32_PLL2_VCO_CK > STM32_PLLVCO_THRESHOLD) || defined(__DOXYGEN__)

+#define STM32_PLLCFGR_PLL2VCOSEL    0U

+#else

+#define STM32_PLLCFGR_PLL2VCOSEL    RCC_PLLCFGR_PLL2VCOSEL

+#endif

 

 /**

- * @brief   PLLI2S Q output clock frequency.

+ * @brief   PLL3 VCO frequency.

  */

-#define STM32_PLLI2S_Q_CLKOUT       (STM32_PLLI2SVCO / STM32_PLLI2SQ_VALUE)

+#define STM32_PLL3_VCO_CK           (STM32_PLL3_REF_CK * STM32_PLL3_DIVN_VALUE)

 

-/**

- * @brief   PLLI2S R output clock frequency.

+/*

+ * PLL3 VCO frequency range check.

  */

-#define STM32_PLLI2S_R_CLKOUT       (STM32_PLLI2SVCO / STM32_PLLI2SR_VALUE)

+#if (STM32_PLL3_VCO_CK < STM32_PLLVCO_MIN) || (STM32_PLL3_VCO_CK > STM32_PLLVCO_MAX)

+#error "STM32_PLL3_VCO_CK outside acceptable range (STM32_PLLVCO_MIN..STM32_PLLVCO_MAX)"

+#endif

 

-/**

- * @brief   STM32_PLLI2SDIVQ field.

+/*

+ * PLL3 VCO mode.

  */

-#if (STM32_PLLI2SDIVQ_VALUE < 1) || (STM32_PLLI2SDIVQ_VALUE > 32)

-#error "STM32_PLLI2SDIVQ_VALUE out of acceptable range"

+#if (STM32_PLL3_VCO_CK > STM32_PLLVCO_THRESHOLD) || defined(__DOXYGEN__)

+#define STM32_PLLCFGR_PLL3VCOSEL    0U

+#else

+#define STM32_PLLCFGR_PLL3VCOSEL    RCC_PLLCFGR_PLL3VCOSEL

 #endif

-#define STM32_PLLI2SDIVQ            ((STM32_PLLI2SDIVQ_VALUE - 1) << 0)

 

 /**

- * @brief   PLLI2S Q output clock frequency after divisor.

+ * @brief   PLL1 P output clock frequency.

  */

-#define STM32_PLLI2SDIVQ_CLKOUT     (STM32_PLLI2S_Q_CLKOUT / STM32_PLLI2SDIVQ_VALUE)

+#define STM32_PLL1_P_CK             (STM32_PLL1_VCO_CK / STM32_PLL1_DIVP_VALUE)

 

 /*

- * PLLSAI enable check.

+ * PLL1 P output frequency range check.

  */

-#if (STM32_CLOCK48_REQUIRED && (STM32_CK48MSEL == STM32_CK48MSEL_PLLSAI)) | \

-    STM32_LCDTFT_REQUIRED ||                                                \

-    (STM32_SAI1SEL == STM32_SAI1SEL_SAIPLL) ||                              \

-    (STM32_SAI2SEL == STM32_SAI2SEL_SAIPLL) ||                              \

-    defined(__DOXYGEN__)

-/**

- * @brief   PLLSAI activation flag.

- */

-#define STM32_ACTIVATE_PLLSAI       TRUE

-#else

-#define STM32_ACTIVATE_PLLSAI       FALSE

+#if (STM32_PLL1_P_CK < STM32_PLLOUT_MIN) || (STM32_PLL1_P_CK > STM32_PLLOUT_MAX)

+#error "STM32_PLL1_P_CLKOUT outside acceptable range (STM32_PLLOUT_MIN..STM32_PLLOUT_MAX)"

 #endif

 

 /**

- * @brief   STM32_PLLSAIN field.

+ * @brief   PLL2 P output clock frequency.

  */

-#if ((STM32_PLLSAIN_VALUE >= 49) && (STM32_PLLSAIN_VALUE <= 432)) ||        \

-    defined(__DOXYGEN__)

-#define STM32_PLLSAIN               (STM32_PLLSAIN_VALUE << 6)

-#else

-#error "invalid STM32_PLLSAIN_VALUE value specified"

+#define STM32_PLL2_P_CK             (STM32_PLL2_VCO_CK / STM32_PLL2_DIVP_VALUE)

+

+/*

+ * PLL2 P output frequency range check.

+ */

+#if (STM32_PLL2_P_CK < STM32_PLLOUT_MIN) || (STM32_PLL2_P_CK > STM32_PLLOUT_MAX)

+#error "STM32_PLL2_P_CLKOUT outside acceptable range (STM32_PLLOUT_MIN..STM32_PLLOUT_MAX)"

 #endif

 

 /**

- * @brief   STM32_PLLSAIQ field.

+ * @brief   PLL3 P output clock frequency.

  */

-#if ((STM32_PLLSAIQ_VALUE >= 2) && (STM32_PLLSAIQ_VALUE <= 15)) ||          \

-    defined(__DOXYGEN__)

-#define STM32_PLLSAIQ               (STM32_PLLSAIQ_VALUE << 24)

-#else

-#error "invalid STM32_PLLSAIR_VALUE value specified"

+#define STM32_PLL3_P_CK             (STM32_PLL3_VCO_CK / STM32_PLL3_DIVP_VALUE)

+

+/*

+ * PLL3 P output frequency range check.

+ */

+#if (STM32_PLL3_P_CK < STM32_PLLOUT_MIN) || (STM32_PLL3_P_CK > STM32_PLLOUT_MAX)

+#error "STM32_PLL3_P_CLKOUT outside acceptable range (STM32_PLLOUT_MIN..STM32_PLLOUT_MAX)"

 #endif

 

 /**

- * @brief   STM32_PLLSAIR field.

+ * @brief   PLL1 Q output clock frequency.

  */

-#if ((STM32_PLLSAIR_VALUE >= 2) && (STM32_PLLSAIR_VALUE <= 7)) ||           \

-    defined(__DOXYGEN__)

-#define STM32_PLLSAIR               (STM32_PLLSAIR_VALUE << 28)

-#else

-#error "invalid STM32_PLLSAIR_VALUE value specified"

+#define STM32_PLL1_Q_CK             (STM32_PLL1_VCO_CK / STM32_PLL1_DIVQ_VALUE)

+

+/*

+ * PLL1 Q output frequency range check.

+ */

+#if (STM32_PLL1_Q_CK < STM32_PLLOUT_MIN) || (STM32_PLL1_Q_CK > STM32_PLLOUT_MAX)

+#error "STM32_PLL1_Q_CLKOUT outside acceptable range (STM32_PLLOUT_MIN..STM32_PLLOUT_MAX)"

 #endif

 

 /**

- * @brief   STM32_PLLSAIP field.

+ * @brief   PLL2 Q output clock frequency.

  */

-#if (STM32_PLLSAIP_VALUE == 2) || defined(__DOXYGEN__)

-#define STM32_PLLSAIP               (0 << 16)

-

-#elif STM32_PLLSAIP_VALUE == 4

-#define STM32_PLLSAIP               (1 << 16)

+#define STM32_PLL2_Q_CK             (STM32_PLL2_VCO_CK / STM32_PLL2_DIVQ_VALUE)

 

-#elif STM32_PLLSAIP_VALUE == 6

-#define STM32_PLLSAIP               (2 << 16)

+/*

+ * PLL2 Q output frequency range check.

+ */

+#if (STM32_PLL2_Q_CK < STM32_PLLOUT_MIN) || (STM32_PLL2_Q_CK > STM32_PLLOUT_MAX)

+#error "STM32_PLL2_Q_CLKOUT outside acceptable range (STM32_PLLOUT_MIN..STM32_PLLOUT_MAX)"

+#endif

 

-#elif STM32_PLLSAIP_VALUE == 8

-#define STM32_PLLSAIP               (3 << 16)

+/**

+ * @brief   PLL3 Q output clock frequency.

+ */

+#define STM32_PLL3_Q_CK             (STM32_PLL3_VCO_CK / STM32_PLL3_DIVQ_VALUE)

 

-#else

-#error "invalid STM32_PLLSAIP_VALUE value specified"

+/*

+ * PLL3 Q output frequency range check.

+ */

+#if (STM32_PLL3_Q_CK < STM32_PLLOUT_MIN) || (STM32_PLL3_Q_CK > STM32_PLLOUT_MAX)

+#error "STM32_PLL3_Q_CLKOUT outside acceptable range (STM32_PLLOUT_MIN..STM32_PLLOUT_MAX)"

 #endif

 

 /**

- * @brief   PLLSAI VCO frequency.

+ * @brief   PLL1 R output clock frequency.

  */

-#define STM32_PLLSAIVCO             (STM32_PLLCLKIN * STM32_PLLSAIN_VALUE)

+#define STM32_PLL1_R_CK             (STM32_PLL1_VCO_CK / STM32_PLL1_DIVR_VALUE)

 

 /*

- * PLLSAI VCO frequency range check.

+ * PLL1 R output frequency range check.

  */

-#if (STM32_PLLSAIVCO < STM32_PLLVCO_MIN) ||                                 \

-    (STM32_PLLSAIVCO > STM32_PLLVCO_MAX)

-#error "STM32_PLLSAIVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"

+#if (STM32_PLL1_R_CK < STM32_PLLOUT_MIN) || (STM32_PLL1_R_CK > STM32_PLLOUT_MAX)

+#error "STM32_PLL1_R_CLKOUT outside acceptable range (STM32_PLLOUT_MIN..STM32_PLLOUT_MAX)"

 #endif

 

 /**

- * @brief   PLLSAI P output clock frequency.

+ * @brief   PLL2 R output clock frequency.

  */

-#define STM32_PLLSAI_P_CLKOUT       (STM32_PLLSAIVCO / STM32_PLLSAIP_VALUE)

+#define STM32_PLL2_R_CK             (STM32_PLL2_VCO_CK / STM32_PLL2_DIVR_VALUE)

 

-/**

- * @brief   PLLSAI Q output clock frequency.

+/*

+ * PLL2 R output frequency range check.

  */

-#define STM32_PLLSAI_Q_CLKOUT       (STM32_PLLSAIVCO / STM32_PLLSAIQ_VALUE)

+#if (STM32_PLL2_R_CK < STM32_PLLOUT_MIN) || (STM32_PLL2_R_CK > STM32_PLLOUT_MAX)

+#error "STM32_PLL2_R_CLKOUT outside acceptable range (STM32_PLLOUT_MIN..STM32_PLLOUT_MAX)"

+#endif

 

 /**

- * @brief   PLLSAI R output clock frequency.

+ * @brief   PLL3 R output clock frequency.

  */

-#define STM32_PLLSAI_R_CLKOUT       (STM32_PLLSAIVCO / STM32_PLLSAIR_VALUE)

+#define STM32_PLL3_R_CK             (STM32_PLL3_VCO_CK / STM32_PLL3_DIVR_VALUE)

 

-/**

- * @brief   STM32_PLLSAIDIVQ field.

+/*

+ * PLL3 R output frequency range check.

  */

-#if (STM32_PLLSAIDIVQ_VALUE < 1) || (STM32_PLLSAIDIVQ_VALUE > 32)

-#error "STM32_PLLSAIDIVQ_VALUE out of acceptable range"

+#if (STM32_PLL3_R_CK < STM32_PLLOUT_MIN) || (STM32_PLL3_R_CK > STM32_PLLOUT_MAX)

+#error "STM32_PLL3_R_CLKOUT outside acceptable range (STM32_PLLOUT_MIN..STM32_PLLOUT_MAX)"

 #endif

-#define STM32_PLLSAIDIVQ            ((STM32_PLLSAIDIVQ_VALUE - 1) << 8)

 

 /**

- * @brief   PLLSAI Q output clock frequency after divisor.

+ * @brief   System clock source.

  */

-#define STM32_PLLSAIDIVQ_CLKOUT     (STM32_PLLSAI_Q_CLKOUT / STM32_PLLSAIDIVQ_VALUE)

+#if STM32_NO_INIT || defined(__DOXYGEN__)

+#define STM32_SYS_CK                STM32_SYS_CK_ENFORCED_VALUE

+

+#elif (STM32_SW == STM32_SW_HSI_CK)

+#define STM32_SYS_CK                STM32_HSI_CK

+

+#elif (STM32_SW == STM32_SW_CSI_CK)

+#define STM32_SYS_CK                STM32_CSICLK

+

+#elif (STM32_SW == STM32_SW_HSE_CK)

+#define STM32_SYS_CK                STM32_HSECLK

+

+#elif (STM32_SW == STM32_SW_PLL1_P_CK)

+#define STM32_SYS_CK                STM32_PLL1_P_CK

+

+#else

+#error "invalid STM32_SW value specified"

+#endif

 

 /*

- * STM32_PLLSAIDIVR field.

+ * Check on the system clock.

  */

-#if (STM32_PLLSAIDIVR_VALUE == 2) || defined(__DOXYGEN__)

-#define STM32_PLLSAIDIVR            (0 << 16)

+#if STM32_SW > STM32_SYSCLK_MAX

+#error "STM32_SYS_CK above maximum rated frequency (STM32_SYSCLK_MAX)"

+#endif

 

-#elif STM32_PLLSAIDIVR_VALUE == 4

-#define STM32_PLLSAIDIVR            (1 << 16)

+/**

+ * @brief   Peripherals clock source.

+ */

+#if (STM32_CKPERSEL == STM32_CKPERSEL_HSI_CK) || defined(__DOXYGEN__)

+#define STM32_PER_CK                STM32_HSI_CK

 

-#elif STM32_PLLSAIDIVR_VALUE == 8

-#define STM32_PLLSAIDIVR            (2 << 16)

+#elif (STM32_CKPERSEL == STM32_CKPERSEL_CSI_CK)

+#define STM32_PER_CK                STM32_CSICLK

 

-#elif STM32_PLLSAIDIVR_VALUE == 16

-#define STM32_PLLSAIDIVR            (3 << 16)

+#elif (STM32_CKPERSEL == STM32_CKPERSEL_HSE_CK)

+#define STM32_PER_CK                STM32_HSECLK

 

 #else

-#error "invalid STM32_PLLSAIDIVR_VALUE value specified"

+#error "invalid STM32_CKPERSEL value specified"

 #endif

 

-/**

- * @brief   PLLSAI R output clock frequency after divisor.

+/*

+ * Check on the peripherals clock.

  */

-#define STM32_PLLSAIDIVR_CLKOUT       (STM32_PLLSAI_R_CLKOUT / STM32_PLLSAIDIVR_VALUE)

+#if STM32_PER_CK > STM32_HCLK_MAX

+#error "STM32_PER_CK above maximum rated frequency (STM32_HCLK_MAX)"

+#endif

 

 /**

  * @brief   MCO1 divider clock.

  */

-#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || defined(__DOXYGEN__)

-#define STM32_MCO1DIVCLK            STM32_HSICLK

+#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI_CK) || defined(__DOXYGEN__)

+#define STM32_MCO1DIVCLK            STM32_HSI_CK

 

-#elif STM32_MCO1SEL == STM32_MCO1SEL_LSE

+#elif STM32_MCO1SEL == STM32_MCO1SEL_LSE_CK

 #define STM32_MCO1DIVCLK            STM32_LSECLK

 

-#elif STM32_MCO1SEL == STM32_MCO1SEL_HSE

+#elif STM32_MCO1SEL == STM32_MCO1SEL_HSE_CK

 #define STM32_MCO1DIVCLK            STM32_HSECLK

 

-#elif STM32_MCO1SEL == STM32_MCO1SEL_PLL

-#define STM32_MCO1DIVCLK            STM32_PLL_P_CLKOUT

+#elif STM32_MCO1SEL == STM32_MCO1SEL_PLL1_Q_CK

+#define STM32_MCO1DIVCLK            STM32_PLL1_P_CK

+

+#elif STM32_MCO1SEL == STM32_MCO1SEL_HSI48_CK

+#define STM32_MCO1DIVCLK            STM32_HSI48CLK

 

 #else

 #error "invalid STM32_MCO1SEL value specified"

@@ -1660,39 +1748,30 @@
 /**

  * @brief   MCO1 output pin clock.

  */

-#if (STM32_MCO1PRE == STM32_MCO1PRE_DIV1) || defined(__DOXYGEN__)

-#define STM32_MCO1CLK               STM32_MCO1DIVCLK

-

-#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV2

-#define STM32_MCO1CLK               (STM32_MCO1DIVCLK / 2)

-

-#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV3

-#define STM32_MCO1CLK               (STM32_MCO1DIVCLK / 3)

-

-#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV4

-#define STM32_MCO1CLK               (STM32_MCO1DIVCLK / 4)

-

-#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV5

-#define STM32_MCO1CLK               (STM32_MCO1DIVCLK / 5)

-

-#else

-#error "invalid STM32_MCO1PRE value specified"

+#if (STM32_MCO1PRE_VALUE < 1) || (STM32_MCO1PRE_VALUE > 15)

+#error "STM32_MCO1PRE_VALUE outside acceptable range (1..15)"

 #endif

 

 /**

  * @brief   MCO2 divider clock.

  */

-#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || defined(__DOXYGEN__)

+#if (STM32_MCO2SEL == STM32_MCO2SEL_SYS_CK) || defined(__DOXYGEN__)

+#define STM32_MCO2DIVCLK            STM32_SYS_CK

+

+#elif STM32_MCO2SEL == STM32_MCO2SEL_PLL1_P_CK

+#define STM32_MCO2DIVCLK            STM32_PLL2_P_CK

+

+#elif STM32_MCO2SEL == STM32_MCO2SEL_HSE_CK

 #define STM32_MCO2DIVCLK            STM32_HSECLK

 

-#elif STM32_MCO2SEL == STM32_MCO2SEL_PLL

-#define STM32_MCO2DIVCLK            STM32_PLL_P_CLKOUT

+#elif STM32_MCO2SEL == STM32_MCO2SEL_PLL2_P_CK

+#define STM32_MCO2DIVCLK            STM32_PLL2_P_CK

 

-#elif STM32_MCO2SEL == STM32_MCO2SEL_SYSCLK

-#define STM32_MCO2DIVCLK            STM32_SYSCLK

+#elif STM32_MCO2SEL == STM32_MCO2SEL_CSI_CK

+#define STM32_MCO2DIVCLK            STM32_CSICLK

 

-#elif STM32_MCO2SEL == STM32_MCO2SEL_PLLI2S

-#define STM32_MCO2DIVCLK            STM32_PLLI2S

+#elif STM32_MCO2SEL == STM32_MCO2SEL_LSI_CK

+#define STM32_MCO2DIVCLK            STM32_LSICLK

 

 #else

 #error "invalid STM32_MCO2SEL value specified"

@@ -1701,64 +1780,235 @@
 /**

  * @brief   MCO2 output pin clock.

  */

-#if (STM32_MCO2PRE == STM32_MCO2PRE_DIV1) || defined(__DOXYGEN__)

-#define STM32_MCO2CLK               STM32_MCO2DIVCLK

+#if (STM32_MCO2PRE_VALUE < 1) || (STM32_MCO2PRE_VALUE > 15)

+#error "STM32_MCO2PRE_VALUE outside acceptable range (1..15)"

+#endif

 

-#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV2

-#define STM32_MCO2CLK               (STM32_MCO2DIVCLK / 2)

+/**

+ * @brief   RTC clock.

+ */

+#if (STM32_RTCSEL == STM32_RTCSEL_NOCLK) || defined(__DOXYGEN__)

+#define STM32_RTC_CK                0

 

-#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV3

-#define STM32_MCO2CLK               (STM32_MCO2DIVCLK / 3)

+#elif STM32_RTCSEL == STM32_RTCSEL_LSE_CK

+#define STM32_RTC_CK                STM32_LSECLK

 

-#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV4

-#define STM32_MCO2CLK               (STM32_MCO2DIVCLK / 4)

+#elif STM32_RTCSEL == STM32_RTCSEL_LSI_CK

+#define STM32_RTC_CK                STM32_LSICLK

 

-#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV5

-#define STM32_MCO2CLK               (STM32_MCO2DIVCLK / 5)

+#elif STM32_RTCSEL == STM32_RTCSEL_HSE_1M_CK

+#define STM32_RTC_CK                STM32_HSE_1M_CK

 

 #else

-#error "invalid STM32_MCO2PRE value specified"

+#error "invalid STM32_RTCSEL value specified"

+#endif

+

+/*

+ * Check on the RTC clock.

+ */

+#if STM32_RTC_CK > 1000000

+#error "STM32_RTC_CK above maximum rated frequency (1000000)"

+#endif

+

+/**

+ * @brief   D1CPRE clock.

+ */

+#if (STM32_D1CPRE == STM32_D1CPRE_DIV1) || defined(__DOXYGEN__)

+#define STM32_SYS_D1CPRE_CK         (STM32_SYS_CK / 1U)

+#elif STM32_D1CPRE == STM32_D1CPRE_DIV2

+#define STM32_SYS_D1CPRE_CK         (STM32_SYS_CK / 2U)

+#elif STM32_D1CPRE == STM32_D1CPRE_DIV4

+#define STM32_SYS_D1CPRE_CK         (STM32_SYS_CK / 4U)

+#elif STM32_D1CPRE == STM32_D1CPRE_DIV8

+#define STM32_SYS_D1CPRE_CK         (STM32_SYS_CK / 8U)

+#elif STM32_D1CPRE == STM32_D1CPRE_DIV16

+#define STM32_SYS_D1CPRE_CK         (STM32_SYS_CK / 16U)

+#elif STM32_D1CPRE == STM32_D1CPRE_DIV64

+#define STM32_SYS_D1CPRE_CK         (STM32_SYS_CK / 64U)

+#elif STM32_D1CPRE == STM32_D1CPRE_DIV128

+#define STM32_SYS_D1CPRE_CK         (STM32_SYS_CK / 128U)

+#elif STM32_D1CPRE == STM32_D1CPRE_DIV256

+#define STM32_SYS_D1CPRE_CK         (STM32_SYS_CK / 256U)

+#elif STM32_D1CPRE == STM32_D1CPRE_DIV512

+#define STM32_SYS_D1CPRE_CK         (STM32_SYS_CK / 512U)

+#else

+#error "invalid STM32_D1CPRE value specified"

+#endif

+

+/**

+ * @brief   HCLK clock.

+ */

+#if (STM32_D1HPRE == STM32_D1HPRE_DIV1) || defined(__DOXYGEN__)

+#define STM32_HCLK                  (STM32_SYS_D1CPRE_CK / 1U)

+#elif STM32_D1HPRE == STM32_D1HPRE_DIV2

+#define STM32_HCLK                  (STM32_SYS_D1CPRE_CK / 2U)

+#elif STM32_D1HPRE == STM32_D1HPRE_DIV4

+#define STM32_HCLK                  (STM32_SYS_D1CPRE_CK / 4U)

+#elif STM32_D1HPRE == STM32_D1HPRE_DIV8

+#define STM32_HCLK                  (STM32_SYS_D1CPRE_CK / 8U)

+#elif STM32_D1HPRE == STM32_D1HPRE_DIV16

+#define STM32_HCLK                  (STM32_SYS_D1CPRE_CK / 16U)

+#elif STM32_D1HPRE == STM32_D1HPRE_DIV64

+#define STM32_HCLK                  (STM32_SYS_D1CPRE_CK / 64U)

+#elif STM32_D1HPRE == STM32_D1HPRE_DIV128

+#define STM32_HCLK                  (STM32_SYS_D1CPRE_CK / 128U)

+#elif STM32_D1HPRE == STM32_D1HPRE_DIV256

+#define STM32_HCLK                  (STM32_SYS_D1CPRE_CK / 256U)

+#elif STM32_D1HPRE == STM32_D1HPRE_DIV512

+#define STM32_HCLK                  (STM32_SYS_D1CPRE_CK / 512U)

+#else

+#error "invalid STM32_D1HPRE value specified"

+#endif

+

+/*

+ * AHB frequency check.

+ */

+#if STM32_HCLK > STM32_HCLK_MAX

+#error "STM32_HCLK exceeding maximum frequency (STM32_HCLK_MAX)"

 #endif

 

 /**

- * @brief   RTC HSE divider setting.

+ * @brief   D1 PCLK3 clock.

  */

-#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) ||            \

-    defined(__DOXYGEN__)

-#define STM32_RTCPRE                (STM32_RTCPRE_VALUE << 16)

+#if (STM32_D1PPRE3 == STM32_D1PPRE3_DIV1) || defined(__DOXYGEN__)

+#define STM32_PCLK3                 (STM32_HCLK / 1U)

+#elif STM32_D1PPRE3 == STM32_D1PPRE3_DIV2

+#define STM32_PCLK3                 (STM32_HCLK / 2U)

+#elif STM32_D1PPRE3 == STM32_D1PPRE3_DIV4

+#define STM32_PCLK3                 (STM32_HCLK / 4U)

+#elif STM32_D1PPRE3 == STM32_D1PPRE3_DIV8

+#define STM32_PCLK3                 (STM32_HCLK / 8U)

+#elif STM32_D1PPRE3 == STM32_D1PPRE3_DIV16

+#define STM32_PCLK3                 (STM32_HCLK / 16U)

 #else

-#error "invalid STM32_RTCPRE value specified"

+#error "invalid STM32_D1PPRE3 value specified"

+#endif

+

+/*

+ * D1 PCLK3 frequency check.

+ */

+#if STM32_PCLK3 > STM32_PCLK3_MAX

+#error "STM32_PCLK3 exceeding maximum frequency (STM32_PCLK3_MAX)"

 #endif

 

 /**

- * @brief   HSE divider toward RTC clock.

+ * @brief   D2 PCLK1 clock.

  */

-#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31))  ||           \

-    defined(__DOXYGEN__)

-#define STM32_HSEDIVCLK             (STM32_HSECLK / STM32_RTCPRE_VALUE)

+#if (STM32_D2PPRE1 == STM32_D2PPRE1_DIV1) || defined(__DOXYGEN__)

+#define STM32_PCLK1                 (STM32_HCLK / 1U)

+#elif STM32_D2PPRE1 == STM32_D2PPRE1_DIV2

+#define STM32_PCLK1                 (STM32_HCLK / 2U)

+#elif STM32_D2PPRE1 == STM32_D2PPRE1_DIV4

+#define STM32_PCLK1                 (STM32_HCLK / 4U)

+#elif STM32_D2PPRE1 == STM32_D2PPRE1_DIV8

+#define STM32_PCLK1                 (STM32_HCLK / 8U)

+#elif STM32_D2PPRE1 == STM32_D2PPRE1_DIV16

+#define STM32_PCLK1                 (STM32_HCLK / 16U)

 #else

-#error "invalid STM32_RTCPRE value specified"

+#error "invalid STM32_D2PPRE1 value specified"

+#endif

+

+/*

+ * D2 PCLK1 frequency check.

+ */

+#if STM32_PCLK1 > STM32_PCLK1_MAX

+#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"

 #endif

 

 /**

- * @brief   RTC clock.

+ * @brief   D2 PCLK2 clock.

  */

-#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)

-#define STM32_RTCCLK                0

+#if (STM32_D2PPRE2 == STM32_D2PPRE2_DIV1) || defined(__DOXYGEN__)

+#define STM32_PCLK2                 (STM32_HCLK / 1U)

+#elif STM32_D2PPRE2 == STM32_D2PPRE2_DIV2

+#define STM32_PCLK2                 (STM32_HCLK / 2U)

+#elif STM32_D2PPRE2 == STM32_D2PPRE2_DIV4

+#define STM32_PCLK2                 (STM32_HCLK / 4U)

+#elif STM32_D2PPRE2 == STM32_D2PPRE2_DIV8

+#define STM32_PCLK2                 (STM32_HCLK / 8U)

+#elif STM32_D2PPRE2 == STM32_D2PPRE2_DIV16

+#define STM32_PCLK2                 (STM32_HCLK / 16U)

+#else

+#error "invalid STM32_D2PPRE2 value specified"

+#endif

 

-#elif STM32_RTCSEL == STM32_RTCSEL_LSE

-#define STM32_RTCCLK                STM32_LSECLK

+/*

+ * D2 PCLK2 frequency check.

+ */

+#if STM32_PCLK2 > STM32_PCLK2_MAX

+#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"

+#endif

+

+/**

+ * @brief   D3 PCLK4 clock.

+ */

+#if (STM32_D3PPRE4 == STM32_D3PPRE4_DIV1) || defined(__DOXYGEN__)

+#define STM32_PCLK4                 (STM32_HCLK / 1U)

+#elif STM32_D3PPRE4 == STM32_D3PPRE4_DIV2

+#define STM32_PCLK4                 (STM32_HCLK / 2U)

+#elif STM32_D3PPRE4 == STM32_D3PPRE4_DIV4

+#define STM32_PCLK4                 (STM32_HCLK / 4U)

+#elif STM32_D3PPRE4 == STM32_D3PPRE4_DIV8

+#define STM32_PCLK4                 (STM32_HCLK / 8U)

+#elif STM32_D3PPRE4 == STM32_D3PPRE4_DIV16

+#define STM32_PCLK4                 (STM32_HCLK / 16U)

+#else

+#error "invalid STM32_D3PPRE4 value specified"

+#endif

 

-#elif STM32_RTCSEL == STM32_RTCSEL_LSI

-#define STM32_RTCCLK                STM32_LSICLK

+/*

+ * D3 PCLK4 frequency check.

+ */

+#if STM32_PCLK4 > STM32_PCLK4_MAX

+#error "STM32_PCLK4 exceeding maximum frequency (STM32_PCLK4_MAX)"

+#endif

 

-#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV

-#define STM32_RTCCLK                STM32_HSEDIVCLK

+/**

+ * @brief   Flash settings.

+ */

+#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)

+#define STM32_FLASHBITS             0x00000000

+

+#elif STM32_HCLK <= STM32_1WS_THRESHOLD

+#define STM32_FLASHBITS             0x00000001

+

+#elif STM32_HCLK <= STM32_2WS_THRESHOLD

+#define STM32_FLASHBITS             0x00000002

+

+#elif STM32_HCLK <= STM32_3WS_THRESHOLD

+#define STM32_FLASHBITS             0x00000003

+

+#elif STM32_HCLK <= STM32_4WS_THRESHOLD

+#define STM32_FLASHBITS             0x00000004

 

 #else

-#error "invalid STM32_RTCSEL value specified"

+#define STM32_FLASHBITS             0x00000007

 #endif

 

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+#if 0

 /**

  * @brief   USART1 frequency.

  */

@@ -2032,39 +2282,6 @@
 #else

 #define STM32_TIMCLK2               (STM32_PCLK2 * 2)

 #endif

-

-/**

- * @brief   Flash settings.

- */

-#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)

-#define STM32_FLASHBITS             0x00000000

-

-#elif STM32_HCLK <= STM32_1WS_THRESHOLD

-#define STM32_FLASHBITS             0x00000001

-

-#elif STM32_HCLK <= STM32_2WS_THRESHOLD

-#define STM32_FLASHBITS             0x00000002

-

-#elif STM32_HCLK <= STM32_3WS_THRESHOLD

-#define STM32_FLASHBITS             0x00000003

-

-#elif STM32_HCLK <= STM32_4WS_THRESHOLD

-#define STM32_FLASHBITS             0x00000004

-

-#elif STM32_HCLK <= STM32_5WS_THRESHOLD

-#define STM32_FLASHBITS             0x00000005

-

-#elif STM32_HCLK <= STM32_6WS_THRESHOLD

-#define STM32_FLASHBITS             0x00000006

-

-#elif STM32_HCLK <= STM32_7WS_THRESHOLD

-#define STM32_FLASHBITS             0x00000007

-

-#elif STM32_HCLK <= STM32_8WS_THRESHOLD

-#define STM32_FLASHBITS             0x00000008

-

-#else

-#define STM32_FLASHBITS             0x00000009

 #endif

 

 /*===========================================================================*/

@@ -2083,7 +2300,7 @@
 #include "nvic.h"

 #include "mpu.h"

 #include "stm32_isr.h"

-#include "stm32_dma.h"

+//#include "stm32_dma.h"

 #include "stm32_rcc.h"

 

 #ifdef __cplusplus

diff --git a/os/hal/ports/STM32/STM32H7xx/platform.mk b/os/hal/ports/STM32/STM32H7xx/platform.mk
index fbe8dfe69..6f8969233 100644
--- a/os/hal/ports/STM32/STM32H7xx/platform.mk
+++ b/os/hal/ports/STM32/STM32H7xx/platform.mk
@@ -1,7 +1,7 @@
 # Required platform files.

 PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \

-               $(CHIBIOS)/os/hal/ports/STM32/STM32H7xx/stm32_isr.c \

                $(CHIBIOS)/os/hal/ports/STM32/STM32H7xx/hal_lld.c

+#               $(CHIBIOS)/os/hal/ports/STM32/STM32H7xx/stm32_isr.c \

 

 # Required include directories.

 PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \