git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5151 35acf78f-673a-0410-8e92-d51de3d6d3f4

2 files changed, 58 insertions, 41 deletions

diff --git a/os/hal/platforms/SPC56ELxx/hal_lld.c b/os/hal/platforms/SPC56ELxx/hal_lld.c
index 3e52ea1ff..a6bf31dc8 100644
--- a/os/hal/platforms/SPC56ELxx/hal_lld.c
+++ b/os/hal/platforms/SPC56ELxx/hal_lld.c
@@ -50,12 +50,24 @@
  */

 void hal_lld_init(void) {

   extern void _vectors(void);

+  uint32_t n;

 

   /* The system is switched to the RUN0 mode, the default for normal

      operations.*/

   if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == CH_FAILED)

     chSysHalt();

 

+  /* Down-counter timer initialized for system tick use, TB enabled for debug

+     and measurements.*/

+  n = halSPCGetSystemClock() / CH_FREQUENCY;

+  asm volatile ("mtspr   22, %[n]           \t\n"   /* Init. DEC register.  */

+                "mtspr   54, %[n]           \t\n"   /* Init. DECAR register.*/

+                "li      %%r3, 0x4000       \t\n"   /* TBEN bit.            */

+                "mtspr   1008, %%r3         \t\n"   /* HID0 register.       */

+                "lis     %%r3, 0x0440       \t\n"   /* DIE ARE bits.        */

+                "mtspr   340, %%r3"                 /* TCR register.        */

+                : : [n] "r" (n) : "r3");

+

   /* INTC initialization, software vector mode, 4 bytes vectors, starting

      at priority 0.*/

   INTC.MCR.R        = 0;

@@ -73,12 +85,19 @@ void hal_lld_init(void) {
  */

 void spc_early_init(void) {

 

+  /* TODO: Check for an invalid ME mode on entry.*/

+

   /* Waiting for IRC stabilization before attempting anything else.*/

   while (!ME.GS.B.S_IRCOSC)

     ;

 

 #if !SPC5_NO_INIT

 

+  /* Enables the branch prediction, clears and enables the BTB into the

+     BUCSR special register (1013).*/

+  asm volatile ("li      %%r3, 0x0201          \t\n"

+                "mtspr   1013, %%r3": : : "r3");

+

   /* SSCM initialization. Setting up the most restrictive handling of

      invalid accesses to peripherals.*/

   SSCM.ERROR.R = 3;                             /* PAE and RAE bits.        */

@@ -103,18 +122,35 @@ void spc_early_init(void) {
   AIPS.OPACR88_95.R = 0;

 

 #if defined(SPC5_OSC_BYPASS)

-  /* If the board is equipped with an oscillator instead of a xtal then the

+  /* If the board is equipped with an oscillator instead of a crystal then the

      bypass must be activated.*/

   CGM.OSC_CTL.B.OSCBYP = TRUE;

 #endif /* SPC5_OSC_BYPASS */

 

+  /* Enable clocks to all peripherals: */

+/*  CGM.SC_DC0.R = 0x80;

+  CGM.AC0_DC0_3.R = 0x80808080;

+  CGM.AC1_DC0_3.R = 0x80808080;

+  CGM.AC2_DC0_3.R = 0x85808080;

+  CGM.AC0_SC.R = 0x04000000;

+  CGM.AC2_SC.R = 0x04000000;*/

+  /* PLLs clock sources.*/

+  CGM.AC3_SC.R = SPC5_FMPLL0_CLK_SRC;

+  CGM.AC4_SC.R = SPC5_FMPLL1_CLK_SRC;

+

+  /* Switches to XOSC in order to check its functionality.*/

+  ME.DRUN.R = SPC5_ME_MC_SYSCLK_IRC | SPC5_ME_MC_IRCON | SPC5_ME_MC_XOSC0ON |           \

+              SPC5_ME_MC_FLAON_NORMAL | SPC5_ME_MC_MVRON;

+  if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED)

+    chSysHalt();

+

   /* Initialization of the FMPLLs settings.*/

   CGM.FMPLL[0].CR.R = SPC5_FMPLL0_ODF |

                       ((SPC5_FMPLL0_IDF_VALUE - 1) << 26) |

                       (SPC5_FMPLL0_NDIV_VALUE << 16);

   CGM.FMPLL[0].MR.R = 0;                        /* TODO: Add a setting.     */

   CGM.FMPLL[1].CR.R = SPC5_FMPLL1_ODF |

-                      (SPC5_FMPLL1_IDF_VALUE << 26) |

+                      ((SPC5_FMPLL1_IDF_VALUE - 1) << 26) |

                       (SPC5_FMPLL1_NDIV_VALUE << 16);

   CGM.FMPLL[1].MR.R = 0;                        /* TODO: Add a setting.     */

 

@@ -147,17 +183,17 @@ void spc_early_init(void) {
   ME.LPPC[6].R      = SPC5_ME_LP_PC6_BITS;

   ME.LPPC[7].R      = SPC5_ME_LP_PC7_BITS;

 

-  /* Switches again to DRUN mode (current mode) in order to update the

-     settings.*/

-  if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED)

-    chSysHalt();

-

   /* CFLASH settings calculated for a maximum clock of 64MHz.*/

 /*  CFLASH.PFCR0.B.BK0_APC  = 2;

   CFLASH.PFCR0.B.BK0_RWSC = 2;

   CFLASH.PFCR1.B.BK1_APC  = 2;

   CFLASH.PFCR1.B.BK1_RWSC = 2;*/

 

+  /* Switches again to DRUN mode (current mode) in order to update the

+     settings.*/

+  if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED)

+    chSysHalt();

+

 #endif /* !SPC5_NO_INIT */

 }

 

@@ -176,18 +212,11 @@ bool_t halSPCSetRunMode(spc5_runmode_t mode) {
   ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;

   ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;

 

-  /* Waits the transition process to start.*/

-  while (!ME.GS.B.S_MTRANS)

-    ;

-

-  /* Waits the transition process to end.*/

-  while (ME.GS.B.S_MTRANS)

+  /* Waits for the mode switch.

+     TODO: Check for errors during the switch procedure.*/

+  while (ME.GS.B.S_CURRENT_MODE != mode)

     ;

 

-  /* Verifies that the mode has been effectively switched.*/

-  if (ME.GS.B.S_CURRENT_MODE != mode)

-    return CH_FAILED;

-

   return CH_SUCCESS;

 }

 

diff --git a/os/hal/platforms/SPC56ELxx/hal_lld.h b/os/hal/platforms/SPC56ELxx/hal_lld.h
index d83265061..3bb2a652d 100644
--- a/os/hal/platforms/SPC56ELxx/hal_lld.h
+++ b/os/hal/platforms/SPC56ELxx/hal_lld.h
@@ -161,16 +161,11 @@
 #define SPC5_ME_MC_XOSC0ON          (1U << 5)

 #define SPC5_ME_MC_PLL0ON           (1U << 6)

 #define SPC5_ME_MC_PLL1ON           (1U << 7)

-#define SPC5_ME_MC_CFLAON_MASK      (3U << 16)

-#define SPC5_ME_MC_CFLAON(n)        ((n) << 16)

-#define SPC5_ME_MC_CFLAON_PD        (1U << 16)

-#define SPC5_ME_MC_CFLAON_LP        (2U << 16)

-#define SPC5_ME_MC_CFLAON_NORMAL    (3U << 16)

-#define SPC5_ME_MC_DFLAON_MASK      (3U << 18)

-#define SPC5_ME_MC_DFLAON(n)        ((n) << 18)

-#define SPC5_ME_MC_DFLAON_PD        (1U << 18)

-#define SPC5_ME_MC_DFLAON_LP        (2U << 18)

-#define SPC5_ME_MC_DFLAON_NORMAL    (3U << 18)

+#define SPC5_ME_MC_FLAON_MASK       ((3U << 16) | (3U << 18))

+#define SPC5_ME_MC_FLAON(n)         (((n) << 16) | ((n) << 18))

+#define SPC5_ME_MC_FLAON_PD         ((1U << 16) | (1U << 18))

+#define SPC5_ME_MC_FLAON_LP         ((2U << 16) | (2U << 18))

+#define SPC5_ME_MC_FLAON_NORMAL     ((3U << 16) | (3U << 18))

 #define SPC5_ME_MC_MVRON            (1U << 20)

 #define SPC5_ME_MC_PDO              (1U << 23)

 /** @} */

@@ -325,8 +320,7 @@
                                              SPC5_ME_MC_XOSC0ON |           \

                                              SPC5_ME_MC_PLL0ON |            \

                                              SPC5_ME_MC_PLL1ON |            \

-                                             SPC5_ME_MC_CFLAON_NORMAL |     \

-                                             SPC5_ME_MC_DFLAON_NORMAL |     \

+                                             SPC5_ME_MC_FLAON_NORMAL |      \

                                              SPC5_ME_MC_MVRON)

 #endif

 

@@ -339,8 +333,7 @@
                                              SPC5_ME_MC_XOSC0ON |           \

                                              SPC5_ME_MC_PLL0ON |            \

                                              SPC5_ME_MC_PLL1ON |            \

-                                             SPC5_ME_MC_CFLAON_NORMAL |     \

-                                             SPC5_ME_MC_DFLAON_NORMAL |     \

+                                             SPC5_ME_MC_FLAON_NORMAL |      \

                                              SPC5_ME_MC_MVRON)

 #endif

 

@@ -353,8 +346,7 @@
                                              SPC5_ME_MC_XOSC0ON |           \

                                              SPC5_ME_MC_PLL0ON |            \

                                              SPC5_ME_MC_PLL1ON |            \

-                                             SPC5_ME_MC_CFLAON_NORMAL |     \

-                                             SPC5_ME_MC_DFLAON_NORMAL |     \

+                                             SPC5_ME_MC_FLAON_NORMAL |      \

                                              SPC5_ME_MC_MVRON)

 #endif

 

@@ -367,8 +359,7 @@
                                              SPC5_ME_MC_XOSC0ON |           \

                                              SPC5_ME_MC_PLL0ON |            \

                                              SPC5_ME_MC_PLL1ON |            \

-                                             SPC5_ME_MC_CFLAON_NORMAL |     \

-                                             SPC5_ME_MC_DFLAON_NORMAL |     \

+                                             SPC5_ME_MC_FLAON_NORMAL |      \

                                              SPC5_ME_MC_MVRON)

 #endif

 

@@ -381,8 +372,7 @@
                                              SPC5_ME_MC_XOSC0ON |           \

                                              SPC5_ME_MC_PLL0ON |            \

                                              SPC5_ME_MC_PLL1ON |            \

-                                             SPC5_ME_MC_CFLAON_NORMAL |     \

-                                             SPC5_ME_MC_DFLAON_NORMAL |     \

+                                             SPC5_ME_MC_FLAON_NORMAL |      \

                                              SPC5_ME_MC_MVRON)

 #endif

 

@@ -395,8 +385,7 @@
                                              SPC5_ME_MC_XOSC0ON |           \

                                              SPC5_ME_MC_PLL0ON |            \

                                              SPC5_ME_MC_PLL1ON |            \

-                                             SPC5_ME_MC_CFLAON_NORMAL |     \

-                                             SPC5_ME_MC_DFLAON_NORMAL |     \

+                                             SPC5_ME_MC_FLAON_NORMAL |      \

                                              SPC5_ME_MC_MVRON)

 #endif

 

@@ -409,8 +398,7 @@
                                              SPC5_ME_MC_XOSC0ON |           \

                                              SPC5_ME_MC_PLL0ON |            \

                                              SPC5_ME_MC_PLL1ON |            \

-                                             SPC5_ME_MC_CFLAON_NORMAL |     \

-                                             SPC5_ME_MC_DFLAON_NORMAL |     \

+                                             SPC5_ME_MC_FLAON_NORMAL |      \

                                              SPC5_ME_MC_MVRON)

 #endif