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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-07-26 12:51:34 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-07-26 12:51:34 +0000 |
| commit | 0e263707af129726b6f9f1056523e1f16f350078 (patch) | |
| tree | 724f3ba5c9c07284c3b7c7574e87fa23c91ff6e3 /os | |
| parent | b33676f51e20e656778a5d6100580950b771fd2e (diff) | |
| download | ChibiOS-0e263707af129726b6f9f1056523e1f16f350078.tar.gz ChibiOS-0e263707af129726b6f9f1056523e1f16f350078.tar.bz2 ChibiOS-0e263707af129726b6f9f1056523e1f16f350078.zip | |
STM32L0xx ADC demo.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8106 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
| -rw-r--r-- | os/hal/ports/STM32/LLD/ADCv1/adc_lld.c | 6 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/ADCv1/adc_lld.h | 20 |
2 files changed, 13 insertions, 13 deletions
diff --git a/os/hal/ports/STM32/LLD/ADCv1/adc_lld.c b/os/hal/ports/STM32/LLD/ADCv1/adc_lld.c index b77a1e21b..4f947f085 100644 --- a/os/hal/ports/STM32/LLD/ADCv1/adc_lld.c +++ b/os/hal/ports/STM32/LLD/ADCv1/adc_lld.c @@ -136,11 +136,11 @@ void adc_lld_init(void) { STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
-#endif
/* The shared vector is initialized on driver initialization and never
disabled.*/
- nvicEnableVector(12, STM32_ADC_IRQ_PRIORITY);
+ nvicEnableVector(12, STM32_ADC_ADC1_IRQ_PRIORITY);
+#endif
/* Calibration procedure.*/
rccEnableADC1(FALSE);
@@ -175,7 +175,7 @@ void adc_lld_start(ADCDriver *adcp) { rccEnableADC1(FALSE);
/* Clock settings.*/
- adcp->adc->CFGR2 = STM32_ADC_CKMODE;
+ adcp->adc->CFGR2 = STM32_ADC_ADC1_CKMODE;
}
#endif /* STM32_ADC_USE_ADC1 */
diff --git a/os/hal/ports/STM32/LLD/ADCv1/adc_lld.h b/os/hal/ports/STM32/LLD/ADCv1/adc_lld.h index e91f79ffe..a561129e4 100644 --- a/os/hal/ports/STM32/LLD/ADCv1/adc_lld.h +++ b/os/hal/ports/STM32/LLD/ADCv1/adc_lld.h @@ -116,6 +116,13 @@ #endif
/**
+ * @brief ADC1 clock source selection.
+ */
+#if !defined(STM32_ADC_CKMODE) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
+#endif
+
+/**
* @brief ADC1 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
@@ -126,7 +133,7 @@ * @brief ADC interrupt priority level setting.
*/
#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_IRQ_PRIORITY 2
+#define STM32_ADC_ADC1_IRQ_PRIORITY 2
#endif
/**
@@ -136,15 +143,8 @@ #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
#endif
-/**
- * @brief ADC clock source selection.
- */
-#if !defined(STM32_ADC_CKMODE) || defined(__DOXYGEN__)
-#define STM32_ADC_CKMODE STM32_ADC_CKMODE_ADCCLK
-#endif
-
#if (STM32_ADC_SUPPORTS_PRESCALER == TRUE) || defined(__DOXYGEN__)
-/**
+/*
* @brief ADC prescaler setting.
* @note This setting has effect only in asynchronous clock mode (the
* default, @p STM32_ADC_CKMODE_ADCCLK).
@@ -169,7 +169,7 @@ #endif
#if STM32_ADC_USE_ADC1 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_IRQ_PRIORITY)
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to ADC1"
#endif
|