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author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-08-02 10:05:09 +0000 |
---|---|---|
committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-08-02 10:05:09 +0000 |
commit | 0aee8c6229dbb72fcc40dda09f15823550d336fa (patch) | |
tree | d3a66d6d6f0d098484bf49f07d981de4b7b611ea /os | |
parent | bd8e7b55eb9200bfc8660f066ddd8b9b0d455c29 (diff) | |
download | ChibiOS-0aee8c6229dbb72fcc40dda09f15823550d336fa.tar.gz ChibiOS-0aee8c6229dbb72fcc40dda09f15823550d336fa.tar.bz2 ChibiOS-0aee8c6229dbb72fcc40dda09f15823550d336fa.zip |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8143 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
-rw-r--r-- | os/hal/boards/ST_STM32F746G_DISCOVERY/board.c (renamed from os/hal/boards/ST_STM32F476G_DISCOVERY/board.c) | 0 | ||||
-rw-r--r-- | os/hal/boards/ST_STM32F746G_DISCOVERY/board.h (renamed from os/hal/boards/ST_STM32F476G_DISCOVERY/board.h) | 0 | ||||
-rw-r--r-- | os/hal/boards/ST_STM32F746G_DISCOVERY/board.mk (renamed from os/hal/boards/ST_STM32F476G_DISCOVERY/board.mk) | 0 | ||||
-rw-r--r-- | os/hal/boards/ST_STM32F746G_DISCOVERY/cfg/board.chcfg (renamed from os/hal/boards/ST_STM32F476G_DISCOVERY/cfg/board.chcfg) | 0 | ||||
-rw-r--r-- | os/hal/ports/STM32/STM32F7xx/hal_lld.c | 37 | ||||
-rw-r--r-- | os/hal/ports/STM32/STM32F7xx/hal_lld.h | 83 | ||||
-rw-r--r-- | os/hal/ports/common/ARMCMx/nvic.c | 4 |
7 files changed, 62 insertions, 62 deletions
diff --git a/os/hal/boards/ST_STM32F476G_DISCOVERY/board.c b/os/hal/boards/ST_STM32F746G_DISCOVERY/board.c index 4d546e3d6..4d546e3d6 100644 --- a/os/hal/boards/ST_STM32F476G_DISCOVERY/board.c +++ b/os/hal/boards/ST_STM32F746G_DISCOVERY/board.c diff --git a/os/hal/boards/ST_STM32F476G_DISCOVERY/board.h b/os/hal/boards/ST_STM32F746G_DISCOVERY/board.h index 61a388d9d..61a388d9d 100644 --- a/os/hal/boards/ST_STM32F476G_DISCOVERY/board.h +++ b/os/hal/boards/ST_STM32F746G_DISCOVERY/board.h diff --git a/os/hal/boards/ST_STM32F476G_DISCOVERY/board.mk b/os/hal/boards/ST_STM32F746G_DISCOVERY/board.mk index a7cfca40d..a7cfca40d 100644 --- a/os/hal/boards/ST_STM32F476G_DISCOVERY/board.mk +++ b/os/hal/boards/ST_STM32F746G_DISCOVERY/board.mk diff --git a/os/hal/boards/ST_STM32F476G_DISCOVERY/cfg/board.chcfg b/os/hal/boards/ST_STM32F746G_DISCOVERY/cfg/board.chcfg index 6f6671b7b..6f6671b7b 100644 --- a/os/hal/boards/ST_STM32F476G_DISCOVERY/cfg/board.chcfg +++ b/os/hal/boards/ST_STM32F746G_DISCOVERY/cfg/board.chcfg diff --git a/os/hal/ports/STM32/STM32F7xx/hal_lld.c b/os/hal/ports/STM32/STM32F7xx/hal_lld.c index b1cbd86e1..28bcb26b0 100644 --- a/os/hal/ports/STM32/STM32F7xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32F7xx/hal_lld.c @@ -54,7 +54,7 @@ uint32_t SystemCoreClock = STM32_SYSCLK; static void hal_lld_backup_domain_init(void) {
/* Backup domain access enabled and left open.*/
- PWR->CR |= PWR_CR_DBP;
+ PWR->CR1 |= PWR_CR1_DBP;
/* Reset BKP domain if different clock source selected.*/
if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
@@ -90,11 +90,11 @@ static void hal_lld_backup_domain_init(void) { #if STM32_BKPRAM_ENABLE
rccEnableBKPSRAM(false);
- PWR->CSR |= PWR_CSR_BRE;
- while ((PWR->CSR & PWR_CSR_BRR) == 0)
+ PWR->CSR1 |= PWR_CSR1_BRE;
+ while ((PWR->CSR1 & PWR_CSR1_BRR) == 0)
; /* Waits until the regulator is stable */
#else
- PWR->CSR &= ~PWR_CSR_BRE;
+ PWR->CSR1 &= ~PWR_CSR1_BRE;
#endif /* STM32_BKPRAM_ENABLE */
}
@@ -132,7 +132,7 @@ void hal_lld_init(void) { /* Programmable voltage detector enable.*/
#if STM32_PVD_ENABLE
- PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
+ PWR->CR1 |= PWR_CR1_PVDE | (STM32_PLS & STM32_PLS_MASK);
#endif /* STM32_PVD_ENABLE */
}
@@ -151,9 +151,9 @@ void stm32_clock_init(void) { /* PWR initialization.*/
#if defined(STM32F7xx) || defined(__DOXYGEN__)
- PWR->CR = STM32_VOS;
+ PWR->CR1 = STM32_VOS;
#else
- PWR->CR = 0;
+ PWR->CR1 = 0;
#endif
/* HSI setup, it enforces the reset situation in order to handle possible
@@ -202,17 +202,17 @@ void stm32_clock_init(void) { /* Synchronization with voltage regulator stabilization.*/
#if defined(STM32F7xx)
- while ((PWR->CSR & PWR_CSR_VOSRDY) == 0)
+ while ((PWR->CSR1 & PWR_CSR1_VOSRDY) == 0)
; /* Waits until power regulator is stable. */
#if STM32_OVERDRIVE_REQUIRED
/* Overdrive activation performed after activating the PLL in order to save
time as recommended in RM in "Entering Over-drive mode" paragraph.*/
- PWR->CR |= PWR_CR_ODEN;
- while (!(PWR->CSR & PWR_CSR_ODRDY))
+ PWR->CR1 |= PWR_CR1_ODEN;
+ while (!(PWR->CSR1 & PWR_CSR1_ODRDY))
;
- PWR->CR |= PWR_CR_ODSWEN;
- while (!(PWR->CSR & PWR_CSR_ODSWRDY))
+ PWR->CR1 |= PWR_CR1_ODSWEN;
+ while (!(PWR->CSR1 & PWR_CSR1_ODSWRDY))
;
#endif /* STM32_OVERDRIVE_REQUIRED */
#endif /* defined(STM32F7xx) */
@@ -248,18 +248,7 @@ void stm32_clock_init(void) { STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
/* Flash setup.*/
-#if defined(STM32_USE_REVISION_A_FIX)
- /* Some old revisions of F4x MCUs randomly crashes with compiler
- optimizations enabled AND flash caches enabled. */
- if ((DBGMCU->IDCODE == 0x20006411) && (SCB->CPUID == 0x410FC241))
- FLASH->ACR = FLASH_ACR_PRFTEN | STM32_FLASHBITS;
- else
- FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |
- FLASH_ACR_DCEN | STM32_FLASHBITS;
-#else
- FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |
- FLASH_ACR_DCEN | STM32_FLASHBITS;
-#endif
+ FLASH->ACR = FLASH_ACR_ARTEN | FLASH_ACR_PRFTEN | STM32_FLASHBITS;
/* Switching to the configured clock source if it is different from HSI.*/
#if (STM32_SW != STM32_SW_HSI)
diff --git a/os/hal/ports/STM32/STM32F7xx/hal_lld.h b/os/hal/ports/STM32/STM32F7xx/hal_lld.h index 23ea7e424..f3d961c19 100644 --- a/os/hal/ports/STM32/STM32F7xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F7xx/hal_lld.h @@ -479,7 +479,7 @@ * @brief Enables or disables the LSE clock source.
*/
#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
-#define STM32_LSE_ENABLED FALSE
+#define STM32_LSE_ENABLED TRUE
#endif
/**
@@ -493,8 +493,8 @@ * @brief Main clock source selection.
* @note If the selected clock source is not the PLL then the PLL is not
* initialized and started.
- * @note The default value is calculated for a 168MHz system clock from
- * an external 8MHz HSE clock.
+ * @note The default value is calculated for a 216MHz system clock from
+ * an external 25MHz HSE clock.
*/
#if !defined(STM32_SW) || defined(__DOXYGEN__)
#define STM32_SW STM32_SW_PLL
@@ -504,8 +504,8 @@ * @brief Clock source for the PLLs.
* @note This setting has only effect if the PLL is selected as the
* system clock source.
- * @note The default value is calculated for a 168MHz system clock from
- * an external 8MHz HSE clock.
+ * @note The default value is calculated for a 216MHz system clock from
+ * an external 25MHz HSE clock.
*/
#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
#define STM32_PLLSRC STM32_PLLSRC_HSE
@@ -514,41 +514,41 @@ /**
* @brief PLLM divider value.
* @note The allowed values are 2..63.
- * @note The default value is calculated for a 168MHz system clock from
- * an external 8MHz HSE clock.
+ * @note The default value is calculated for a 216MHz system clock from
+ * an external 25MHz HSE clock.
*/
#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLM_VALUE 8
+#define STM32_PLLM_VALUE 25
#endif
/**
* @brief PLLN multiplier value.
* @note The allowed values are 192..432.
- * @note The default value is calculated for a 168MHz system clock from
- * an external 8MHz HSE clock.
+ * @note The default value is calculated for a 216MHz system clock from
+ * an external 25MHz HSE clock.
*/
#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLN_VALUE 336
+#define STM32_PLLN_VALUE 432
#endif
/**
* @brief PLLP divider value.
* @note The allowed values are 2, 4, 6, 8.
- * @note The default value is calculated for a 168MHz system clock from
- * an external 8MHz HSE clock.
+ * @note The default value is calculated for a 216MHz system clock from
+ * an external 25MHz HSE clock.
*/
#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLP_VALUE 2
#endif
/**
- * @brief PLLQ multiplier value.
+ * @brief PLLQ divider value.
* @note The allowed values are 2..15.
- * @note The default value is calculated for a 168MHz system clock from
- * an external 8MHz HSE clock.
+ * @note The default value is calculated for a 216MHz system clock from
+ * an external 25MHz HSE clock.
*/
#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLQ_VALUE 7
+#define STM32_PLLQ_VALUE 9
#endif
/**
@@ -581,9 +581,10 @@ /**
* @brief RTC HSE prescaler value.
+ * @note The allowed values are 2..31.
*/
#if !defined(STM32_RTCPRE_VALUE) || defined(__DOXYGEN__)
-#define STM32_RTCPRE_VALUE 8
+#define STM32_RTCPRE_VALUE 25
#endif
/**
@@ -604,7 +605,7 @@ /**
* @brief MC02 clock source value.
- * @note The default value outputs SYSCLK / 5 on MC02 pin.
+ * @note The default value outputs SYSCLK / 8 on MC02 pin.
*/
#if !defined(STM32_MCO2SEL) || defined(__DOXYGEN__)
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
@@ -612,17 +613,17 @@ /**
* @brief MC02 prescaler value.
- * @note The default value outputs SYSCLK / 5 on MC02 pin.
+ * @note The default value outputs SYSCLK / 8 on MC02 pin.
*/
#if !defined(STM32_MCO2PRE) || defined(__DOXYGEN__)
-#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
+#define STM32_MCO2PRE STM32_MCO2PRE_DIV8
#endif
/**
* @brief I2S clock source.
*/
#if !defined(STM32_I2SSRC) || defined(__DOXYGEN__)
-#define STM32_I2SSRC STM32_I2SSRC_CKIN
+#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
#endif
/**
@@ -634,7 +635,7 @@ #endif
/**
- * @brief PLLI2SP multiplier value.
+ * @brief PLLI2SP divider value.
* @note The allowed values are 2, 4, 6 and 8.
*/
#if !defined(STM32_PLLI2SP_VALUE) || defined(__DOXYGEN__)
@@ -642,31 +643,31 @@ #endif
/**
- * @brief PLLI2SQ multiplier value.
+ * @brief PLLI2SQ divider value.
* @note The allowed values are 2..15.
*/
#if !defined(STM32_PLLI2SQ_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLI2SQ_VALUE 5
+#define STM32_PLLI2SQ_VALUE 4
#endif
/**
- * @brief PLLI2SR multiplier value.
+ * @brief PLLI2SR divider value.
* @note The allowed values are 2..7.
*/
#if !defined(STM32_PLLI2SR_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLI2SR_VALUE 5
+#define STM32_PLLI2SR_VALUE 4
#endif
/**
- * @brief PLLSAIN value.
+ * @brief PLLSAIN multiplier value.
* @note The allowed values are 49..432.
*/
#if !defined(STM32_PLLSAIN_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLSAIN_VALUE 120
+#define STM32_PLLSAIN_VALUE 192
#endif
/**
- * @brief PLLSAIP value.
+ * @brief PLLSAIP divider value.
* @note The allowed values are 2, 4, 6 and 8.
*/
#if !defined(STM32_PLLSAIP_VALUE) || defined(__DOXYGEN__)
@@ -674,15 +675,15 @@ #endif
/**
- * @brief PLLSAIQ value.
+ * @brief PLLSAIQ divider value.
* @note The allowed values are 2..15.
*/
#if !defined(STM32_PLLSAIQ_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLSAIQ_VALUE 8
+#define STM32_PLLSAIQ_VALUE 4
#endif
/**
- * @brief PLLSAIR value.
+ * @brief PLLSAIR divider value.
* @note The allowed values are 2..7.
*/
#if !defined(STM32_PLLSAIR_VALUE) || defined(__DOXYGEN__)
@@ -690,7 +691,7 @@ #endif
/**
- * @brief PLLSAIDIVR value (LCD clock divider).
+ * @brief PLLSAIDIVR divider value (LCD clock divider).
*/
#if !defined(STM32_PLLSAIDIVR) || defined(__DOXYGEN__)
#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF
@@ -941,12 +942,18 @@ #if STM32_HSE_ENABLED
#if STM32_HSECLK == 0
-#error "HSE frequency not defined"
-
-#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
+ #error "HSE frequency not defined"
+#else /* STM32_HSECLK != 0 */
+#if defined(STM32_HSE_BYPASS)
+#if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_BYP_MAX)
+#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_BYP_MAX)"
+#endif
+#else /* !defined(STM32_HSE_BYPASS) */
+#if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
#endif
-
+#endif /* !defined(STM32_HSE_BYPASS) */
+#endif /* STM32_HSECLK != 0 */
#else /* !STM32_HSE_ENABLED */
#if STM32_SW == STM32_SW_HSE
diff --git a/os/hal/ports/common/ARMCMx/nvic.c b/os/hal/ports/common/ARMCMx/nvic.c index 93e74ca82..c8f1f21af 100644 --- a/os/hal/ports/common/ARMCMx/nvic.c +++ b/os/hal/ports/common/ARMCMx/nvic.c @@ -82,7 +82,11 @@ void nvicSetSystemHandlerPriority(uint32_t handler, uint32_t prio) { osalDbgCheck(handler <= 12);
+#if defined(__CORE_CM7_H_GENERIC)
+ SCB->SHPR[handler] = NVIC_PRIORITY_MASK(prio);
+#else
SCB->SHP[handler] = NVIC_PRIORITY_MASK(prio);
+#endif
}
/**
|