PVD. Merged to trunk. Checked compilability on F1x, L1x, F4x.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3733 35acf78f-673a-0410-8e92-d51de3d6d3f4

10 files changed, 203 insertions, 10 deletions

diff --git a/os/hal/platforms/STM32F1xx/hal_lld.c b/os/hal/platforms/STM32F1xx/hal_lld.c
index 0f2d490d6..8afaf39a2 100644
--- a/os/hal/platforms/STM32F1xx/hal_lld.c
+++ b/os/hal/platforms/STM32F1xx/hal_lld.c
@@ -73,6 +73,12 @@ void hal_lld_init(void) {
 #if defined(STM32_DMA_REQUIRED)

   dmaInit();

 #endif

+

+  /* Programmable voltage detector enable. */

+#if STM32_PVD_ENABLE

+  rccEnablePWRInterface(FALSE);

+  PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);

+#endif /* STM32_PVD_ENABLE */

 }

 

 /**

diff --git a/os/hal/platforms/STM32F1xx/hal_lld.h b/os/hal/platforms/STM32F1xx/hal_lld.h
index 4e1ca3f35..cf8e09cbe 100644
--- a/os/hal/platforms/STM32F1xx/hal_lld.h
+++ b/os/hal/platforms/STM32F1xx/hal_lld.h
@@ -48,10 +48,37 @@
 /*===========================================================================*/

 /* Driver constants.                                                         */

 /*===========================================================================*/

+/**

+ * @name    PWR_CR register bits definitions

+ * @{

+ */

+#define STM32_PLS_MASK          (7 << 5)    /**< PLS bits mask.             */

+#define STM32_PLS_LEV0          (0 << 5)    /**< PVD level 0.               */

+#define STM32_PLS_LEV1          (1 << 5)    /**< PVD level 0.               */

+#define STM32_PLS_LEV2          (2 << 5)    /**< PVD level 0.               */

+#define STM32_PLS_LEV3          (3 << 5)    /**< PVD level 0.               */

+#define STM32_PLS_LEV4          (4 << 5)    /**< PVD level 0.               */

+#define STM32_PLS_LEV5          (5 << 5)    /**< PVD level 0.               */

+#define STM32_PLS_LEV6          (6 << 5)    /**< PVD level 0.               */

+#define STM32_PLS_LEV7          (7 << 5)    /**< PVD level 0.               */

+/** @} */

 

 /*===========================================================================*/

 /* Driver pre-compile time settings.                                         */

 /*===========================================================================*/

+/**

+ * @brief   Enables or disables the programmable voltage detector.

+ */

+#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)

+#define STM32_PVD_ENABLE            FALSE

+#endif

+

+/**

+ * @brief   Sets voltage level for programmable voltage detector.

+ */

+#if !defined(STM32_PLS) || defined(__DOXYGEN__)

+#define STM32_PLS                   STM32_PLS_LEV0

+#endif

 

 /*===========================================================================*/

 /* Derived constants and error checks.                                       */

diff --git a/os/hal/platforms/STM32F1xx/stm32_rcc.h b/os/hal/platforms/STM32F1xx/stm32_rcc.h
index aa55d4fca..41cf725cb 100644
--- a/os/hal/platforms/STM32F1xx/stm32_rcc.h
+++ b/os/hal/platforms/STM32F1xx/stm32_rcc.h
@@ -244,6 +244,38 @@
 /** @} */

 

 /**

+ * @brief   PWR interface specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the PWR interface clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)

+

+/**

+ * @brief   Disables PWR interface clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_BKPEN, lp)

+

+/**

+ * @brief   Resets the PWR interface.

+ *

+ * @api

+ */

+#define rccResetPWRInterface() rccResetAPB1(RCC_APB1ENR_BKPRST)

+/** @} */

+

+/**

  * @brief   CAN peripherals specific RCC operations

  * @{

  */

diff --git a/os/hal/platforms/STM32F2xx/hal_lld.c b/os/hal/platforms/STM32F2xx/hal_lld.c
index 2344d161f..a56051a05 100644
--- a/os/hal/platforms/STM32F2xx/hal_lld.c
+++ b/os/hal/platforms/STM32F2xx/hal_lld.c
@@ -74,14 +74,15 @@ void hal_lld_init(void) {
   /* DWT cycle counter enable.*/

   DWT_CTRL |= DWT_CTRL_CYCCNTENA;

 

-#if STM32_PVD_ENABLE

-  /* Programmable voltage detector initialization */

-  PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);

-#endif /* STM32_PVD_ENABLE */

-

 #if defined(STM32_DMA_REQUIRED)

   dmaInit();

 #endif

+

+  /* Programmable voltage detector enable. */

+#if STM32_PVD_ENABLE

+  rccEnablePWRInterface(FALSE);

+  PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);

+#endif /* STM32_PVD_ENABLE */

 }

 

 /**

diff --git a/os/hal/platforms/STM32F2xx/stm32_rcc.h b/os/hal/platforms/STM32F2xx/stm32_rcc.h
index 19ad4484d..39d674bd0 100644
--- a/os/hal/platforms/STM32F2xx/stm32_rcc.h
+++ b/os/hal/platforms/STM32F2xx/stm32_rcc.h
@@ -391,6 +391,38 @@
 /** @} */

 

 /**

+ * @brief   PWR interface specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the PWR interface clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)

+

+/**

+ * @brief   Disables PWR interface clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_BKPEN, lp)

+

+/**

+ * @brief   Resets the PWR interface.

+ *

+ * @api

+ */

+#define rccResetPWRInterface() rccResetAPB1(RCC_APB1ENR_BKPRST)

+/** @} */

+

+/**

  * @brief   I2C peripherals specific RCC operations

  * @{

  */

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index d9bf8374e..71b8ad219 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -74,14 +74,15 @@ void hal_lld_init(void) {
   /* DWT cycle counter enable.*/

   DWT_CTRL |= DWT_CTRL_CYCCNTENA;

 

-#if STM32_PVD_ENABLE

-  /* Programmable voltage detector initialization */

-  PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);

-#endif /* STM32_PVD_ENABLE */

-

 #if defined(STM32_DMA_REQUIRED)

   dmaInit();

 #endif

+

+  /* Programmable voltage detector enable. */

+#if STM32_PVD_ENABLE

+  rccEnablePWRInterface(FALSE);

+  PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);

+#endif /* STM32_PVD_ENABLE */

 }

 

 /**

diff --git a/os/hal/platforms/STM32F4xx/stm32_rcc.h b/os/hal/platforms/STM32F4xx/stm32_rcc.h
index 4971a71c5..a20274b26 100644
--- a/os/hal/platforms/STM32F4xx/stm32_rcc.h
+++ b/os/hal/platforms/STM32F4xx/stm32_rcc.h
@@ -391,6 +391,38 @@
 /** @} */

 

 /**

+ * @brief   PWR interface specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the PWR interface clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)

+

+/**

+ * @brief   Disables PWR interface clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_BKPEN, lp)

+

+/**

+ * @brief   Resets the PWR interface.

+ *

+ * @api

+ */

+#define rccResetPWRInterface() rccResetAPB1(RCC_APB1ENR_BKPRST)

+/** @} */

+

+/**

  * @brief   I2C peripherals specific RCC operations

  * @{

  */

diff --git a/os/hal/platforms/STM32L1xx/hal_lld.c b/os/hal/platforms/STM32L1xx/hal_lld.c
index 54d67b9d0..69619dead 100644
--- a/os/hal/platforms/STM32L1xx/hal_lld.c
+++ b/os/hal/platforms/STM32L1xx/hal_lld.c
@@ -74,6 +74,12 @@ void hal_lld_init(void) {
 #if defined(STM32_DMA_REQUIRED)

   dmaInit();

 #endif

+

+  /* Programmable voltage detector enable. */

+#if STM32_PVD_ENABLE

+  rccEnablePWRInterface(FALSE);

+  PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);

+#endif /* STM32_PVD_ENABLE */

 }

 

 /**

diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h
index 4bbe2fe76..c11c9ccd8 100644
--- a/os/hal/platforms/STM32L1xx/hal_lld.h
+++ b/os/hal/platforms/STM32L1xx/hal_lld.h
@@ -66,6 +66,16 @@
 #define STM32_VOS_1P8           (1 << 11)   /**< Core voltage 1.8 Volts.    */

 #define STM32_VOS_1P5           (2 << 11)   /**< Core voltage 1.5 Volts.    */

 #define STM32_VOS_1P2           (3 << 11)   /**< Core voltage 1.2 Volts.    */

+

+#define STM32_PLS_MASK          (7 << 5)    /**< PLS bits mask.             */

+#define STM32_PLS_LEV0          (0 << 5)    /**< PVD level 0.               */

+#define STM32_PLS_LEV1          (1 << 5)    /**< PVD level 0.               */

+#define STM32_PLS_LEV2          (2 << 5)    /**< PVD level 0.               */

+#define STM32_PLS_LEV3          (3 << 5)    /**< PVD level 0.               */

+#define STM32_PLS_LEV4          (4 << 5)    /**< PVD level 0.               */

+#define STM32_PLS_LEV5          (5 << 5)    /**< PVD level 0.               */

+#define STM32_PLS_LEV6          (6 << 5)    /**< PVD level 0.               */

+#define STM32_PLS_LEV7          (7 << 5)    /**< PVD level 0.               */

 /** @} */

 

 /**

@@ -387,6 +397,20 @@
 #endif

 

 /**

+ * @brief   Enables or disables the programmable voltage detector.

+ */

+#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)

+#define STM32_PVD_ENABLE            FALSE

+#endif

+

+/**

+ * @brief   Sets voltage level for programmable voltage detector.

+ */

+#if !defined(STM32_PLS) || defined(__DOXYGEN__)

+#define STM32_PLS                   STM32_PLS_LEV0

+#endif

+

+/**

  * @brief   Enables or disables the HSI clock source.

  */

 #if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)

diff --git a/os/hal/platforms/STM32L1xx/stm32_rcc.h b/os/hal/platforms/STM32L1xx/stm32_rcc.h
index 9ffcc07b4..9068adc5a 100644
--- a/os/hal/platforms/STM32L1xx/stm32_rcc.h
+++ b/os/hal/platforms/STM32L1xx/stm32_rcc.h
@@ -237,6 +237,38 @@
 /** @} */

 

 /**

+ * @brief   PWR interface specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the PWR interface clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)

+

+/**

+ * @brief   Disables PWR interface clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_BKPEN, lp)

+

+/**

+ * @brief   Resets the PWR interface.

+ *

+ * @api

+ */

+#define rccResetPWRInterface() rccResetAPB1(RCC_APB1ENR_BKPRST)

+/** @} */

+

+/**

  * @brief   I2C peripherals specific RCC operations

  * @{

  */