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| author | isiora <none@example.com> | 2018-02-27 00:12:49 +0000 |
|---|---|---|
| committer | isiora <none@example.com> | 2018-02-27 00:12:49 +0000 |
| commit | 043860de59a350c8eefe02a7ae952e0894d191d7 (patch) | |
| tree | 20e1ffc2f8b3343d7dcf634e4fc5b438002dcc79 /os | |
| parent | 6c665fa72e262649ffd3133c843c0e9d9ddf15db (diff) | |
| download | ChibiOS-043860de59a350c8eefe02a7ae952e0894d191d7.tar.gz ChibiOS-043860de59a350c8eefe02a7ae952e0894d191d7.tar.bz2 ChibiOS-043860de59a350c8eefe02a7ae952e0894d191d7.zip | |
Fixed L2C_310 defines.
git-svn-id: https://svn.code.sf.net/p/chibios/svn2/trunk@11572 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'os')
| -rw-r--r-- | os/common/ext/ARM/CMSIS/Core_A/Include/ARMCA5.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/os/common/ext/ARM/CMSIS/Core_A/Include/ARMCA5.h b/os/common/ext/ARM/CMSIS/Core_A/Include/ARMCA5.h index 02d80d2b9..70002a773 100644 --- a/os/common/ext/ARM/CMSIS/Core_A/Include/ARMCA5.h +++ b/os/common/ext/ARM/CMSIS/Core_A/Include/ARMCA5.h @@ -114,7 +114,7 @@ typedef enum IRQn //The VE-A5 model implements L1 cache as architecturally defined, but does not implement L2 cache. //Do not enable the L2 cache if you are running RTX on a VE-A5 model as it may cause a data abort. -#define VE_A5_MP_PL310_BASE (0x2C0F0000UL) /*!< (L2C-310 ) Base Address */ +#define VE_A5_MP_PL310_BASE (0x00A00000UL) /*!< (L2C-310 ) Base Address */ #define L2C_310_BASE VE_A5_MP_PL310_BASE /* -------- Configuration of the Cortex-A5 Processor and Core Peripherals ------- */ @@ -123,7 +123,7 @@ typedef enum IRQn #define __FPU_PRESENT 1U /* FPU present */ #define __GIC_PRESENT 1U /* GIC present */ #define __TIM_PRESENT 1U /* TIM present */ -#define __L2C_PRESENT 0U /* L2C present */ +#define __L2C_PRESENT 1U /* L2C present */ #include "core_ca.h" #include <system_ARMCA5.h> |