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author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-03-05 21:28:51 +0000 |
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committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-03-05 21:28:51 +0000 |
commit | b53489d0e4252aafe5ada7466e0b3b7c4ad5aaaf (patch) | |
tree | 2efd9ba0b52dfed9daefb6eb4d6b86b073776a21 /os/rt/ports/ARMCMx/chcore_v6m.h | |
parent | 880d6916b3fb25b3972ed78b380db630524623e7 (diff) | |
download | ChibiOS-b53489d0e4252aafe5ada7466e0b3b7c4ad5aaaf.tar.gz ChibiOS-b53489d0e4252aafe5ada7466e0b3b7c4ad5aaaf.tar.bz2 ChibiOS-b53489d0e4252aafe5ada7466e0b3b7c4ad5aaaf.zip |
Lots of MISRA-related changes in RT. Not finished yet.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7715 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/rt/ports/ARMCMx/chcore_v6m.h')
-rw-r--r-- | os/rt/ports/ARMCMx/chcore_v6m.h | 72 |
1 files changed, 36 insertions, 36 deletions
diff --git a/os/rt/ports/ARMCMx/chcore_v6m.h b/os/rt/ports/ARMCMx/chcore_v6m.h index 3ded54449..3c28c0f54 100644 --- a/os/rt/ports/ARMCMx/chcore_v6m.h +++ b/os/rt/ports/ARMCMx/chcore_v6m.h @@ -33,42 +33,6 @@ /*===========================================================================*/
/**
- * @name Architecture and Compiler
- * @{
- */
-#if (CORTEX_MODEL == CORTEX_M0) || defined(__DOXYGEN__)
-/**
- * @brief Macro defining the specific ARM architecture.
- */
-#define PORT_ARCHITECTURE_ARM_v6M
-
-/**
- * @brief Name of the implemented architecture.
- */
-#define PORT_ARCHITECTURE_NAME "ARMv6-M"
-
-/**
- * @brief Name of the architecture variant.
- */
-#define PORT_CORE_VARIANT_NAME "Cortex-M0"
-
-#elif (CORTEX_MODEL == CORTEX_M0PLUS)
-#define PORT_ARCHITECTURE_ARM_v6M
-#define PORT_ARCHITECTURE_NAME "ARMv6-M"
-#define PORT_CORE_VARIANT_NAME "Cortex-M0+"
-#endif
-
-/**
- * @brief Port-specific information string.
- */
-#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
-#define PORT_INFO "Preemption through NMI"
-#else
-#define PORT_INFO "Preemption through PendSV"
-#endif
-/** @} */
-
-/**
* @brief This port does not support a realtime counter.
*/
#define PORT_SUPPORTS_RT FALSE
@@ -132,6 +96,42 @@ /*===========================================================================*/
/**
+ * @name Architecture and Compiler
+ * @{
+ */
+#if (CORTEX_MODEL == CORTEX_M0) || defined(__DOXYGEN__)
+/**
+ * @brief Macro defining the specific ARM architecture.
+ */
+#define PORT_ARCHITECTURE_ARM_v6M
+
+/**
+ * @brief Name of the implemented architecture.
+ */
+#define PORT_ARCHITECTURE_NAME "ARMv6-M"
+
+/**
+ * @brief Name of the architecture variant.
+ */
+#define PORT_CORE_VARIANT_NAME "Cortex-M0"
+
+#elif (CORTEX_MODEL == CORTEX_M0PLUS)
+#define PORT_ARCHITECTURE_ARM_v6M
+#define PORT_ARCHITECTURE_NAME "ARMv6-M"
+#define PORT_CORE_VARIANT_NAME "Cortex-M0+"
+#endif
+
+/**
+ * @brief Port-specific information string.
+ */
+#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
+#define PORT_INFO "Preemption through NMI"
+#else
+#define PORT_INFO "Preemption through PendSV"
+#endif
+/** @} */
+
+/**
* @brief Maximum usable priority for normal ISRs.
*/
#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
|