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authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2009-11-01 19:18:09 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2009-11-01 19:18:09 +0000
commit639d957e5eacffffb849b976552b39a2b66433aa (patch)
treeaa919ffa72219ad110129d7e953dea456d632b80 /os/ports
parentbf464a835d40efa0f766e5602bf0cd566ce48327 (diff)
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Bug 2890382.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1263 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/ports')
-rw-r--r--os/ports/GCC/ARMCM3/chcore.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/os/ports/GCC/ARMCM3/chcore.c b/os/ports/GCC/ARMCM3/chcore.c
index a2334dcf7..8c421867c 100644
--- a/os/ports/GCC/ARMCM3/chcore.c
+++ b/os/ports/GCC/ARMCM3/chcore.c
@@ -92,22 +92,22 @@ void SVCallVector(Thread *otp, Thread *ntp) {
asm volatile ("mrs r3, BASEPRI \n\t" \
"mrs r12, PSP \n\t" \
"stmdb r12!, {r3-r6,r8-r11, lr} \n\t" \
- "str r12, [%0, #16] \n\t" \
- "ldr r12, [%1, #16] \n\t" \
+ "str r12, [r0, #16] \n\t" \
+ "ldr r12, [r1, #16] \n\t" \
"ldmia r12!, {r3-r6,r8-r11, lr} \n\t" \
"msr PSP, r12 \n\t" \
"msr BASEPRI, r3 \n\t" \
- "bx lr" : : "r" (otp), "r" (ntp));
+ "bx lr ");
#else
asm volatile ("mrs r3, BASEPRI \n\t" \
"mrs r12, PSP \n\t" \
"stmdb r12!, {r3-r11, lr} \n\t" \
- "str r12, [%0, #16] \n\t" \
- "ldr r12, [%1, #16] \n\t" \
+ "str r12, [r0, #16] \n\t" \
+ "ldr r12, [r1, #16] \n\t" \
"ldmia r12!, {r3-r11, lr} \n\t" \
"msr PSP, r12 \n\t" \
"msr BASEPRI, r3 \n\t" \
- "bx lr" : : "r" (otp), "r" (ntp));
+ "bx lr ");
#endif
}