Fixed bug 3317500, retested impacted ports.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3047 35acf78f-673a-0410-8e92-d51de3d6d3f4

6 files changed, 50 insertions, 74 deletions

diff --git a/os/ports/GCC/ARMCMx/chcore_v6m.c b/os/ports/GCC/ARMCMx/chcore_v6m.c
index 18082e86f..2183a9ded 100644
--- a/os/ports/GCC/ARMCMx/chcore_v6m.c
+++ b/os/ports/GCC/ARMCMx/chcore_v6m.c
@@ -90,7 +90,8 @@ __attribute__((naked))
 #endif

 void _port_switch_from_isr(void) {

 

-  chSchDoRescheduleI();

+  if (chSchIsRescRequiredExI())

+    chSchDoRescheduleI();

 #if CORTEX_ALTERNATE_SWITCH

   SCB_ICSR = ICSR_PENDSVSET;

   port_unlock();

@@ -153,22 +154,18 @@ void _port_switch(Thread *ntp, Thread *otp) {
 void _port_irq_epilogue(regarm_t lr) {

 

   if (lr != (regarm_t)0xFFFFFFF1) {

+    register struct extctx *ctxp;

+

     port_lock_from_isr();

-    if (chSchIsRescRequiredExI()) {

-      register struct extctx *ctxp;

-

-      /* Adding an artificial exception return context, there is no need to

-         populate it fully.*/

-      asm volatile ("mrs     %0, PSP" : "=r" (ctxp) : : "memory");

-      ctxp--;

-      asm volatile ("msr     PSP, %0" : : "r" (ctxp) : "memory");

-      ctxp->pc = _port_switch_from_isr;

-      ctxp->xpsr = (regarm_t)0x01000000;

-      /* Note, returning without unlocking is intentional, this is done in

-        order to keep the rest of the context switching atomic.*/

-      return;

-    }

-    port_unlock_from_isr();

+    /* Adding an artificial exception return context, there is no need to

+       populate it fully.*/

+    asm volatile ("mrs     %0, PSP" : "=r" (ctxp) : : "memory");

+    ctxp--;

+    asm volatile ("msr     PSP, %0" : : "r" (ctxp) : "memory");

+    ctxp->pc = _port_switch_from_isr;

+    ctxp->xpsr = (regarm_t)0x01000000;

+    /* Note, returning without unlocking is intentional, this is done in

+      order to keep the rest of the context switching atomic.*/

   }

 }

 

diff --git a/os/ports/GCC/ARMCMx/chcore_v7m.c b/os/ports/GCC/ARMCMx/chcore_v7m.c
index 2cf5cfe6b..897c90a96 100644
--- a/os/ports/GCC/ARMCMx/chcore_v7m.c
+++ b/os/ports/GCC/ARMCMx/chcore_v7m.c
@@ -110,12 +110,12 @@ void PendSVVector(void) {
 #endif /* CORTEX_SIMPLIFIED_PRIORITY */

 

 /**

- * @brief   Reschedule verification and setup after an IRQ.

+ * @brief   Exception exit redirection to _port_switch_from_isr().

  */

 void _port_irq_epilogue(void) {

 

   port_lock_from_isr();

-  if ((SCB_ICSR & ICSR_RETTOBASE) && chSchIsRescRequiredExI()) {

+  if ((SCB_ICSR & ICSR_RETTOBASE)) {

     register struct extctx *ctxp;

 

     /* Adding an artificial exception return context, there is no need to

@@ -129,7 +129,6 @@ void _port_irq_epilogue(void) {
        order to keep the rest of the context switching atomic.*/

     return;

   }

-  /* ISR exit without context switching.*/

   port_unlock_from_isr();

 }

 

@@ -142,7 +141,8 @@ __attribute__((naked))
 #endif

 void _port_switch_from_isr(void) {

 

-  chSchDoRescheduleI();

+  if (chSchIsRescRequiredExI())

+    chSchDoRescheduleI();

 #if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)

   asm volatile ("svc     #0");

 #else /* CORTEX_SIMPLIFIED_PRIORITY */

diff --git a/os/ports/IAR/ARMCMx/chcoreasm_v6m.s b/os/ports/IAR/ARMCMx/chcoreasm_v6m.s
index ef72de53c..a05ce3aa1 100644
--- a/os/ports/IAR/ARMCMx/chcoreasm_v6m.s
+++ b/os/ports/IAR/ARMCMx/chcoreasm_v6m.s
@@ -110,7 +110,11 @@ PendSVVector:
  */

         PUBLIC  _port_switch_from_isr

 _port_switch_from_isr:

+        bl      chSchIsRescRequiredExI

+        cmp     r0, #0

+        beq     noresch

         bl      chSchDoRescheduleI

+noresch:

         ldr     r2, =SCB_ICSR

         movs    r3, #128

 #if CORTEX_ALTERNATE_SWITCH

@@ -129,25 +133,19 @@ waithere:
  */

         PUBLIC  _port_irq_epilogue

 _port_irq_epilogue:

-        push    {r3, lr}

+        push    {lr}

         adds    r0, r0, #15

-        beq     stillnested

+        beq     skipexit

         cpsid   i

-        bl      chSchIsRescRequiredExI

-        cmp     r0, #0

-        bne     doresch

-        cpsie   i

-stillnested

-        pop     {r3, pc}

-doresch

         mrs     r3, PSP

         subs    r3, r3, #32

         msr     PSP, r3

         ldr     r2, =_port_switch_from_isr

         str     r2, [r3, #24]

         movs    r2, #128

-        lsls     r2, r2, #17

+        lsls    r2, r2, #17

         str     r2, [r3, #28]

-        pop     {r3, pc}

+skipexit:

+        pop     {pc}

 

         END

diff --git a/os/ports/IAR/ARMCMx/chcoreasm_v7m.s b/os/ports/IAR/ARMCMx/chcoreasm_v7m.s
index 65531ff8c..8367fcdb0 100644
--- a/os/ports/IAR/ARMCMx/chcoreasm_v7m.s
+++ b/os/ports/IAR/ARMCMx/chcoreasm_v7m.s
@@ -76,7 +76,10 @@ _port_thread_start:
  */

         PUBLIC  _port_switch_from_isr

 _port_switch_from_isr:

+        bl      chSchIsRescRequiredExI

+        cbz     r0, .L2

         bl      chSchDoRescheduleI

+.L2:

 #if CORTEX_SIMPLIFIED_PRIORITY

         mov     r3, #LWRD SCB_ICSR

         movt    r3, #HWRD SCB_ICSR

@@ -102,20 +105,16 @@ _port_irq_epilogue:
         mov     r3, #LWRD SCB_ICSR

         movt    r3, #HWRD SCB_ICSR

         ldr     r3, [r3, #0]

-        tst     r3, #ICSR_RETTOBASE

-        bne     .L7

+        ands    r3, r3, #ICSR_RETTOBASE

+        bne     .L8

 #if CORTEX_SIMPLIFIED_PRIORITY

         cpsie   i

 #else

-        movs    r3, #CORTEX_BASEPRI_DISABLED

+        /* Note, R3 is already zero.*/

         msr     BASEPRI, r3

 #endif

         bx      lr

-.L7:

-        push    {r3, lr}

-        bl      chSchIsRescRequiredExI

-        cmp     r0, #0

-        beq     .L4

+.L8:

         mrs     r3, PSP

         subs    r3, r3, #EXTCTX_SIZE

         msr     PSP, r3

@@ -123,15 +122,7 @@ _port_irq_epilogue:
         str     r2, [r3, #24]

         mov     r2, #0x01000000

         str     r2, [r3, #28]

-        pop     {r3, pc}

-.L4:

-#if CORTEX_SIMPLIFIED_PRIORITY

-        cpsie   i

-#else

-        movs    r3, #CORTEX_BASEPRI_DISABLED

-        msr     BASEPRI, r3

-#endif

-        pop     {r3, pc}

+        bx      lr

 

 /*

  * SVC vector.

diff --git a/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s b/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s
index 6cfc89410..579680421 100644
--- a/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s
+++ b/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s
@@ -109,7 +109,11 @@ PendSVVector       PROC
  */

                 EXPORT  _port_switch_from_isr

 _port_switch_from_isr PROC

+                bl      chSchIsRescRequiredExI

+                cmp     r0, #0

+                beq     noresch

                 bl      chSchDoRescheduleI

+noresch

                 ldr     r2, =SCB_ICSR

                 movs    r3, #128

 #if CORTEX_ALTERNATE_SWITCH

@@ -128,26 +132,20 @@ waithere        b       waithere
  */

                 EXPORT  _port_irq_epilogue

 _port_irq_epilogue PROC

-                push    {r3, lr}

+                push    {lr}

                 adds    r0, r0, #15

-                beq     stillnested

+                beq     skipexit

                 cpsid   i

-                bl      chSchIsRescRequiredExI

-                cmp     r0, #0

-                bne     doresch

-                cpsie   i

-stillnested

-                pop     {r3, pc}

-doresch

                 mrs     r3, PSP

                 subs    r3, r3, #32

                 msr     PSP, r3

                 ldr     r2, =_port_switch_from_isr

                 str     r2, [r3, #24]

                 movs    r2, #128

-                lsls     r2, r2, #17

+                lsls    r2, r2, #17

                 str     r2, [r3, #28]

-                pop     {r3, pc}

+skipexit

+                pop     {pc}

                 ENDP

 

                 END

diff --git a/os/ports/RVCT/ARMCMx/chcoreasm_v7m.s b/os/ports/RVCT/ARMCMx/chcoreasm_v7m.s
index 6c7efeb3c..f6acf2968 100644
--- a/os/ports/RVCT/ARMCMx/chcoreasm_v7m.s
+++ b/os/ports/RVCT/ARMCMx/chcoreasm_v7m.s
@@ -73,7 +73,10 @@ _port_thread_start PROC
  */

                 EXPORT  _port_switch_from_isr

 _port_switch_from_isr PROC

+                bl      chSchIsRescRequiredExI

+                cbz     r0, noreschedule

                 bl      chSchDoRescheduleI

+noreschedule

 #if CORTEX_SIMPLIFIED_PRIORITY

                 mov     r3, #SCB_ICSR :AND: 0xFFFF

                 movt    r3, #SCB_ICSR :SHR: 16

@@ -100,20 +103,16 @@ _port_irq_epilogue PROC
                 mov     r3, #SCB_ICSR :AND: 0xFFFF

                 movt    r3, #SCB_ICSR :SHR: 16

                 ldr     r3, [r3, #0]

-                tst     r3, #ICSR_RETTOBASE

+                ands    r3, r3, #ICSR_RETTOBASE

                 bne     skipexit

 #if CORTEX_SIMPLIFIED_PRIORITY

                 cpsie   i

 #else

-                movs    r3, #CORTEX_BASEPRI_DISABLED

+                /* Note, R3 is already zero.*/

                 msr     BASEPRI, r3

 #endif

                 bx      lr

 skipexit

-                push    {r3, lr}

-                bl      chSchIsRescRequiredExI

-                cmp     r0, #0

-                beq     noreschedule

                 mrs     r3, PSP

                 subs    r3, r3, #EXTCTX_SIZE

                 msr     PSP, r3

@@ -121,15 +120,7 @@ skipexit
                 str     r2, [r3, #24]

                 mov     r2, #0x01000000

                 str     r2, [r3, #28]

-                pop     {r3, pc}

-noreschedule

-#if CORTEX_SIMPLIFIED_PRIORITY

-                cpsie   i

-#else

-                movs    r3, #CORTEX_BASEPRI_DISABLED

-                msr     BASEPRI, r3

-#endif

-                pop     {r3, pc}

+                bx      lr

                 ENDP

 

 /*

@@ -146,6 +137,7 @@ SVCallVector    PROC
                 movs    r3, #CORTEX_BASEPRI_DISABLED

                 msr     BASEPRI, r3

                 bx      lr

+                nop

                 ENDP

 #endif