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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-02-15 15:23:50 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-02-15 15:23:50 +0000 |
| commit | 0c57f0a00bc194ddcba02ea64c79ce0dcc63af0f (patch) | |
| tree | 1cd18cad758388bea5f49ec7a772190ce18491b1 /os/ports/GCC/PPC | |
| parent | a3c4ffa3341bbf03f47ef688ae71ce5e357d0604 (diff) | |
| download | ChibiOS-0c57f0a00bc194ddcba02ea64c79ce0dcc63af0f.tar.gz ChibiOS-0c57f0a00bc194ddcba02ea64c79ce0dcc63af0f.tar.bz2 ChibiOS-0c57f0a00bc194ddcba02ea64c79ce0dcc63af0f.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5190 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/ports/GCC/PPC')
| -rw-r--r-- | os/ports/GCC/PPC/SPC560Pxx/core.s | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/os/ports/GCC/PPC/SPC560Pxx/core.s b/os/ports/GCC/PPC/SPC560Pxx/core.s index 246c39739..245887f28 100644 --- a/os/ports/GCC/PPC/SPC560Pxx/core.s +++ b/os/ports/GCC/PPC/SPC560Pxx/core.s @@ -72,6 +72,55 @@ .type _coreinit, @function
_coreinit:
/*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor %r0, %r0, %r0
+ xor %r1, %r1, %r1
+ xor %r2, %r2, %r2
+ xor %r3, %r3, %r3
+ xor %r4, %r4, %r4
+ xor %r5, %r5, %r5
+ xor %r6, %r6, %r6
+ xor %r7, %r7, %r7
+ xor %r8, %r8, %r8
+ xor %r9, %r9, %r9
+ xor %r10, %r10, %r10
+ xor %r11, %r11, %r11
+ xor %r12, %r12, %r12
+ xor %r13, %r13, %r13
+ xor %r14, %r14, %r14
+ xor %r15, %r15, %r15
+ xor %r16, %r16, %r16
+ xor %r17, %r17, %r17
+ xor %r18, %r18, %r18
+ xor %r19, %r19, %r19
+ xor %r20, %r20, %r20
+ xor %r21, %r21, %r21
+ xor %r22, %r22, %r22
+ xor %r23, %r23, %r23
+ xor %r24, %r24, %r24
+ xor %r25, %r25, %r25
+ xor %r26, %r26, %r26
+ xor %r27, %r27, %r27
+ xor %r28, %r28, %r28
+ xor %r29, %r29, %r29
+ xor %r30, %r30, %r30
+ xor %r31, %r31, %r31
+ lis %r4, __ram_start__@h
+ ori %r4, %r4, __ram_start__@l
+ lis %r5, __ram_end__@h
+ ori %r5, %r5, __ram_end__@l
+.cleareccloop:
+ cmpl %cr0, %r4, %r5
+ bge %cr0, .cleareccend
+ stmw %r16, 0(%r4)
+ addi %r4, %r4, 64
+ b .cleareccloop
+.cleareccend:
+
+ /*
* Branch prediction enabled.
*/
li %r3, BUCSR_DEFAULT
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