git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2966 35acf78f-673a-0410-8e92-d51de3d6d3f4

5 files changed, 285 insertions, 230 deletions

diff --git a/os/ports/GCC/ARMCMx/chcore.h b/os/ports/GCC/ARMCMx/chcore.h
index c58b7bb3a..42df48a09 100644
--- a/os/ports/GCC/ARMCMx/chcore.h
+++ b/os/ports/GCC/ARMCMx/chcore.h
@@ -35,10 +35,10 @@
 /* Port constants.                                                           */

 /*===========================================================================*/

 

-#define CORTEX_M0                   0   /**< @brief Cortex-M0 variant.      */

-#define CORTEX_M1                   1   /**< @brief Cortex-M1 variant.      */

-#define CORTEX_M3                   3   /**< @brief Cortex-M3 variant.      */

-#define CORTEX_M4                   4   /**< @brief Cortex-M4 variant.      */

+#define CORTEX_M0                       0   /**< @brief Cortex-M0 variant.  */

+#define CORTEX_M1                       1   /**< @brief Cortex-M1 variant.  */

+#define CORTEX_M3                       3   /**< @brief Cortex-M3 variant.  */

+#define CORTEX_M4                       4   /**< @brief Cortex-M4 variant.  */

 

 /* Inclusion of the Cortex-Mx implementation specific parameters.*/

 #include "cmparams.h"

@@ -51,33 +51,29 @@
 #error "unknown or unsupported Cortex-M model"

 #endif

 

-/*===========================================================================*/

-/* Port statically derived parameters.                                       */

-/*===========================================================================*/

-

 /**

  * @brief   Total priority levels.

  */

-#define CORTEX_PRIORITY_LEVELS      (1 << CORTEX_PRIORITY_BITS)

+#define CORTEX_PRIORITY_LEVELS          (1 << CORTEX_PRIORITY_BITS)

 

 /**

  * @brief   Minimum priority level.

  * @details This minimum priority level is calculated from the number of

  *          priority bits supported by the specific Cortex-Mx implementation.

  */

-#define CORTEX_MINIMUM_PRIORITY     (CORTEX_PRIORITY_LEVELS - 1)

+#define CORTEX_MINIMUM_PRIORITY         (CORTEX_PRIORITY_LEVELS - 1)

 

 /**

  * @brief   Maximum priority level.

  * @details The maximum allowed priority level is always zero.

  */

-#define CORTEX_MAXIMUM_PRIORITY     0

+#define CORTEX_MAXIMUM_PRIORITY         0

 

 /**

  * @brief   Disabled value for BASEPRI register.

  * @note    ARMv7-M architecture only.

  */

-#define CORTEX_BASEPRI_DISABLED     0

+#define CORTEX_BASEPRI_DISABLED         0

 

 /*===========================================================================*/

 /* Port macros.                                                              */

@@ -100,74 +96,55 @@
 /*===========================================================================*/

 

 /**

- * @brief   Enables the use of the WFI instruction in the idle thread loop.

+ * @brief   Stack size for the system idle thread.

+ * @details This size depends on the idle thread implementation, usually

+ *          the idle thread should take no more space than those reserved

+ *          by @p PORT_INT_REQUIRED_STACK.

+ * @note    In this port it is set to 16 because the idle thread does have

+ *          a stack frame when compiling without optimizations. You may

+ *          reduce this value to zero when compiling with optimizations.

  */

-#ifndef CORTEX_ENABLE_WFI_IDLE

-#define CORTEX_ENABLE_WFI_IDLE      FALSE

+#ifndef PORT_IDLE_THREAD_STACK_SIZE

+#define PORT_IDLE_THREAD_STACK_SIZE     16

 #endif

 

 /**

- * @brief   SYSTICK handler priority.

- * @note    The default SYSTICK handler priority is calculated as the priority

- *          level in the middle of the numeric priorities range.

+ * @brief   Per-thread stack overhead for interrupts servicing.

+ * @details This constant is used in the calculation of the correct working

+ *          area size.

+ *          This value can be zero on those architecture where there is a

+ *          separate interrupt stack and the stack space between @p intctx and

+ *          @p extctx is known to be zero.

+ * @note    In this port it is conservatively set to 16 because the function

+ *          @p chSchDoRescheduleI() can have a stack frame, expecially with

+ *          compiler optimizations disabled.

  */

-#ifndef CORTEX_PRIORITY_SYSTICK

-#define CORTEX_PRIORITY_SYSTICK     (CORTEX_PRIORITY_LEVELS >> 1)

-#else

-/* If it is externally redefined then better perform a validity check on it.*/

-#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK)

-#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK"

-#endif

+#ifndef PORT_INT_REQUIRED_STACK

+#define PORT_INT_REQUIRED_STACK         16

 #endif

 

 /**

- * @brief   SVCALL handler priority.

- * @note    The default SVCALL handler priority is calculated as

- *          @p CORTEX_MAXIMUM_PRIORITY+1, in the ARMv7-M port this reserves

- *          the @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts

- *          priority level.

- * @note    The SVCALL vector is only used in the ARMv7-M port, it is available

- *          to user in the ARMv6-M port.

+ * @brief   Enables the use of the WFI instruction in the idle thread loop.

  */

-#ifndef CORTEX_PRIORITY_SVCALL

-#define CORTEX_PRIORITY_SVCALL      (CORTEX_MAXIMUM_PRIORITY + 1)

-#else

-/* If it is externally redefined then better perform a validity check on it.*/

-#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL)

-#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL"

-#endif

+#ifndef CORTEX_ENABLE_WFI_IDLE

+#define CORTEX_ENABLE_WFI_IDLE          FALSE

 #endif

 

 /**

- * @brief   PENDSV handler priority.

- * @note    The default PENDSV handler priority is set at the

- *          @p CORTEX_MINIMUM_PRIORITY priority level.

- * @note    The PENDSV vector is only used in the ARMv7-M legacy port, it is

- *          available to user in the ARMv6-M and ARMv7-M ports.

- * @note    In the ARMv7-M legacy port this value should be not changed from

- *          the minimum priority level.

+ * @brief   SYSTICK handler priority.

+ * @note    The default SYSTICK handler priority is calculated as the priority

+ *          level in the middle of the numeric priorities range.

  */

-#ifndef CORTEX_PRIORITY_PENDSV

-#define CORTEX_PRIORITY_PENDSV      CORTEX_MINIMUM_PRIORITY

+#ifndef CORTEX_PRIORITY_SYSTICK

+#define CORTEX_PRIORITY_SYSTICK         (CORTEX_PRIORITY_LEVELS >> 1)

 #else

 /* If it is externally redefined then better perform a validity check on it.*/

-#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_PENDSV)

-#error "invalid priority level specified for CORTEX_PRIORITY_PENDSV"

+#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK)

+#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK"

 #endif

 #endif

 

 /**

- * @brief   BASEPRI level within kernel lock.

- * @note    This value must not mask the SVCALL priority level or the

- *          kernel would hard fault.

- * @note    ARMv7-M architecture only.

- */

-#ifndef CORTEX_BASEPRI_KERNEL

-#define CORTEX_BASEPRI_KERNEL                                               \

-  CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL+1)

-#endif

-

-/**

  * @brief   Stack alignment enforcement.

  * @note    The default value is 64 in order to comply with EABI, reducing

  *          the value to 32 can save some RAM space if you don't care about

@@ -175,10 +152,14 @@
  * @note    Allowed values are 32 or 64.

  */

 #ifndef CORTEX_STACK_ALIGNMENT

-#define CORTEX_STACK_ALIGNMENT      64

+#define CORTEX_STACK_ALIGNMENT          64

 #endif

 

 /*===========================================================================*/

+/* Port derived parameters.                                                  */

+/*===========================================================================*/

+

+/*===========================================================================*/

 /* Port exported info.                                                       */

 /*===========================================================================*/

 

@@ -187,57 +168,10 @@
  */

 #define CH_ARCHITECTURE_ARM

 

-#if defined(__DOXYGEN__)

-/**

- * @brief   Macro defining the specific ARM architecture.

- * @note    This macro is for documentation only, the real name changes

- *          depending on the selected architecture, the possible names are:

- *          - CH_ARCHITECTURE_ARM_v6M.

- *          - CH_ARCHITECTURE_ARM_v7M.

- *          .

- */

-#define CH_ARCHITECTURE_ARM_vxm

-

 /**

- * @brief   Name of the implemented architecture.

- * @note    The value is for documentation only, the real value changes

- *          depending on the selected architecture, the possible values are:

- *          - "ARMv6-M".

- *          - "ARMv7-M".

- *          - "ARMv7-ME".

- *          .

+ * @brief   Name of the compiler supported by this port.

  */

-#define CH_ARCHITECTURE_NAME        "ARMvx-M"

-

-/**

- * @brief   Name of the architecture variant (optional).

- * @note    The value is for documentation only, the real value changes

- *          depending on the selected architecture, the possible values are:

- *          - "Cortex-M0"

- *          - "Cortex-M1"

- *          - "Cortex-M3"

- *          - "Cortex-M4"

- *          .

- */

-#define CH_CORE_VARIANT_NAME        "Cortex-Mx"

-

-#elif CORTEX_MODEL == CORTEX_M4

-#define CH_ARCHITECTURE_ARM_v7M

-#define CH_ARCHITECTURE_NAME        "ARMv7-ME"

-#define CH_CORE_VARIANT_NAME        "Cortex-M4"

-#elif CORTEX_MODEL == CORTEX_M3

-#define CH_ARCHITECTURE_ARM_v7M

-#define CH_ARCHITECTURE_NAME        "ARMv7-M"

-#define CH_CORE_VARIANT_NAME        "Cortex-M3"

-#elif CORTEX_MODEL == CORTEX_M1

-#define CH_ARCHITECTURE_ARM_v6M

-#define CH_ARCHITECTURE_NAME        "ARMv6-M"

-#define CH_CORE_VARIANT_NAME        "Cortex-M1"

-#elif CORTEX_MODEL == CORTEX_M0

-#define CH_ARCHITECTURE_ARM_v6M

-#define CH_ARCHITECTURE_NAME        "ARMv6-M"

-#define CH_CORE_VARIANT_NAME        "Cortex-M0"

-#endif

+#define CH_COMPILER_NAME                "GCC "__VERSION__

 

 /*===========================================================================*/

 /* Port implementation part (common).                                        */

@@ -295,6 +229,20 @@ struct context {
 };

 

 /**

+ * @brief   Platform dependent part of the @p chThdCreateI() API.

+ * @details This code usually setup the context switching frame represented

+ *          by an @p intctx structure.

+ */

+#define SETUP_CONTEXT(workspace, wsize, pf, arg) {                          \

+  tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace +                  \

+                                     wsize -                                \

+                                     sizeof(struct intctx));                \

+  tp->p_ctx.r13->r4 = pf;                                                   \

+  tp->p_ctx.r13->r5 = arg;                                                  \

+  tp->p_ctx.r13->lr = _port_thread_start;                                   \

+}

+

+/**

  * @brief   Enforces a correct alignment for a stack area size value.

  */

 #define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)

@@ -302,10 +250,10 @@ struct context {
 /**

  * @brief   Computes the thread working area global size.

  */

-#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) +                     \

-                                   sizeof(struct intctx) +              \

-                                   sizeof(struct extctx) +              \

-                                   (n) + (INT_REQUIRED_STACK))

+#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) +                         \

+                                   sizeof(struct intctx) +                  \

+                                   sizeof(struct extctx) +                  \

+                                   (n) + (PORT_INT_REQUIRED_STACK))

 

 /**

  * @brief   Static working area allocation.

@@ -315,9 +263,9 @@ struct context {
 #define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]

 

 /* Includes the architecture-specific implementation part.*/

-#if defined(CH_ARCHITECTURE_ARM_v6M)

+#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1)

 #include "chcore_v6m.h"

-#elif defined(CH_ARCHITECTURE_ARM_v7M)

+#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4)

 #include "chcore_v7m.h"

 #endif

 

diff --git a/os/ports/GCC/ARMCMx/chcore_v6m.h b/os/ports/GCC/ARMCMx/chcore_v6m.h
index 0212fe6b3..3154bde56 100644
--- a/os/ports/GCC/ARMCMx/chcore_v6m.h
+++ b/os/ports/GCC/ARMCMx/chcore_v6m.h
@@ -30,6 +30,57 @@
 #define _CHCORE_V6M_H_

 

 /*===========================================================================*/

+/* Port constants.                                                           */

+/*===========================================================================*/

+

+/**

+ * @brief   BASEPRI level within kernel lock.

+ * @note    The ARMv6-M architecture does not implement the BASEPRI register

+ *          so the kernel always masks the whole priority range during

+ *          a kernel lock.

+ */

+#define CORTEX_BASEPRI_KERNEL           0

+

+/**

+ * @brief   PendSV priority level.

+ * @note    This priority is enforced to be equal to @p CORTEX_BASEPRI_KERNEL,

+ *          this handler always have the highest priority that cannot preempt

+ *          the kernel.

+ */

+#define CORTEX_PRIORITY_PENDSV          CORTEX_BASEPRI_KERNEL

+

+/*===========================================================================*/

+/* Port configurable parameters.                                             */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Port derived parameters.                                                  */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Port exported info.                                                       */

+/*===========================================================================*/

+

+/**

+ * @brief   Macro defining the specific ARM architecture.

+ */

+#define CH_ARCHITECTURE_ARM_v7M

+

+/**

+ * @brief   Name of the implemented architecture.

+ */

+#define CH_ARCHITECTURE_NAME            "ARMv6-M"

+

+/**

+ * @brief   Name of the architecture variant.

+ */

+#if (CORTEX_MODEL == CORTEX_M0) || defined(__DOXYGEN__)

+#define CH_CORE_VARIANT_NAME            "Cortex-M0"

+#elif (CORTEX_MODEL == CORTEX_M1)

+#define CH_CORE_VARIANT_NAME            "Cortex-M1"

+#endif

+

+/*===========================================================================*/

 /* Port implementation part.                                                 */

 /*===========================================================================*/

 

@@ -59,48 +110,6 @@ struct intctx {
 #endif

 

 /**

- * @brief   Platform dependent part of the @p chThdCreateI() API.

- * @details This code usually setup the context switching frame represented

- *          by an @p intctx structure.

- */

-#define SETUP_CONTEXT(workspace, wsize, pf, arg) {                          \

-  tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace +                  \

-                                     wsize -                                \

-                                     sizeof(struct intctx));                \

-  tp->p_ctx.r13->r4 = pf;                                                   \

-  tp->p_ctx.r13->r5 = arg;                                                  \

-  tp->p_ctx.r13->lr = _port_thread_start;                                   \

-}

-

-/**

- * @brief   Stack size for the system idle thread.

- * @details This size depends on the idle thread implementation, usually

- *          the idle thread should take no more space than those reserved

- *          by @p INT_REQUIRED_STACK.

- * @note    In this port it is set to 8 because the idle thread does have

- *          a stack frame when compiling without optimizations. You may

- *          reduce this value to zero when compiling with optimizations.

- */

-#ifndef IDLE_THREAD_STACK_SIZE

-#define IDLE_THREAD_STACK_SIZE      16

-#endif

-

-/**

- * @brief   Per-thread stack overhead for interrupts servicing.

- * @details This constant is used in the calculation of the correct working

- *          area size.

- *          This value can be zero on those architecture where there is a

- *          separate interrupt stack and the stack space between @p intctx and

- *          @p extctx is known to be zero.

- * @note    In this port it is conservatively set to 16 because the function

- *          @p chSchDoRescheduleI() can have a stack frame, expecially with

- *          compiler optimizations disabled.

- */

-#ifndef INT_REQUIRED_STACK

-#define INT_REQUIRED_STACK          16

-#endif

-

-/**

  * @brief   IRQ prologue code.

  * @details This macro must be inserted at the start of all IRQ handlers

  *          enabled to invoke system APIs.

@@ -135,6 +144,8 @@ struct intctx {
  */

 #define port_init() {                                                       \

   SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0);                            \

+  NVICSetSystemHandlerPriority(HANDLER_PENDSV,                              \

+    CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV));                          \

   NVICSetSystemHandlerPriority(HANDLER_SYSTICK,                             \

     CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK));                         \

 }

diff --git a/os/ports/GCC/ARMCMx/chcore_v7m.c b/os/ports/GCC/ARMCMx/chcore_v7m.c
index c71102127..da3f7b956 100644
--- a/os/ports/GCC/ARMCMx/chcore_v7m.c
+++ b/os/ports/GCC/ARMCMx/chcore_v7m.c
@@ -28,7 +28,6 @@
 

 #include "ch.h"

 

-#if !defined(CH_CURRP_REGISTER_CACHE) || defined(__DOXXYGEN__)

 /**

  * @brief   Internal context stacking.

  */

@@ -44,17 +43,6 @@
   asm volatile ("pop     {r4, r5, r6, r7, r8, r9, r10, r11, pc}"            \

                 : : : "memory");                                            \

 }

-#else /* defined(CH_CURRP_REGISTER_CACHE) */

-#define PUSH_CONTEXT() {                                                    \

-  asm volatile ("push    {r4, r5, r6, r8, r9, r10, r11, lr}"                \

-                : : : "memory");                                            \

-}

-

-#define POP_CONTEXT() {                                                     \

-  asm volatile ("pop     {r4, r5, r6, r8, r9, r10, r11, pc}"                \

-                 : : : "memory");                                           \

-}

-#endif /* defined(CH_CURRP_REGISTER_CACHE) */

 

 #if !CH_OPTIMIZE_SPEED

 void _port_lock(void) {

@@ -84,10 +72,12 @@ CH_IRQ_HANDLER(SysTickVector) {
   CH_IRQ_EPILOGUE();

 }

 

+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)

 /**

  * @brief   SVC vector.

  * @details The SVC vector is used for exception mode re-entering after a

  *          context switch.

+ * @note    The PendSV vector is only used in advanced kernel mode.

  */

 void SVCallVector(void) {

   register struct extctx *ctxp;

@@ -99,6 +89,25 @@ void SVCallVector(void) {
   asm volatile ("msr     PSP, %0" : : "r" (ctxp) : "memory");

   port_unlock_from_isr();

 }

+#endif /* !CORTEX_SIMPLIFIED_PRIORITY */

+

+#if CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)

+/**

+ * @brief   PendSV vector.

+ * @details The PendSV vector is used for exception mode re-entering after a

+ *          context switch.

+ * @note    The PendSV vector is only used in normal kernel mode.

+ */

+void PendSVVector(void) {

+  register struct extctx *ctxp;

+

+  /* Discarding the current exception context and positioning the stack to

+     point to the real one.*/

+  asm volatile ("mrs     %0, PSP" : "=r" (ctxp) : : "memory");

+  ctxp++;

+  asm volatile ("msr     PSP, %0" : : "r" (ctxp) : "memory");

+}

+#endif /* CORTEX_SIMPLIFIED_PRIORITY */

 

 /**

  * @brief   Reschedule verification and setup after an IRQ.

@@ -134,7 +143,14 @@ __attribute__((naked))
 void _port_switch_from_isr(void) {

 

   chSchDoRescheduleI();

+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)

   asm volatile ("svc     #0");

+#else /* CORTEX_SIMPLIFIED_PRIORITY */

+  SCB_ICSR = ICSR_PENDSVSET;

+  port_unlock();

+  while (TRUE)

+    ;

+#endif /* CORTEX_SIMPLIFIED_PRIORITY */

 }

 

 /**

diff --git a/os/ports/GCC/ARMCMx/chcore_v7m.h b/os/ports/GCC/ARMCMx/chcore_v7m.h
index a7f02aece..ef7860b87 100644
--- a/os/ports/GCC/ARMCMx/chcore_v7m.h
+++ b/os/ports/GCC/ARMCMx/chcore_v7m.h
@@ -30,6 +30,93 @@
 #define _CHCORE_V7M_H_

 

 /*===========================================================================*/

+/* Port constants.                                                           */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Port configurable parameters.                                             */

+/*===========================================================================*/

+

+/**

+ * @brief   Simplified priority handling flag.

+ * @details Activating this option will make the Kernel work in normal mode.

+ */

+#ifndef CORTEX_SIMPLIFIED_PRIORITY

+#define CORTEX_SIMPLIFIED_PRIORITY      FALSE

+#endif

+

+/**

+ * @brief   SVCALL handler priority.

+ * @note    The default SVCALL handler priority is defaulted to

+ *          @p CORTEX_MAXIMUM_PRIORITY+1, this reserves the

+ *          @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts

+ *          priority level.

+ */

+#ifndef CORTEX_PRIORITY_SVCALL

+#define CORTEX_PRIORITY_SVCALL          (CORTEX_MAXIMUM_PRIORITY + 1)

+#else

+/* If it is externally redefined then better perform a validity check on it.*/

+#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL)

+#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL"

+#endif

+#endif

+

+/*===========================================================================*/

+/* Port derived parameters.                                                  */

+/*===========================================================================*/

+

+/**

+ * @brief   BASEPRI level within kernel lock.

+ * @note    In normal kernel mode this constant value is enforced to zero.

+ */

+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)

+#define CORTEX_BASEPRI_KERNEL                                               \

+  CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL+1)

+#else

+#define CORTEX_BASEPRI_KERNEL           0

+#endif

+

+/**

+ * @brief   PendSV priority level.

+ * @note    This priority is enforced to be equal to @p CORTEX_BASEPRI_KERNEL,

+ *          this handler always have the highest priority that cannot preempt

+ *          the kernel.

+ */

+#define CORTEX_PRIORITY_PENDSV          CORTEX_BASEPRI_KERNEL

+

+/*===========================================================================*/

+/* Port exported info.                                                       */

+/*===========================================================================*/

+

+/**

+ * @brief   Macro defining the specific ARM architecture.

+ */

+#define CH_ARCHITECTURE_ARM_v7M

+

+/**

+ * @brief   Name of the implemented architecture.

+ */

+#define CH_ARCHITECTURE_NAME            "ARMv7-M"

+

+/**

+ * @brief   Name of the architecture variant.

+ */

+#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)

+#define CH_CORE_VARIANT_NAME            "Cortex-M3"

+#elif (CORTEX_MODEL == CORTEX_M4)

+#define CH_CORE_VARIANT_NAME            "Cortex-M4"

+#endif

+

+/**

+ * @brief   Port-specific information string.

+ */

+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)

+#define CH_PORT_INFO                    "Advanced kernel mode"

+#else

+#define CH_PORT_INFO                    "Normal kernel mode"

+#endif

+

+/*===========================================================================*/

 /* Port implementation part.                                                 */

 /*===========================================================================*/

 

@@ -49,9 +136,7 @@ struct intctx {
   regarm_t      r4;

   regarm_t      r5;

   regarm_t      r6;

-#ifndef CH_CURRP_REGISTER_CACHE

   regarm_t      r7;

-#endif

   regarm_t      r8;

   regarm_t      r9;

   regarm_t      r10;

@@ -61,48 +146,6 @@ struct intctx {
 #endif

 

 /**

- * @brief   Platform dependent part of the @p chThdCreateI() API.

- * @details This code usually setup the context switching frame represented

- *          by an @p intctx structure.

- */

-#define SETUP_CONTEXT(workspace, wsize, pf, arg) {                          \

-  tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace +                  \

-                                     wsize -                                \

-                                     sizeof(struct intctx));                \

-  tp->p_ctx.r13->r4 = pf;                                                   \

-  tp->p_ctx.r13->r5 = arg;                                                  \

-  tp->p_ctx.r13->lr = _port_thread_start;                                   \

-}

-

-/**

- * @brief   Stack size for the system idle thread.

- * @details This size depends on the idle thread implementation, usually

- *          the idle thread should take no more space than those reserved

- *          by @p INT_REQUIRED_STACK.

- * @note    In this port it is set to 8 because the idle thread does have

- *          a stack frame when compiling without optimizations. You may

- *          reduce this value to zero when compiling with optimizations.

- */

-#ifndef IDLE_THREAD_STACK_SIZE

-#define IDLE_THREAD_STACK_SIZE      8

-#endif

-

-/**

- * @brief   Per-thread stack overhead for interrupts servicing.

- * @details This constant is used in the calculation of the correct working

- *          area size.

- *          This value can be zero on those architecture where there is a

- *          separate interrupt stack and the stack space between @p intctx and

- *          @p extctx is known to be zero.

- * @note    In this port it is conservatively set to 16 because the function

- *          @p chSchDoRescheduleI() can have a stack frame, expecially with

- *          compiler optimizations disabled.

- */

-#ifndef INT_REQUIRED_STACK

-#define INT_REQUIRED_STACK          16

-#endif

-

-/**

  * @brief   IRQ prologue code.

  * @details This macro must be inserted at the start of all IRQ handlers

  *          enabled to invoke system APIs.

@@ -137,6 +180,8 @@ struct intctx {
   SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0);                            \

   NVICSetSystemHandlerPriority(HANDLER_SVCALL,                              \

     CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL));                          \

+  NVICSetSystemHandlerPriority(HANDLER_PENDSV,                              \

+    CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV));                          \

   NVICSetSystemHandlerPriority(HANDLER_SYSTICK,                             \

     CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK));                         \

 }

@@ -147,16 +192,20 @@ struct intctx {
  *          more actions.

  * @note    In this port this it raises the base priority to kernel level.

  */

-#if CH_OPTIMIZE_SPEED

+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)

+#if CH_OPTIMIZE_SPEED || defined(__DOXYGEN__)

 #define port_lock() {                                                       \

   register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL;                 \

   asm volatile ("msr     BASEPRI, %0" : : "r" (tmp) : "memory");            \

 }

-#else

+#else /* !CH_OPTIMIZE_SPEED */

 #define port_lock() {                                                       \

   asm volatile ("bl      _port_lock" : : : "r3", "lr", "memory");           \

 }

-#endif

+#endif /* !CH_OPTIMIZE_SPEED */

+#else /* CORTEX_SIMPLIFIED_PRIORITY */

+#define port_lock() asm volatile ("cpsid   i" : : : "memory")

+#endif /* CORTEX_SIMPLIFIED_PRIORITY */

 

 /**

  * @brief   Kernel-unlock action.

@@ -164,16 +213,20 @@ struct intctx {
  *          more actions.

  * @note    In this port this it lowers the base priority to user level.

  */

-#if CH_OPTIMIZE_SPEED

+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)

+#if CH_OPTIMIZE_SPEED || defined(__DOXYGEN__)

 #define port_unlock() {                                                     \

   register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED;               \

   asm volatile ("msr     BASEPRI, %0" : : "r" (tmp) : "memory");            \

 }

-#else

+#else /* !CH_OPTIMIZE_SPEED */

 #define port_unlock() {                                                     \

   asm volatile ("bl      _port_unlock" : : : "r3", "lr", "memory");         \

 }

-#endif

+#endif /* !CH_OPTIMIZE_SPEED */

+#else /* CORTEX_SIMPLIFIED_PRIORITY */

+#define port_unlock() asm volatile ("cpsie   i" : : : "memory")

+#endif /* CORTEX_SIMPLIFIED_PRIORITY */

 

 /**

  * @brief   Kernel-lock action from an interrupt handler.

@@ -206,21 +259,29 @@ struct intctx {
  * @note    Interrupt sources above kernel level remains enabled.

  * @note    In this port it raises/lowers the base priority to kernel level.

  */

+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)

 #define port_suspend() {                                                    \

   register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL;                 \

   asm volatile ("msr     BASEPRI, %0                    \n\t"               \

                 "cpsie   i" : : "r" (tmp) : "memory");                      \

 }

+#else /* CORTEX_SIMPLIFIED_PRIORITY */

+#define port_suspend() asm volatile ("cpsid   i" : : : "memory")

+#endif /* CORTEX_SIMPLIFIED_PRIORITY */

 

 /**

  * @brief   Enables all the interrupt sources.

  * @note    In this port it lowers the base priority to user level.

  */

+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)

 #define port_enable() {                                                     \

   register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED;               \

   asm volatile ("msr     BASEPRI, %0                    \n\t"               \

                 "cpsie   i" : : "r" (tmp) : "memory");                      \

 }

+#else /* CORTEX_SIMPLIFIED_PRIORITY */

+#define port_enable() asm volatile ("cpsie   i" : : : "memory")

+#endif /* CORTEX_SIMPLIFIED_PRIORITY */

 

 /**

  * @brief   Enters an architecture-dependent IRQ-waiting mode.

diff --git a/os/ports/GCC/ARMCMx/port.dox b/os/ports/GCC/ARMCMx/port.dox
index 27e321f21..8f4a9bd51 100644
--- a/os/ports/GCC/ARMCMx/port.dox
+++ b/os/ports/GCC/ARMCMx/port.dox
@@ -26,9 +26,28 @@
  * This port supports all the cores implementing the ARMv6-M and ARMv7-M

  * architectures.

  *

- * @section ARMCMx_STATES_A System logical states in ARMv6-M mode

- * The ChibiOS/RT logical @ref system_states are mapped as follow in the ARM

- * Cortex-M0 port:

+ * @section ARMCMx_MODES Kernel Modes

+ * The Cortex-Mx port supports two distinct kernel modes:

+ * - <b>Normal Kernel</b> mode. In this mode the kernel handles IRQ priorities

+ *   in a simplified way, all interrupt sources are disabled when the kernel

+ *   enters into a critical zone and re-enabled on exit. This is simple and

+ *   adequate for most applications, this mode results in a more compact and

+ *   faster kernel.

+ * - <b>Advanced Kernel</b> mode. In this mode the kernel only masks

+ *   interrupt sources with priorities below or equal to the

+ *   @p CORTEX_BASEPRI_KERNEL level. Higher priorities are not affected by

+ *   the kernel critical sections and can be used for fast interrupts.

+ *   This mode is not available in the ARMv6-M architecture which does not

+ *   support priority masking.

+ * .

+ * The selection of the mode is performed using the port configuration option

+ * @p CORTEX_SIMPLIFIED_PRIORITY. Apart from the different handling of

+ * interrupts there are no other differences between the two modes. The

+ * kernel API is exactly the same.

+ *

+ * @section ARMCMx_STATES_A System logical states in Normal Kernel mode

+ * The ChibiOS/RT logical @ref system_states are mapped as follow in Normal

+ * Kernel mode:

  * - <b>Init</b>. This state is represented by the startup code and the

  *   initialization code before @p chSysInit() is executed. It has not a

  *   special hardware state associated.

@@ -53,21 +72,21 @@
  *   mode.

  * - <b>Serving Fast Interrupt</b>. This state is not implemented in the

  *   ARMv6-M implementation.

- * - <b>Serving Non-Maskable Interrupt</b>. The Cortex-M3 has a specific

+ * - <b>Serving Non-Maskable Interrupt</b>. The Cortex-Mx has a specific

  *   asynchronous NMI vector and several synchronous fault vectors that can

  *   be considered belonging to this category.

  * - <b>Halted</b>. Implemented as an infinite loop after globally masking all

  *   the maskable interrupt sources. The ARM state is whatever the processor

  *   was running when @p chSysHalt() was invoked.

  *

- * @section ARMCMx_STATES_B System logical states in ARMv7-M mode

- * The ChibiOS/RT logical @ref system_states are mapped as follow in the ARM

- * Cortex-M3 port:

+ * @section ARMCMx_STATES_B System logical states in Advanced Kernel mode

+ * The ChibiOS/RT logical @ref system_states are mapped as follow in the

+ * Advanced Kernel mode:

  * - <b>Init</b>. This state is represented by the startup code and the

  *   initialization code before @p chSysInit() is executed. It has not a

  *   special hardware state associated.

  * - <b>Normal</b>. This is the state the system has after executing

- *   @p chSysInit(). In this state the ARM Cortex-M3 has the BASEPRI register

+ *   @p chSysInit(). In this state the ARM Cortex-Mx has the BASEPRI register

  *   set at @p CORTEX_BASEPRI_USER level, interrupts are not masked. The

  *   processor is running in thread-privileged mode.

  * - <b>Suspended</b>. In this state the interrupt sources are not globally

@@ -93,7 +112,7 @@
  * - <b>Serving Fast Interrupt</b>. It is basically the same of the SRI state

  *   but it is not possible to switch to the I-Locked state because fast

  *   interrupts can preempt the kernel critical zone.

- * - <b>Serving Non-Maskable Interrupt</b>. The Cortex-M3 has a specific

+ * - <b>Serving Non-Maskable Interrupt</b>. The Cortex-Mx has a specific

  *   asynchronous NMI vector and several synchronous fault vectors that can

  *   be considered belonging to this category.

  * - <b>Halted</b>. Implemented as an infinite loop after globally masking all