diff options
| author | barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-06-07 14:34:59 +0000 |
|---|---|---|
| committer | barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-06-07 14:34:59 +0000 |
| commit | 5cad241306f64d0a3c0f7829421e4bf8f4b18fbe (patch) | |
| tree | ebbcad6d0cdb19fa5ef0bf5f6dc5cf80dfbdc4d1 /os/ports/GCC/ARMCMx | |
| parent | 152f34a80c6ffe5fd17809732272823091b854e8 (diff) | |
| parent | aec912f13f9aa85cd677353fa556f679c3832970 (diff) | |
| download | ChibiOS-5cad241306f64d0a3c0f7829421e4bf8f4b18fbe.tar.gz ChibiOS-5cad241306f64d0a3c0f7829421e4bf8f4b18fbe.tar.bz2 ChibiOS-5cad241306f64d0a3c0f7829421e4bf8f4b18fbe.zip | |
I2C. Merged code from trunk.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3036 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/ports/GCC/ARMCMx')
24 files changed, 804 insertions, 395 deletions
diff --git a/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h b/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h index 927a729e0..4016e6aa1 100644 --- a/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h +++ b/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h @@ -1,5 +1,6 @@ /*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
diff --git a/os/ports/GCC/ARMCMx/LPC11xx/port.mk b/os/ports/GCC/ARMCMx/LPC11xx/port.mk index 886add45d..a38729958 100644 --- a/os/ports/GCC/ARMCMx/LPC11xx/port.mk +++ b/os/ports/GCC/ARMCMx/LPC11xx/port.mk @@ -1,10 +1,11 @@ # List of the ChibiOS/RT Cortex-M0 LPC11xx port files.
-PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC11xx/vectors.c \
+PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \
+ $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC11xx/vectors.c \
${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v6m.c \
${CHIBIOS}/os/ports/GCC/ARMCMx/nvic.c
-PORTASM = ${CHIBIOS}/os/ports/GCC/ARMCMx/crt0_v6m.s
+PORTASM =
PORTINC = ${CHIBIOS}/os/ports/GCC/ARMCMx \
${CHIBIOS}/os/ports/GCC/ARMCMx/LPC11xx
diff --git a/os/ports/GCC/ARMCMx/LPC11xx/vectors.c b/os/ports/GCC/ARMCMx/LPC11xx/vectors.c index 34b220807..63b343ea2 100644 --- a/os/ports/GCC/ARMCMx/LPC11xx/vectors.c +++ b/os/ports/GCC/ARMCMx/LPC11xx/vectors.c @@ -1,5 +1,6 @@ /*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
@@ -81,7 +82,7 @@ extern void VectorBC(void); #endif
/**
- * @brief LPC11xx vectors table. + * @brief LPC11xx vectors table.
*/
#if !defined(__DOXYGEN__)
__attribute__ ((section("vectors")))
@@ -106,7 +107,7 @@ void (*_vectors[])(void) = { * @details Any undefined exception vector points to this function by default.
* This function simply stops the system into an infinite loop.
*
- * @notapi + * @notapi
*/
#if !defined(__DOXYGEN__)
__attribute__ ((naked))
diff --git a/os/ports/GCC/ARMCMx/LPC13xx/cmparams.h b/os/ports/GCC/ARMCMx/LPC13xx/cmparams.h index fb08f181f..ee49e5de9 100644 --- a/os/ports/GCC/ARMCMx/LPC13xx/cmparams.h +++ b/os/ports/GCC/ARMCMx/LPC13xx/cmparams.h @@ -1,5 +1,6 @@ /*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
diff --git a/os/ports/GCC/ARMCMx/LPC13xx/port.mk b/os/ports/GCC/ARMCMx/LPC13xx/port.mk index 3ab940082..d87487e54 100644 --- a/os/ports/GCC/ARMCMx/LPC13xx/port.mk +++ b/os/ports/GCC/ARMCMx/LPC13xx/port.mk @@ -1,10 +1,11 @@ # List of the ChibiOS/RT Cortex-M0 LPC13xx port files.
-PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC13xx/vectors.c \
+PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \
+ $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC13xx/vectors.c \
${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \
${CHIBIOS}/os/ports/GCC/ARMCMx/nvic.c
-PORTASM = ${CHIBIOS}/os/ports/GCC/ARMCMx/crt0_v7m.s
+PORTASM =
PORTINC = ${CHIBIOS}/os/ports/GCC/ARMCMx \
${CHIBIOS}/os/ports/GCC/ARMCMx/LPC13xx
diff --git a/os/ports/GCC/ARMCMx/LPC13xx/vectors.c b/os/ports/GCC/ARMCMx/LPC13xx/vectors.c index 4602f3c1b..1e27c4fc8 100644 --- a/os/ports/GCC/ARMCMx/LPC13xx/vectors.c +++ b/os/ports/GCC/ARMCMx/LPC13xx/vectors.c @@ -1,5 +1,6 @@ /*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
@@ -105,7 +106,7 @@ extern void Vector11C(void); #endif
/**
- * @brief LPC13xx vectors table. + * @brief LPC13xx vectors table.
*/
#if !defined(__DOXYGEN__)
__attribute__ ((section("vectors")))
@@ -136,7 +137,7 @@ void (*_vectors[])(void) = { * @details Any undefined exception vector points to this function by default.
* This function simply stops the system into an infinite loop.
*
- * @notapi + * @notapi
*/
#if !defined(__DOXYGEN__)
__attribute__ ((naked))
diff --git a/os/ports/GCC/ARMCMx/STM32/cmparams.h b/os/ports/GCC/ARMCMx/STM32/cmparams.h index fe9f219e5..5b630dbb8 100644 --- a/os/ports/GCC/ARMCMx/STM32/cmparams.h +++ b/os/ports/GCC/ARMCMx/STM32/cmparams.h @@ -1,5 +1,6 @@ /*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
diff --git a/os/ports/GCC/ARMCMx/STM32/port.mk b/os/ports/GCC/ARMCMx/STM32/port.mk index 80764b3d9..104b22e42 100644 --- a/os/ports/GCC/ARMCMx/STM32/port.mk +++ b/os/ports/GCC/ARMCMx/STM32/port.mk @@ -1,10 +1,11 @@ # List of the ChibiOS/RT Cortex-M3 STM32 port files.
-PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32/vectors.c \
+PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \
+ $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32/vectors.c \
${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \
${CHIBIOS}/os/ports/GCC/ARMCMx/nvic.c
-PORTASM = ${CHIBIOS}/os/ports/GCC/ARMCMx/crt0_v7m.s
+PORTASM =
PORTINC = ${CHIBIOS}/os/ports/GCC/ARMCMx \
${CHIBIOS}/os/ports/GCC/ARMCMx/STM32
diff --git a/os/ports/GCC/ARMCMx/STM32/vectors.c b/os/ports/GCC/ARMCMx/STM32/vectors.c index 1ecbae7e4..f12e2e867 100644 --- a/os/ports/GCC/ARMCMx/STM32/vectors.c +++ b/os/ports/GCC/ARMCMx/STM32/vectors.c @@ -1,5 +1,6 @@ /*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
@@ -96,12 +97,13 @@ extern void VectorDC(void); extern void VectorE0(void);
extern void VectorE4(void);
extern void VectorE8(void);
-#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) || defined(STM32F10X_CL)
+#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) || \
+ defined(STM32F10X_XL) || defined(STM32F10X_CL)
extern void VectorEC(void);
extern void VectorF0(void);
extern void VectorF4(void);
#endif
-#if defined(STM32F10X_HD) || defined(STM32F10X_CL)
+#if defined(STM32F10X_HD) || defined(STM32F10X_XL) || defined(STM32F10X_CL)
extern void VectorF8(void);
extern void VectorFC(void);
extern void Vector100(void);
@@ -130,7 +132,7 @@ extern void Vector14C(void); #endif
/**
- * @brief STM32 vectors table. + * @brief STM32 vectors table.
*/
#if !defined(__DOXYGEN__)
__attribute__ ((section("vectors")))
@@ -172,7 +174,7 @@ void (*_vectors[])(void) = { * @details Any undefined exception vector points to this function by default.
* This function simply stops the system into an infinite loop.
*
- * @notapi + * @notapi
*/
#if !defined(__DOXYGEN__)
__attribute__ ((naked))
diff --git a/os/ports/GCC/ARMCMx/chcore.c b/os/ports/GCC/ARMCMx/chcore.c index 4bb0436cd..5b210b8fa 100644 --- a/os/ports/GCC/ARMCMx/chcore.c +++ b/os/ports/GCC/ARMCMx/chcore.c @@ -1,5 +1,6 @@ /*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
diff --git a/os/ports/GCC/ARMCMx/chcore.h b/os/ports/GCC/ARMCMx/chcore.h index 3fe046a95..5d47a6699 100644 --- a/os/ports/GCC/ARMCMx/chcore.h +++ b/os/ports/GCC/ARMCMx/chcore.h @@ -1,5 +1,6 @@ /*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
@@ -28,16 +29,22 @@ #ifndef _CHCORE_H_
#define _CHCORE_H_
-#include "nvic.h"
-
/*===========================================================================*/
-/* Port constants. */
+/* Port constants (common). */
/*===========================================================================*/
-#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */
-#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */
-#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */
-#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */
+/* Added to make the header stand-alone when included from asm.*/
+#ifndef FALSE
+#define FALSE 0
+#endif
+#ifndef TRUE
+#define TRUE (!FALSE)
+#endif
+
+#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */
+#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */
+#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */
+#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */
/* Inclusion of the Cortex-Mx implementation specific parameters.*/
#include "cmparams.h"
@@ -50,36 +57,26 @@ #error "unknown or unsupported Cortex-M model"
#endif
-/*===========================================================================*/
-/* Port statically derived parameters. */
-/*===========================================================================*/
-
/**
* @brief Total priority levels.
*/
-#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS)
+#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS)
/**
* @brief Minimum priority level.
* @details This minimum priority level is calculated from the number of
* priority bits supported by the specific Cortex-Mx implementation.
*/
-#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1)
+#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1)
/**
* @brief Maximum priority level.
* @details The maximum allowed priority level is always zero.
*/
-#define CORTEX_MAXIMUM_PRIORITY 0
-
-/**
- * @brief Disabled value for BASEPRI register.
- * @note ARMv7-M architecture only. - */
-#define CORTEX_BASEPRI_DISABLED 0
+#define CORTEX_MAXIMUM_PRIORITY 0
/*===========================================================================*/
-/* Port macros. */
+/* Port macros (common). */
/*===========================================================================*/
/**
@@ -95,75 +92,56 @@ ((n) << (8 - CORTEX_PRIORITY_BITS))
/*===========================================================================*/
-/* Port configurable parameters. */
+/* Port configurable parameters (common). */
/*===========================================================================*/
/**
- * @brief Enables the use of the WFI instruction in the idle thread loop.
+ * @brief Stack size for the system idle thread.
+ * @details This size depends on the idle thread implementation, usually
+ * the idle thread should take no more space than those reserved
+ * by @p PORT_INT_REQUIRED_STACK.
+ * @note In this port it is set to 16 because the idle thread does have
+ * a stack frame when compiling without optimizations. You may
+ * reduce this value to zero when compiling with optimizations.
*/
-#ifndef CORTEX_ENABLE_WFI_IDLE
-#define CORTEX_ENABLE_WFI_IDLE FALSE
+#ifndef PORT_IDLE_THREAD_STACK_SIZE
+#define PORT_IDLE_THREAD_STACK_SIZE 16
#endif
/**
- * @brief SYSTICK handler priority.
- * @note The default SYSTICK handler priority is calculated as the priority
- * level in the middle of the numeric priorities range.
+ * @brief Per-thread stack overhead for interrupts servicing.
+ * @details This constant is used in the calculation of the correct working
+ * area size.
+ * This value can be zero on those architecture where there is a
+ * separate interrupt stack and the stack space between @p intctx and
+ * @p extctx is known to be zero.
+ * @note In this port it is conservatively set to 16 because the function
+ * @p chSchDoRescheduleI() can have a stack frame, expecially with
+ * compiler optimizations disabled.
*/
-#ifndef CORTEX_PRIORITY_SYSTICK
-#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1)
-#else
-/* If it is externally redefined then better perform a validity check on it.*/
-#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK)
-#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK"
-#endif
+#ifndef PORT_INT_REQUIRED_STACK
+#define PORT_INT_REQUIRED_STACK 16
#endif
/**
- * @brief SVCALL handler priority.
- * @note The default SVCALL handler priority is calculated as
- * @p CORTEX_MAXIMUM_PRIORITY+1, in the ARMv7-M port this reserves
- * the @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts
- * priority level.
- * @note The SVCALL vector is only used in the ARMv7-M port, it is available
- * to user in the ARMv6-M port.
+ * @brief Enables the use of the WFI instruction in the idle thread loop.
*/
-#ifndef CORTEX_PRIORITY_SVCALL
-#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1)
-#else
-/* If it is externally redefined then better perform a validity check on it.*/
-#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL)
-#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL"
-#endif
+#ifndef CORTEX_ENABLE_WFI_IDLE
+#define CORTEX_ENABLE_WFI_IDLE FALSE
#endif
/**
- * @brief PENDSV handler priority.
- * @note The default PENDSV handler priority is set at the
- * @p CORTEX_MINIMUM_PRIORITY priority level.
- * @note The PENDSV vector is only used in the ARMv7-M legacy port, it is
- * available to user in the ARMv6-M and ARMv7-M ports.
- * @note In the ARMv7-M legacy port this value should be not changed from
- * the minimum priority level.
+ * @brief SYSTICK handler priority.
+ * @note The default SYSTICK handler priority is calculated as the priority
+ * level in the middle of the numeric priorities range.
*/
-#ifndef CORTEX_PRIORITY_PENDSV
-#define CORTEX_PRIORITY_PENDSV CORTEX_MINIMUM_PRIORITY
+#ifndef CORTEX_PRIORITY_SYSTICK
+#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1)
#else
/* If it is externally redefined then better perform a validity check on it.*/
-#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_PENDSV)
-#error "invalid priority level specified for CORTEX_PRIORITY_PENDSV"
-#endif
+#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK)
+#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK"
#endif
-
-/**
- * @brief BASEPRI level within kernel lock.
- * @note This value must not mask the SVCALL priority level or the
- * kernel would hard fault.
- * @note ARMv7-M architecture only.
- */
-#ifndef CORTEX_BASEPRI_KERNEL
-#define CORTEX_BASEPRI_KERNEL \
- CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL+1)
#endif
/**
@@ -171,14 +149,18 @@ * @note The default value is 64 in order to comply with EABI, reducing
* the value to 32 can save some RAM space if you don't care about
* binary compatibility with EABI compiled libraries.
- * @note Allowed values are 32 or 64. + * @note Allowed values are 32 or 64.
*/
#ifndef CORTEX_STACK_ALIGNMENT
-#define CORTEX_STACK_ALIGNMENT 64
+#define CORTEX_STACK_ALIGNMENT 64
#endif
/*===========================================================================*/
-/* Port exported info. */
+/* Port derived parameters (common). */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Port exported info (common). */
/*===========================================================================*/
/**
@@ -186,62 +168,26 @@ */
#define CH_ARCHITECTURE_ARM
-#if defined(__DOXYGEN__)
-/**
- * @brief Macro defining the specific ARM architecture.
- * @note This macro is for documentation only, the real name changes
- * depending on the selected architecture, the possible names are:
- * - CH_ARCHITECTURE_ARM_v6M.
- * - CH_ARCHITECTURE_ARM_v7M.
- * .
- */
-#define CH_ARCHITECTURE_ARM_vxm
-
/**
- * @brief Name of the implemented architecture.
- * @note The value is for documentation only, the real value changes
- * depending on the selected architecture, the possible values are:
- * - "ARMv6-M".
- * - "ARMv7-M".
- * - "ARMv7-ME".
- * .
+ * @brief Name of the compiler supported by this port.
*/
-#define CH_ARCHITECTURE_NAME "ARMvx-M"
-
-/**
- * @brief Name of the architecture variant (optional).
- * @note The value is for documentation only, the real value changes
- * depending on the selected architecture, the possible values are:
- * - "Cortex-M0"
- * - "Cortex-M1"
- * - "Cortex-M3"
- * - "Cortex-M4"
- * .
- */
-#define CH_CORE_VARIANT_NAME "Cortex-Mx"
-
-#elif CORTEX_MODEL == CORTEX_M4
-#define CH_ARCHITECTURE_ARM_v7M
-#define CH_ARCHITECTURE_NAME "ARMv7-ME"
-#define CH_CORE_VARIANT_NAME "Cortex-M4"
-#elif CORTEX_MODEL == CORTEX_M3
-#define CH_ARCHITECTURE_ARM_v7M
-#define CH_ARCHITECTURE_NAME "ARMv7-M"
-#define CH_CORE_VARIANT_NAME "Cortex-M3"
-#elif CORTEX_MODEL == CORTEX_M1
-#define CH_ARCHITECTURE_ARM_v6M
-#define CH_ARCHITECTURE_NAME "ARMv6-M"
-#define CH_CORE_VARIANT_NAME "Cortex-M1"
-#elif CORTEX_MODEL == CORTEX_M0
-#define CH_ARCHITECTURE_ARM_v6M
-#define CH_ARCHITECTURE_NAME "ARMv6-M"
-#define CH_CORE_VARIANT_NAME "Cortex-M0"
-#endif
+#define CH_COMPILER_NAME "GCC "__VERSION__
/*===========================================================================*/
/* Port implementation part (common). */
/*===========================================================================*/
+/* Includes the sub-architecture-specific part.*/
+#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1)
+#include "chcore_v6m.h"
+#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4)
+#include "chcore_v7m.h"
+#endif
+
+#if !defined(_FROM_ASM_)
+
+#include "nvic.h"
+
/**
* @brief Stack and memory alignment enforcement.
*/
@@ -258,11 +204,6 @@ typedef uint32_t stkalign_t __attribute__ ((aligned (4))); #error "invalid stack alignment selected"
#endif
-/**
- * @brief Generic ARM register.
- */
-typedef void *regarm_t;
-
#if defined(__DOXYGEN__)
/**
* @brief Interrupt saved context.
@@ -294,6 +235,20 @@ struct context { };
/**
+ * @brief Platform dependent part of the @p chThdCreateI() API.
+ * @details This code usually setup the context switching frame represented
+ * by an @p intctx structure.
+ */
+#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
+ tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \
+ wsize - \
+ sizeof(struct intctx)); \
+ tp->p_ctx.r13->r4 = pf; \
+ tp->p_ctx.r13->r5 = arg; \
+ tp->p_ctx.r13->lr = _port_thread_start; \
+}
+
+/**
* @brief Enforces a correct alignment for a stack area size value.
*/
#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
@@ -301,10 +256,10 @@ struct context { /**
* @brief Computes the thread working area global size.
*/
-#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \
- sizeof(struct intctx) + \
- sizeof(struct extctx) + \
- (n) + (INT_REQUIRED_STACK))
+#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \
+ sizeof(struct intctx) + \
+ sizeof(struct extctx) + \
+ (n) + (PORT_INT_REQUIRED_STACK))
/**
* @brief Static working area allocation.
@@ -313,12 +268,7 @@ struct context { */
#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
-/* Includes the architecture-specific implementation part.*/
-#if defined(CH_ARCHITECTURE_ARM_v6M)
-#include "chcore_v6m.h"
-#elif defined(CH_ARCHITECTURE_ARM_v7M)
-#include "chcore_v7m.h"
-#endif
+#endif /* _FROM_ASM_ */
#endif /* _CHCORE_H_ */
diff --git a/os/ports/GCC/ARMCMx/chcore_v6m.c b/os/ports/GCC/ARMCMx/chcore_v6m.c index dbff1d07c..18082e86f 100644 --- a/os/ports/GCC/ARMCMx/chcore_v6m.c +++ b/os/ports/GCC/ARMCMx/chcore_v6m.c @@ -1,5 +1,6 @@ /*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
@@ -28,16 +29,6 @@ #include "ch.h"
/**
- * @brief PC register temporary storage.
- */
-regarm_t _port_saved_pc;
-
-/**
- * @brief IRQ nesting counter. - */
-unsigned _port_irq_nesting;
-
-/**
* @brief System Timer vector.
* @details This interrupt is used as system tick.
* @note The timer must be initialized in the startup code.
@@ -53,39 +44,63 @@ CH_IRQ_HANDLER(SysTickVector) { CH_IRQ_EPILOGUE();
}
+#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
+/**
+ * @brief NMI vector.
+ * @details The NMI vector is used for exception mode re-entering after a
+ * context switch.
+ */
+void NMIVector(void) {
+ register struct extctx *ctxp;
+
+ /* Discarding the current exception context and positioning the stack to
+ point to the real one.*/
+ asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory");
+ ctxp++;
+ asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory");
+ port_unlock_from_isr();
+}
+#endif /* !CORTEX_ALTERNATE_SWITCH */
+
+#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
+/**
+ * @brief PendSV vector.
+ * @details The PendSV vector is used for exception mode re-entering after a
+ * context switch.
+ */
+void PendSVVector(void) {
+ register struct extctx *ctxp;
+
+ /* Discarding the current exception context and positioning the stack to
+ point to the real one.*/
+ asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory");
+ ctxp++;
+ asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory");
+}
+#endif /* CORTEX_ALTERNATE_SWITCH */
+
/**
* @brief Post-IRQ switch code.
- * @details On entry the stack and the registers are restored by the exception
- * return, the PC value is stored in @p _port_saved_pc, the interrupts
- * are disabled.
+ * @details The switch is performed in thread context then an NMI exception
+ * is enforced in order to return to the exact point before the
+ * preemption.
*/
#if !defined(__DOXYGEN__)
__attribute__((naked))
#endif
void _port_switch_from_isr(void) {
- /* Note, saves r4 to make space for the PC.*/
- asm volatile ("push {r0, r1, r2, r3, r4} \n\t"
- "mrs r0, APSR \n\t"
- "mov r1, r12 \n\t"
- "push {r0, r1, lr} \n\t"
- "ldr r0, =_port_saved_pc \n\t"
- "ldr r0, [r0] \n\t"
- "add r0, r0, #1 \n\t"
- "str r0, [sp, #28]" : : : "memory");
chSchDoRescheduleI();
-
- /* Note, the last registers are restored alone after re-enabling the
- interrupts in order to minimize the (very remote and unlikely)
- possibility that the stack is filled by continuous and saturating
- interrupts that would not allow that last words to be pulled out of
- the stack.*/
- asm volatile ("pop {r0, r1, r2} \n\t"
- "mov r12, r1 \n\t"
- "msr APSR, r0 \n\t"
- "mov lr, r2 \n\t"
- "cpsie i \n\t"
- "pop {r0, r1, r2, r3, pc}" : : : "memory");
+#if CORTEX_ALTERNATE_SWITCH
+ SCB_ICSR = ICSR_PENDSVSET;
+ port_unlock();
+#else
+ SCB_ICSR = ICSR_NMIPENDSET;
+#endif
+ /* The following loop should never be executed, the exception will kick in
+ immediately.*/
+ while (TRUE)
+ ;
}
#define PUSH_CONTEXT(sp) { \
@@ -119,16 +134,9 @@ void _port_switch_from_isr(void) { #if !defined(__DOXYGEN__)
__attribute__((naked))
#endif
-void port_switch(Thread *ntp, Thread *otp) {
+void _port_switch(Thread *ntp, Thread *otp) {
register struct intctx *r13 asm ("r13");
- /* Stack overflow check, if enabled.*/
-#if CH_DBG_ENABLE_STACK_CHECK
- if ((void *)(r13 - 1) < (void *)(otp + 1))
- asm volatile ("movs r0, #0 \n\t"
- "b chDbgPanic");
-#endif /* CH_DBG_ENABLE_STACK_CHECK */
-
PUSH_CONTEXT(r13);
otp->p_ctx.r13 = r13;
@@ -138,6 +146,33 @@ void port_switch(Thread *ntp, Thread *otp) { }
/**
+ * @brief IRQ epilogue code.
+ *
+ * @param[in] lr value of the @p LR register on ISR entry
+ */
+void _port_irq_epilogue(regarm_t lr) {
+
+ if (lr != (regarm_t)0xFFFFFFF1) {
+ port_lock_from_isr();
+ if (chSchIsRescRequiredExI()) {
+ register struct extctx *ctxp;
+
+ /* Adding an artificial exception return context, there is no need to
+ populate it fully.*/
+ asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory");
+ ctxp--;
+ asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory");
+ ctxp->pc = _port_switch_from_isr;
+ ctxp->xpsr = (regarm_t)0x01000000;
+ /* Note, returning without unlocking is intentional, this is done in
+ order to keep the rest of the context switching atomic.*/
+ return;
+ }
+ port_unlock_from_isr();
+ }
+}
+
+/**
* @brief Start a thread by invoking its work function.
* @details If the work function returns @p chThdExit() is automatically
* invoked.
diff --git a/os/ports/GCC/ARMCMx/chcore_v6m.h b/os/ports/GCC/ARMCMx/chcore_v6m.h index 1bd2f777e..2141ee468 100644 --- a/os/ports/GCC/ARMCMx/chcore_v6m.h +++ b/os/ports/GCC/ARMCMx/chcore_v6m.h @@ -1,5 +1,6 @@ /*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
@@ -29,33 +30,87 @@ #define _CHCORE_V6M_H_
/*===========================================================================*/
+/* Port constants. */
+/*===========================================================================*/
+
+/**
+ * @brief PendSV priority level.
+ * @note This priority is enforced to be equal to @p 0,
+ * this handler always have the highest priority that cannot preempt
+ * the kernel.
+ */
+#define CORTEX_PRIORITY_PENDSV 0
+
+/*===========================================================================*/
+/* Port configurable parameters. */
+/*===========================================================================*/
+
+/**
+ * @brief Alternate preemption method.
+ * @details Activating this option will make the Kernel use the PendSV
+ * handler for preemption instead of the NMI handler.
+ */
+#ifndef CORTEX_ALTERNATE_SWITCH
+#define CORTEX_ALTERNATE_SWITCH FALSE
+#endif
+
+/*===========================================================================*/
+/* Port derived parameters. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Port exported info. */
+/*===========================================================================*/
+
+/**
+ * @brief Macro defining the specific ARM architecture.
+ */
+#define CH_ARCHITECTURE_ARM_v6M
+
+/**
+ * @brief Name of the implemented architecture.
+ */
+#define CH_ARCHITECTURE_NAME "ARMv6-M"
+
+/**
+ * @brief Name of the architecture variant.
+ */
+#if (CORTEX_MODEL == CORTEX_M0) || defined(__DOXYGEN__)
+#define CH_CORE_VARIANT_NAME "Cortex-M0"
+#elif (CORTEX_MODEL == CORTEX_M1)
+#define CH_CORE_VARIANT_NAME "Cortex-M1"
+#endif
+
+/**
+ * @brief Port-specific information string.
+ */
+#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
+#define CH_PORT_INFO "Preemption through NMI"
+#else
+#define CH_PORT_INFO "Preemption through PendSV"
+#endif
+
+/*===========================================================================*/
/* Port implementation part. */
/*===========================================================================*/
+#if !defined(_FROM_ASM_)
+
/**
- * @brief Cortex-Mx exception context.
+ * @brief Generic ARM register.
*/
-struct cmxctx {
- regarm_t r0;
- regarm_t r1;
- regarm_t r2;
- regarm_t r3;
- regarm_t r12;
- regarm_t lr_thd;
- regarm_t pc;
- regarm_t xpsr;
-};
+typedef void *regarm_t;
#if !defined(__DOXYGEN__)
struct extctx {
- regarm_t xpsr;
- regarm_t r12;
- regarm_t lr;
regarm_t r0;
regarm_t r1;
regarm_t r2;
regarm_t r3;
+ regarm_t r12;
+ regarm_t lr_thd;
regarm_t pc;
+ regarm_t xpsr;
};
struct intctx {
@@ -72,75 +127,20 @@ struct intctx { #endif
/**
- * @brief Platform dependent part of the @p chThdCreateI() API.
- * @details This code usually setup the context switching frame represented
- * by an @p intctx structure.
- */
-#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
- tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \
- wsize - \
- sizeof(struct intctx)); \
- tp->p_ctx.r13->r4 = pf; \
- tp->p_ctx.r13->r5 = arg; \
- tp->p_ctx.r13->lr = _port_thread_start; \
-}
-
-/**
- * @brief Stack size for the system idle thread.
- * @details This size depends on the idle thread implementation, usually
- * the idle thread should take no more space than those reserved
- * by @p INT_REQUIRED_STACK.
- * @note In this port it is set to 8 because the idle thread does have
- * a stack frame when compiling without optimizations. You may
- * reduce this value to zero when compiling with optimizations.
- */
-#ifndef IDLE_THREAD_STACK_SIZE
-#define IDLE_THREAD_STACK_SIZE 8
-#endif
-
-/**
- * @brief Per-thread stack overhead for interrupts servicing.
- * @details This constant is used in the calculation of the correct working
- * area size.
- * This value can be zero on those architecture where there is a
- * separate interrupt stack and the stack space between @p intctx and
- * @p extctx is known to be zero.
- * @note In this port it is conservatively set to 16 because the function
- * @p chSchDoRescheduleI() can have a stack frame, expecially with
- * compiler optimizations disabled.
- */
-#ifndef INT_REQUIRED_STACK
-#define INT_REQUIRED_STACK 16
-#endif
-
-/**
* @brief IRQ prologue code.
* @details This macro must be inserted at the start of all IRQ handlers
* enabled to invoke system APIs.
*/
-#define PORT_IRQ_PROLOGUE() { \
- port_lock_from_isr(); \
- _port_irq_nesting++; \
- port_unlock_from_isr(); \
-}
+#define PORT_IRQ_PROLOGUE() \
+ regarm_t _saved_lr; \
+ asm volatile ("mov %0, lr" : "=r" (_saved_lr) : : "memory")
/**
* @brief IRQ epilogue code.
* @details This macro must be inserted at the end of all IRQ handlers
* enabled to invoke system APIs.
*/
-#define PORT_IRQ_EPILOGUE() { \
- port_lock_from_isr(); \
- if ((--_port_irq_nesting == 0) && chSchIsRescRequiredExI()) { \
- register struct cmxctx *ctxp; \
- \
- asm volatile ("mrs %0, PSP" : "=r" (ctxp) : ); \
- _port_saved_pc = ctxp->pc; \
- ctxp->pc = _port_switch_from_isr; \
- return; \
- } \
- port_unlock_from_isr(); \
-}
+#define PORT_IRQ_EPILOGUE() _port_irq_epilogue(_saved_lr)
/**
* @brief IRQ handler function declaration.
@@ -160,8 +160,9 @@ struct intctx { * @brief Port-related initialization code.
*/
#define port_init() { \
- _port_irq_nesting = 0; \
SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \
+ NVICSetSystemHandlerPriority(HANDLER_PENDSV, \
+ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \
NVICSetSystemHandlerPriority(HANDLER_SYSTICK, \
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \
}
@@ -227,22 +228,41 @@ struct intctx { #define port_wait_for_interrupt()
#endif
-#if !defined(__DOXYGEN__)
-extern regarm_t _port_saved_pc;
-extern unsigned _port_irq_nesting;
+/**
+ * @brief Performs a context switch between two threads.
+ * @details This is the most critical code in any port, this function
+ * is responsible for the context switch between 2 threads.
+ * @note The implementation of this code affects <b>directly</b> the context
+ * switch performance so optimize here as much as you can.
+ *
+ * @param[in] ntp the thread to be switched in
+ * @param[in] otp the thread to be switched out
+ */
+#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
+#define port_switch(ntp, otp) _port_switch(ntp, otp)
+#else
+#define port_switch(ntp, otp) { \
+ register struct intctx *r13 asm ("r13"); \
+ if ((void *)(r13 - 1) < (void *)(otp + 1)) \
+ chDbgPanic("stack overflow"); \
+ _port_switch(ntp, otp); \
+}
#endif
#ifdef __cplusplus
extern "C" {
#endif
void port_halt(void);
- void port_switch(Thread *ntp, Thread *otp);
+ void _port_switch(Thread *ntp, Thread *otp);
+ void _port_irq_epilogue(regarm_t lr);
void _port_switch_from_isr(void);
void _port_thread_start(void);
#ifdef __cplusplus
}
#endif
+#endif /* _FROM_ASM_ */
+
#endif /* _CHCORE_V6M_H_ */
/** @} */
diff --git a/os/ports/GCC/ARMCMx/chcore_v7m.c b/os/ports/GCC/ARMCMx/chcore_v7m.c index 6e3732a8d..2cf5cfe6b 100644 --- a/os/ports/GCC/ARMCMx/chcore_v7m.c +++ b/os/ports/GCC/ARMCMx/chcore_v7m.c @@ -1,5 +1,6 @@ /*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
@@ -27,9 +28,8 @@ #include "ch.h"
-#if !defined(CH_CURRP_REGISTER_CACHE) || defined(__DOXXYGEN__)
/**
- * @brief Internal context stacking. + * @brief Internal context stacking.
*/
#define PUSH_CONTEXT() { \
asm volatile ("push {r4, r5, r6, r7, r8, r9, r10, r11, lr}" \
@@ -43,17 +43,6 @@ asm volatile ("pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}" \
: : : "memory"); \
}
-#else /* defined(CH_CURRP_REGISTER_CACHE) */
-#define PUSH_CONTEXT() { \
- asm volatile ("push {r4, r5, r6, r8, r9, r10, r11, lr}" \
- : : : "memory"); \
-}
-
-#define POP_CONTEXT() { \
- asm volatile ("pop {r4, r5, r6, r8, r9, r10, r11, pc}" \
- : : : "memory"); \
-}
-#endif /* defined(CH_CURRP_REGISTER_CACHE) */
#if !CH_OPTIMIZE_SPEED
void _port_lock(void) {
@@ -83,10 +72,12 @@ CH_IRQ_HANDLER(SysTickVector) { CH_IRQ_EPILOGUE();
}
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
/**
* @brief SVC vector.
* @details The SVC vector is used for exception mode re-entering after a
* context switch.
+ * @note The PendSV vector is only used in advanced kernel mode.
*/
void SVCallVector(void) {
register struct extctx *ctxp;
@@ -98,9 +89,28 @@ void SVCallVector(void) { asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory");
port_unlock_from_isr();
}
+#endif /* !CORTEX_SIMPLIFIED_PRIORITY */
+#if CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
/**
- * @brief Reschedule verification and setup after an IRQ. + * @brief PendSV vector.
+ * @details The PendSV vector is used for exception mode re-entering after a
+ * context switch.
+ * @note The PendSV vector is only used in compact kernel mode.
+ */
+void PendSVVector(void) {
+ register struct extctx *ctxp;
+
+ /* Discarding the current exception context and positioning the stack to
+ point to the real one.*/
+ asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory");
+ ctxp++;
+ asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory");
+}
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
+
+/**
+ * @brief Reschedule verification and setup after an IRQ.
*/
void _port_irq_epilogue(void) {
@@ -133,7 +143,14 @@ __attribute__((naked)) void _port_switch_from_isr(void) {
chSchDoRescheduleI();
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
asm volatile ("svc #0");
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+ SCB_ICSR = ICSR_PENDSVSET;
+ port_unlock();
+ while (TRUE)
+ ;
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
}
/**
diff --git a/os/ports/GCC/ARMCMx/chcore_v7m.h b/os/ports/GCC/ARMCMx/chcore_v7m.h index 2a4838669..297bd4e54 100644 --- a/os/ports/GCC/ARMCMx/chcore_v7m.h +++ b/os/ports/GCC/ARMCMx/chcore_v7m.h @@ -1,5 +1,6 @@ /*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
@@ -29,9 +30,111 @@ #define _CHCORE_V7M_H_
/*===========================================================================*/
+/* Port constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Disabled value for BASEPRI register.
+ */
+#define CORTEX_BASEPRI_DISABLED 0
+
+/*===========================================================================*/
+/* Port configurable parameters. */
+/*===========================================================================*/
+
+/**
+ * @brief Simplified priority handling flag.
+ * @details Activating this option will make the Kernel work in compact mode.
+ */
+#ifndef CORTEX_SIMPLIFIED_PRIORITY
+#define CORTEX_SIMPLIFIED_PRIORITY FALSE
+#endif
+
+/**
+ * @brief SVCALL handler priority.
+ * @note The default SVCALL handler priority is defaulted to
+ * @p CORTEX_MAXIMUM_PRIORITY+1, this reserves the
+ * @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts
+ * priority level.
+ */
+#ifndef CORTEX_PRIORITY_SVCALL
+#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1)
+#else
+/* If it is externally redefined then better perform a validity check on it.*/
+#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL)
+#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL"
+#endif
+#endif
+
+/*===========================================================================*/
+/* Port derived parameters. */
+/*===========================================================================*/
+
+/**
+ * @brief BASEPRI level within kernel lock.
+ * @note In compact kernel mode this constant value is enforced to zero.
+ */
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
+#define CORTEX_BASEPRI_KERNEL \
+ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL+1)
+#else
+#define CORTEX_BASEPRI_KERNEL 0
+#endif
+
+/**
+ * @brief PendSV priority level.
+ * @note This priority is enforced to be equal to @p CORTEX_BASEPRI_KERNEL,
+ * this handler always have the highest priority that cannot preempt
+ * the kernel.
+ */
+#define CORTEX_PRIORITY_PENDSV CORTEX_BASEPRI_KERNEL
+
+/*===========================================================================*/
+/* Port exported info. */
+/*===========================================================================*/
+
+#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)
+/**
+ * @brief Macro defining the specific ARM architecture.
+ */
+#define CH_ARCHITECTURE_ARM_v7M
+
+/**
+ * @brief Name of the implemented architecture.
+ */
+#define CH_ARCHITECTURE_NAME "ARMv7-M"
+
+/**
+ * @brief Name of the architecture variant.
+ */
+#define CH_CORE_VARIANT_NAME "Cortex-M3"
+
+#elif (CORTEX_MODEL == CORTEX_M4)
+#define CH_ARCHITECTURE_ARM_v7ME
+#define CH_ARCHITECTURE_NAME "ARMv7-ME"
+#define CH_CORE_VARIANT_NAME "Cortex-M4"
+#endif
+
+/**
+ * @brief Port-specific information string.
+ */
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
+#define CH_PORT_INFO "Advanced kernel mode"
+#else
+#define CH_PORT_INFO "Compact kernel mode"
+#endif
+
+/*===========================================================================*/
/* Port implementation part. */
/*===========================================================================*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief Generic ARM register.
+ */
+typedef void *regarm_t;
+
#if !defined(__DOXYGEN__)
struct extctx {
regarm_t r0;
@@ -48,9 +151,7 @@ struct intctx { regarm_t r4;
regarm_t r5;
regarm_t r6;
-#ifndef CH_CURRP_REGISTER_CACHE
regarm_t r7;
-#endif
regarm_t r8;
regarm_t r9;
regarm_t r10;
@@ -60,48 +161,6 @@ struct intctx { #endif
/**
- * @brief Platform dependent part of the @p chThdCreateI() API.
- * @details This code usually setup the context switching frame represented
- * by an @p intctx structure.
- */
-#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
- tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \
- wsize - \
- sizeof(struct intctx)); \
- tp->p_ctx.r13->r4 = pf; \
- tp->p_ctx.r13->r5 = arg; \
- tp->p_ctx.r13->lr = _port_thread_start; \
-}
-
-/**
- * @brief Stack size for the system idle thread.
- * @details This size depends on the idle thread implementation, usually
- * the idle thread should take no more space than those reserved
- * by @p INT_REQUIRED_STACK.
- * @note In this port it is set to 8 because the idle thread does have
- * a stack frame when compiling without optimizations. You may
- * reduce this value to zero when compiling with optimizations.
- */
-#ifndef IDLE_THREAD_STACK_SIZE
-#define IDLE_THREAD_STACK_SIZE 8
-#endif
-
-/**
- * @brief Per-thread stack overhead for interrupts servicing.
- * @details This constant is used in the calculation of the correct working
- * area size.
- * This value can be zero on those architecture where there is a
- * separate interrupt stack and the stack space between @p intctx and
- * @p extctx is known to be zero.
- * @note In this port it is conservatively set to 16 because the function
- * @p chSchDoRescheduleI() can have a stack frame, expecially with
- * compiler optimizations disabled.
- */
-#ifndef INT_REQUIRED_STACK
-#define INT_REQUIRED_STACK 16
-#endif
-
-/**
* @brief IRQ prologue code.
* @details This macro must be inserted at the start of all IRQ handlers
* enabled to invoke system APIs.
@@ -136,6 +195,8 @@ struct intctx { SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \
NVICSetSystemHandlerPriority(HANDLER_SVCALL, \
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL)); \
+ NVICSetSystemHandlerPriority(HANDLER_PENDSV, \
+ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \
NVICSetSystemHandlerPriority(HANDLER_SYSTICK, \
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \
}
@@ -146,16 +207,20 @@ struct intctx { * more actions.
* @note In this port this it raises the base priority to kernel level.
*/
-#if CH_OPTIMIZE_SPEED
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
+#if CH_OPTIMIZE_SPEED || defined(__DOXYGEN__)
#define port_lock() { \
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \
asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory"); \
}
-#else
+#else /* !CH_OPTIMIZE_SPEED */
#define port_lock() { \
asm volatile ("bl _port_lock" : : : "r3", "lr", "memory"); \
}
-#endif
+#endif /* !CH_OPTIMIZE_SPEED */
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+#define port_lock() asm volatile ("cpsid i" : : : "memory")
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
/**
* @brief Kernel-unlock action.
@@ -163,16 +228,20 @@ struct intctx { * more actions.
* @note In this port this it lowers the base priority to user level.
*/
-#if CH_OPTIMIZE_SPEED
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
+#if CH_OPTIMIZE_SPEED || defined(__DOXYGEN__)
#define port_unlock() { \
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \
asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory"); \
}
-#else
+#else /* !CH_OPTIMIZE_SPEED */
#define port_unlock() { \
asm volatile ("bl _port_unlock" : : : "r3", "lr", "memory"); \
}
-#endif
+#endif /* !CH_OPTIMIZE_SPEED */
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+#define port_unlock() asm volatile ("cpsie i" : : : "memory")
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
/**
* @brief Kernel-lock action from an interrupt handler.
@@ -205,21 +274,29 @@ struct intctx { * @note Interrupt sources above kernel level remains enabled.
* @note In this port it raises/lowers the base priority to kernel level.
*/
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
#define port_suspend() { \
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \
asm volatile ("msr BASEPRI, %0 \n\t" \
"cpsie i" : : "r" (tmp) : "memory"); \
}
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+#define port_suspend() asm volatile ("cpsid i" : : : "memory")
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
/**
* @brief Enables all the interrupt sources.
* @note In this port it lowers the base priority to user level.
*/
+#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
#define port_enable() { \
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \
asm volatile ("msr BASEPRI, %0 \n\t" \
"cpsie i" : : "r" (tmp) : "memory"); \
}
+#else /* CORTEX_SIMPLIFIED_PRIORITY */
+#define port_enable() asm volatile ("cpsie i" : : : "memory")
+#endif /* CORTEX_SIMPLIFIED_PRIORITY */
/**
* @brief Enters an architecture-dependent IRQ-waiting mode.
@@ -253,6 +330,8 @@ extern "C" { }
#endif
+#endif /* _FROM_ASM_ */
+
#endif /* _CHCORE_V7M_H_ */
/** @} */
diff --git a/os/ports/GCC/ARMCMx/chtypes.h b/os/ports/GCC/ARMCMx/chtypes.h index f4bf93c1c..938a736d0 100644 --- a/os/ports/GCC/ARMCMx/chtypes.h +++ b/os/ports/GCC/ARMCMx/chtypes.h @@ -1,5 +1,6 @@ /*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
diff --git a/os/ports/GCC/ARMCMx/crt0.c b/os/ports/GCC/ARMCMx/crt0.c new file mode 100644 index 000000000..0bb88dd83 --- /dev/null +++ b/os/ports/GCC/ARMCMx/crt0.c @@ -0,0 +1,274 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file ARMCMx/crt0.c
+ * @brief Generic ARMvx-M (Cortex-M0/M1/M3/M4) startup file for ChibiOS/RT.
+ *
+ * @addtogroup ARMCMx_STARTUP
+ * @{
+ */
+
+#include "chtypes.h"
+
+#define FALSE 0
+#define TRUE (!FALSE)
+
+typedef void (*funcp_t)(void);
+typedef funcp_t * funcpp_t;
+
+/**
+ * @brief Control special register initialization value.
+ * @details The system is setup to run in privileged mode using the PSP
+ * stack (dual stack mode).
+ */
+#if !defined(CRT0_CONTROL_INIT) || defined(__DOXYGEN__)
+#define CRT0_CONTROL_INIT 0x00000002
+#endif
+
+/**
+ * @brief DATA segment initialization switch.
+ */
+#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__)
+#define CRT0_INIT_DATA TRUE
+#endif
+
+/**
+ * @brief BSS segment initialization switch.
+ */
+#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__)
+#define CRT0_INIT_BSS TRUE
+#endif
+
+/**
+ * @brief Constructors invocation switch.
+ */
+#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__)
+#define CRT0_CALL_CONSTRUCTORS TRUE
+#endif
+
+/**
+ * @brief Destructors invocation switch.
+ */
+#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__)
+#define CRT0_CALL_DESTRUCTORS TRUE
+#endif
+
+#define SYMVAL(sym) (uint32_t)(((uint8_t *)&(sym)) - ((uint8_t *)0))
+
+/**
+ * @brief Ram end.
+ * @details This symbol must be exported by the linker script and represents
+ * the location after the last RAM location.
+ */
+extern uint8_t __ram_end__;
+
+/**
+ * @brief Main stack size.
+ * @details This symbol must be exported by the linker script and represents
+ * the main stack size.
+ * @note The main stack is the stack where interrupts and exceptions are
+ * processed.
+ */
+extern uint8_t __main_stack_size__;
+
+/**
+ * @brief Process stack size.
+ * @details This symbol must be exported by the linker script and represents
+ * the process stack size.
+ * @note The process stack is the stack used by the @p main() function.
+ */
+extern uint8_t __process_stack_size__;
+
+/**
+ * @brief ROM image of the data segment start.
+ * @pre The symbol must be aligned to a 32 bits boundary.
+ */
+extern uint32_t _textdata;
+
+/**
+ * @brief Data segment start.
+ * @pre The symbol must be aligned to a 32 bits boundary.
+ */
+extern uint32_t _data;
+
+/**
+ * @brief Data segment end.
+ * @pre The symbol must be aligned to a 32 bits boundary.
+ */
+extern uint32_t _edata;
+
+/**
+ * @brief BSS segment start.
+ * @pre The symbol must be aligned to a 32 bits boundary.
+ */
+extern uint32_t _bss_start;
+
+/**
+ * @brief BSS segment end.
+ * @pre The symbol must be aligned to a 32 bits boundary.
+ */
+extern uint32_t _bss_end;
+
+/**
+ * @brief Constructors table start.
+ * @pre The symbol must be aligned to a 32 bits boundary.
+ */
+extern funcp_t __init_array_start;
+
+/**
+ * @brief Constructors table end.
+ * @pre The symbol must be aligned to a 32 bits boundary.
+ */
+extern funcp_t __init_array_end;
+
+/**
+ * @brief Destructors table start.
+ * @pre The symbol must be aligned to a 32 bits boundary.
+ */
+extern funcp_t __fini_array_start;
+
+/**
+ * @brief Destructors table end.
+ * @pre The symbol must be aligned to a 32 bits boundary.
+ */
+extern funcp_t __fini_array_end;
+
+/**
+ * @brief Application @p main() function.
+ */
+extern void main(void);
+
+/**
+ * @brief Early initialization.
+ * @details This hook is invoked immediately after the stack initialization
+ * and before the DATA and BSS segments initialization. The
+ * default behavior is to do nothing.
+ * @note This function is a weak symbol.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((weak))
+#endif
+void __early_init(void) {}
+
+/**
+ * @brief Late initialization.
+ * @details This hook is invoked after the DATA and BSS segments
+ * initialization and before any static constructor. The
+ * default behavior is to do nothing.
+ * @note This function is a weak symbol.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((weak))
+#endif
+void __late_init(void) {}
+
+/**
+ * @brief Default @p main() function exit handler.
+ * @details This handler is invoked or the @p main() function exit. The
+ * default behavior is to enter an infinite loop.
+ * @note This function is a weak symbol.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((weak, naked))
+#endif
+void _default_exit(void) {
+ while (1)
+ ;
+}
+
+/**
+ * @brief Reset vector.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((naked))
+#endif
+void ResetHandler(void) {
+ uint32_t psp, ctl;
+
+ /* Process Stack initialization, it is allocated below the main stack. The
+ main stack is assumed to be allocated starting from @p __ram_end__
+ extending downward.*/
+ asm volatile ("cpsid i");
+ psp = SYMVAL(__ram_end__) - SYMVAL(__main_stack_size__);
+ asm volatile ("msr PSP, %0" : : "r" (psp));
+
+ ctl = CRT0_CONTROL_INIT;
+ asm volatile ("msr CONTROL, %0" : : "r" (ctl));
+ asm volatile ("isb");
+
+ /* Early initialization hook invocation.*/
+ __early_init();
+
+#if CRT0_INIT_DATA
+ /* DATA segment initialization.*/
+ {
+ uint32_t *tp, *dp;
+
+ tp = &_textdata;
+ dp = &_data;
+ while (dp < &_edata)
+ *dp++ = *tp++;
+ }
+#endif
+
+#if CRT0_INIT_BSS
+ /* BSS segment initialization.*/
+ {
+ uint32_t *bp;
+
+ bp = &_bss_start;
+ while (bp < &_bss_end)
+ *bp++ = 0;
+ }
+#endif
+
+ /* Late initialization hook invocation.*/
+ __late_init();
+
+#if CRT0_CALL_CONSTRUCTORS
+ /* Constructors invocation.*/
+ {
+ funcpp_t fpp = &__init_array_start;
+ while (fpp < &__init_array_end) {
+ (*fpp)();
+ fpp++;
+ }
+ }
+#endif
+
+ /* Invoking application main() function.*/
+ main();
+
+#if CRT0_CALL_DESTRUCTORS
+ /* Destructors invocation.*/
+ {
+ funcpp_t fpp = &__fini_array_start;
+ while (fpp < &__fini_array_end) {
+ (*fpp)();
+ fpp++;
+ }
+ }
+#endif
+
+ /* Invoking the exit handler.*/
+ _default_exit();
+}
+
+/** @} */
diff --git a/os/ports/GCC/ARMCMx/crt0_v6m.s b/os/ports/GCC/ARMCMx/crt0_v6m.s index baaf6f32d..478625d42 100644 --- a/os/ports/GCC/ARMCMx/crt0_v6m.s +++ b/os/ports/GCC/ARMCMx/crt0_v6m.s @@ -1,5 +1,6 @@ /*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
diff --git a/os/ports/GCC/ARMCMx/crt0_v7m.s b/os/ports/GCC/ARMCMx/crt0_v7m.s index 4e4a40631..c5f714a26 100644 --- a/os/ports/GCC/ARMCMx/crt0_v7m.s +++ b/os/ports/GCC/ARMCMx/crt0_v7m.s @@ -1,5 +1,6 @@ /*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
diff --git a/os/ports/GCC/ARMCMx/nvic.c b/os/ports/GCC/ARMCMx/nvic.c index fb470c2e1..51e4280f2 100644 --- a/os/ports/GCC/ARMCMx/nvic.c +++ b/os/ports/GCC/ARMCMx/nvic.c @@ -1,5 +1,6 @@ /*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
diff --git a/os/ports/GCC/ARMCMx/nvic.h b/os/ports/GCC/ARMCMx/nvic.h index bd5d0f31b..02f010c4a 100644 --- a/os/ports/GCC/ARMCMx/nvic.h +++ b/os/ports/GCC/ARMCMx/nvic.h @@ -1,5 +1,6 @@ /*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
diff --git a/os/ports/GCC/ARMCMx/old/chcore_v7m.c b/os/ports/GCC/ARMCMx/old/chcore_v7m.c index c8b2f3af6..244ff396e 100644 --- a/os/ports/GCC/ARMCMx/old/chcore_v7m.c +++ b/os/ports/GCC/ARMCMx/old/chcore_v7m.c @@ -1,5 +1,6 @@ /*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
@@ -53,7 +54,6 @@ void SysTickVector(void) { chSysUnlockFromIsr();
}
-#if !defined(CH_CURRP_REGISTER_CACHE)
#define PUSH_CONTEXT(sp, prio) { \
asm volatile ("mrs %0, PSP \n\t" \
"stmdb %0!, {r3-r11,lr}" : \
@@ -66,20 +66,6 @@ void SysTickVector(void) { "msr BASEPRI, r3 \n\t" \
"bx lr" : "=r" (sp) : "r" (sp)); \
}
-#else /* defined(CH_CURRP_REGISTER_CACHE) */
-#define PUSH_CONTEXT(sp, prio) { \
- asm volatile ("mrs %0, PSP \n\t" \
- "stmdb %0!, {r3-r6,r8-r11, lr}" : \
- "=r" (sp) : "r" (sp), "r" (prio)); \
-}
-
-#define POP_CONTEXT(sp) { \
- asm volatile ("ldmia %0!, {r3-r6,r8-r11, lr} \n\t" \
- "msr PSP, %0 \n\t" \
- "msr BASEPRI, r3 \n\t" \
- "bx lr" : "=r" (sp) : "r" (sp)); \
-}
-#endif /* defined(CH_CURRP_REGISTER_CACHE) */
/**
* @brief SVC vector.
diff --git a/os/ports/GCC/ARMCMx/old/chcore_v7m.h b/os/ports/GCC/ARMCMx/old/chcore_v7m.h index 480542db1..b94afdca3 100644 --- a/os/ports/GCC/ARMCMx/old/chcore_v7m.h +++ b/os/ports/GCC/ARMCMx/old/chcore_v7m.h @@ -1,5 +1,6 @@ /*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
@@ -95,12 +96,12 @@ struct intctx { * @brief Stack size for the system idle thread.
* @details This size depends on the idle thread implementation, usually
* the idle thread should take no more space than those reserved
- * by @p INT_REQUIRED_STACK.
+ * by @p PORT_INT_REQUIRED_STACK.
* @note In this port it is set to 4 because the idle thread does have
* a stack frame when compiling without optimizations.
*/
-#ifndef IDLE_THREAD_STACK_SIZE
-#define IDLE_THREAD_STACK_SIZE 4
+#ifndef PORT_IDLE_THREAD_STACK_SIZE
+#define PORT_IDLE_THREAD_STACK_SIZE 4
#endif
/**
@@ -112,8 +113,8 @@ struct intctx { * @p extctx is known to be zero.
* @note This port requires no extra stack space for interrupt handling.
*/
-#ifndef INT_REQUIRED_STACK
-#define INT_REQUIRED_STACK 0
+#ifndef PORT_INT_REQUIRED_STACK
+#define PORT_INT_REQUIRED_STACK 0
#endif
/**
diff --git a/os/ports/GCC/ARMCMx/port.dox b/os/ports/GCC/ARMCMx/port.dox index 32b736434..8f5efc9aa 100644 --- a/os/ports/GCC/ARMCMx/port.dox +++ b/os/ports/GCC/ARMCMx/port.dox @@ -1,5 +1,6 @@ /*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
@@ -25,9 +26,28 @@ * This port supports all the cores implementing the ARMv6-M and ARMv7-M
* architectures.
*
- * @section ARMCMx_STATES_A System logical states in ARMv6-M mode
- * The ChibiOS/RT logical @ref system_states are mapped as follow in the ARM
- * Cortex-M0 port:
+ * @section ARMCMx_MODES Kernel Modes
+ * The Cortex-Mx port supports two distinct kernel modes:
+ * - <b>Advanced Kernel</b> mode. In this mode the kernel only masks
+ * interrupt sources with priorities below or equal to the
+ * @p CORTEX_BASEPRI_KERNEL level. Higher priorities are not affected by
+ * the kernel critical sections and can be used for fast interrupts.
+ * This mode is not available in the ARMv6-M architecture which does not
+ * support priority masking.
+ * - <b>Compact Kernel</b> mode. In this mode the kernel handles IRQ priorities
+ * in a simplified way, all interrupt sources are disabled when the kernel
+ * enters into a critical zone and re-enabled on exit. This is simple and
+ * adequate for most applications, this mode results in a more compact and
+ * faster kernel.
+ * .
+ * The selection of the mode is performed using the port configuration option
+ * @p CORTEX_SIMPLIFIED_PRIORITY. Apart from the different handling of
+ * interrupts there are no other differences between the two modes. The
+ * kernel API is exactly the same.
+ *
+ * @section ARMCMx_STATES_A System logical states in Compact Kernel mode
+ * The ChibiOS/RT logical @ref system_states are mapped as follow in Compact
+ * Kernel mode:
* - <b>Init</b>. This state is represented by the startup code and the
* initialization code before @p chSysInit() is executed. It has not a
* special hardware state associated.
@@ -52,21 +72,21 @@ * mode.
* - <b>Serving Fast Interrupt</b>. This state is not implemented in the
* ARMv6-M implementation.
- * - <b>Serving Non-Maskable Interrupt</b>. The Cortex-M3 has a specific
+ * - <b>Serving Non-Maskable Interrupt</b>. The Cortex-Mx has a specific
* asynchronous NMI vector and several synchronous fault vectors that can
* be considered belonging to this category.
* - <b>Halted</b>. Implemented as an infinite loop after globally masking all
* the maskable interrupt sources. The ARM state is whatever the processor
* was running when @p chSysHalt() was invoked.
*
- * @section ARMCMx_STATES_B System logical states in ARMv7-M mode
- * The ChibiOS/RT logical @ref system_states are mapped as follow in the ARM
- * Cortex-M3 port:
+ * @section ARMCMx_STATES_B System logical states in Advanced Kernel mode
+ * The ChibiOS/RT logical @ref system_states are mapped as follow in the
+ * Advanced Kernel mode:
* - <b>Init</b>. This state is represented by the startup code and the
* initialization code before @p chSysInit() is executed. It has not a
* special hardware state associated.
* - <b>Normal</b>. This is the state the system has after executing
- * @p chSysInit(). In this state the ARM Cortex-M3 has the BASEPRI register
+ * @p chSysInit(). In this state the ARM Cortex-Mx has the BASEPRI register
* set at @p CORTEX_BASEPRI_USER level, interrupts are not masked. The
* processor is running in thread-privileged mode.
* - <b>Suspended</b>. In this state the interrupt sources are not globally
@@ -92,7 +112,7 @@ * - <b>Serving Fast Interrupt</b>. It is basically the same of the SRI state
* but it is not possible to switch to the I-Locked state because fast
* interrupts can preempt the kernel critical zone.
- * - <b>Serving Non-Maskable Interrupt</b>. The Cortex-M3 has a specific
+ * - <b>Serving Non-Maskable Interrupt</b>. The Cortex-Mx has a specific
* asynchronous NMI vector and several synchronous fault vectors that can
* be considered belonging to this category.
* - <b>Halted</b>. Implemented as an infinite loop after globally masking all
@@ -139,17 +159,24 @@ * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE
* thread. Usually there is no need to change this value unless inserting
* code in the IDLE thread using the @p IDLE_LOOP_HOOK hook macro.
- * - @p CORTEX_BASEPRI_KERNEL, this is the @p BASEPRI value for the kernel lock
- * code. Code running at higher priority levels must not invoke any OS API.
- * This setting is specific to the ARMv7-M architecture.
* - @p CORTEX_PRIORITY_SYSTICK, priority of the SYSTICK handler.
- * - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler.
* - @p CORTEX_PRIORITY_PENDSV, priority of the PENDSV handler.
* - @p CORTEX_ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the
* @p <b>wfi</b> instruction from within the idle loop. This option is
* defaulted to FALSE because it can create problems with some debuggers.
* Setting this option to TRUE reduces the system power requirements.
* .
+ * @section ARMCMx_CONF_1 ARMv6-M specific options
+ * The following options are specific for the ARMv6-M architecture:
+ * - @p CORTEX_ALTERNATE_SWITCH, when activated makes the OS use the PendSV
+ * exception instead of NMI as preemption handler.
+ * .
+ * @section ARMCMx_CONF_2 ARMv7-M specific options
+ * The following options are specific for the ARMv6-M architecture:
+ * - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler.
+ * - @p CORTEX_SIMPLIFIED_PRIORITY, when enabled activates the Compact kernel
+ * mode.
+ * .
* @ingroup ARMCMx
*/
@@ -199,15 +226,19 @@ * @section ARMCMx_STARTUP_2 Expected linker symbols
* The startup code starts at the symbol @p ResetHandler and expects the
* following symbols to be defined in the linker script:
- * - @p __ram_end__ RAM end location +1.
+ * - @p __ram_end__ End of RAM.
* - @p __main_stack_size__ Exception stack size.
* - @p __process_stack_size__ Process stack size. This is the stack area used
* by the @p main() function.
- * - @p _textdata address of the data segment source read only data.
- * - @p _data data segment start location.
- * - @p _edata data segment end location +1.
- * - @p _bss_start BSS start location.
- * - @p _bss_end BSS end location +1.
+ * - @p _textdata Address of the data segment source read only data.
+ * - @p _data Start of the data segment.
+ * - @p _edata End of the data segment end location.
+ * - @p _bss_start Start of the BSS.
+ * - @p _bss_end End of the BSS segment.
+ * - @p __init_array_start Start of the constructors array.
+ * - @p __init_array_end End of the constructors array.
+ * - @p __fini_array_start Start of the destructors array.
+ * - @p __fini_array_end End of the destructors array.
* .
* @ingroup ARMCMx
*/
|