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authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2010-08-31 18:56:49 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2010-08-31 18:56:49 +0000
commit58e000a8366bad3848fe20e84b3cee95836861b1 (patch)
treed51eee9beef5473fc66d3ad8b998b07084d02687 /os/ports/GCC/ARMCMx
parenta14fa4358d81cff24dbf0dbc37046b8e1629b512 (diff)
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2153 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/ports/GCC/ARMCMx')
-rw-r--r--os/ports/GCC/ARMCMx/chcore_v6m.c8
-rw-r--r--os/ports/GCC/ARMCMx/chcore_v7m.c24
2 files changed, 18 insertions, 14 deletions
diff --git a/os/ports/GCC/ARMCMx/chcore_v6m.c b/os/ports/GCC/ARMCMx/chcore_v6m.c
index d331b203d..c8ee32387 100644
--- a/os/ports/GCC/ARMCMx/chcore_v6m.c
+++ b/os/ports/GCC/ARMCMx/chcore_v6m.c
@@ -71,7 +71,7 @@ void _port_switch_from_irq(void) {
"ldr r0, =_port_saved_pc \n\t"
"ldr r0, [r0] \n\t"
"add r0, r0, #1 \n\t"
- "str r0, [sp, #28]");
+ "str r0, [sp, #28]" : : : "memory");
chSchDoRescheduleI();
@@ -85,7 +85,7 @@ void _port_switch_from_irq(void) {
"msr APSR, r0 \n\t"
"mov lr, r2 \n\t"
"cpsie i \n\t"
- "pop {r0, r1, r2, r3, pc}");
+ "pop {r0, r1, r2, r3, pc}" : : : "memory");
}
#define PUSH_CONTEXT(sp) { \
@@ -94,7 +94,7 @@ void _port_switch_from_irq(void) {
"mov r5, r9 \n\t" \
"mov r6, r10 \n\t" \
"mov r7, r11 \n\t" \
- "push {r4, r5, r6, r7}"); \
+ "push {r4, r5, r6, r7}" : : : "memory"); \
}
#define POP_CONTEXT(sp) { \
@@ -103,7 +103,7 @@ void _port_switch_from_irq(void) {
"mov r9, r5 \n\t" \
"mov r10, r6 \n\t" \
"mov r11, r7 \n\t" \
- "pop {r4, r5, r6, r7, pc}" : : "r" (sp)); \
+ "pop {r4, r5, r6, r7, pc}" : : "r" (sp) : "memory"); \
}
/**
diff --git a/os/ports/GCC/ARMCMx/chcore_v7m.c b/os/ports/GCC/ARMCMx/chcore_v7m.c
index f546a11fa..527161ebf 100644
--- a/os/ports/GCC/ARMCMx/chcore_v7m.c
+++ b/os/ports/GCC/ARMCMx/chcore_v7m.c
@@ -32,34 +32,38 @@
* @brief Internal context stacking.
*/
#define PUSH_CONTEXT() { \
- asm volatile ("push {r4, r5, r6, r7, r8, r9, r10, r11, lr}"); \
+ asm volatile ("push {r4, r5, r6, r7, r8, r9, r10, r11, lr}" \
+ : : : "memory"); \
}
/**
* @brief Internal context unstacking.
*/
#define POP_CONTEXT() { \
- asm volatile ("pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}"); \
+ asm volatile ("pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}" \
+ : : : "memory"); \
}
#else /* defined(CH_CURRP_REGISTER_CACHE) */
#define PUSH_CONTEXT() { \
- asm volatile ("push {r4, r5, r6, r8, r9, r10, r11, lr}"); \
+ asm volatile ("push {r4, r5, r6, r8, r9, r10, r11, lr}" \
+ : : : "memory"); \
}
#define POP_CONTEXT() { \
- asm volatile ("pop {r4, r5, r6, r8, r9, r10, r11, pc}"); \
+ asm volatile ("pop {r4, r5, r6, r8, r9, r10, r11, pc}" \
+ : : : "memory"); \
}
#endif /* defined(CH_CURRP_REGISTER_CACHE) */
#if !CH_OPTIMIZE_SPEED
void _port_lock(void) {
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL;
- asm volatile ("msr BASEPRI, %0" : : "r" (tmp));
+ asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory");
}
void _port_unlock(void) {
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED;
- asm volatile ("msr BASEPRI, %0" : : "r" (tmp));
+ asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory");
}
#endif
@@ -89,9 +93,9 @@ void SVCallVector(void) {
/* Discarding the current exception context and positioning the stack to
point to the real one.*/
- asm volatile ("mrs %0, PSP" : "=r" (ctxp) : );
+ asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory");
ctxp++;
- asm volatile ("msr PSP, %0" : : "r" (ctxp));
+ asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory");
port_unlock_from_isr();
}
@@ -106,9 +110,9 @@ void _port_irq_epilogue(void) {
/* Adding an artificial exception return context, there is no need to
populate it fully.*/
- asm volatile ("mrs %0, PSP" : "=r" (ctxp) : );
+ asm volatile ("mrs %0, PSP" : "=r" (ctxp) : : "memory");
ctxp--;
- asm volatile ("msr PSP, %0" : : "r" (ctxp));
+ asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory");
ctxp->pc = _port_switch_from_isr;
ctxp->xpsr = (regarm_t)0x01000000;
/* Note, returning without unlocking is intentional, this is done in