git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1791 35acf78f-673a-0410-8e92-d51de3d6d3f4

3 files changed, 340 insertions, 0 deletions

diff --git a/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h b/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h
new file mode 100644
index 000000000..790d529cb
--- /dev/null
+++ b/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h
@@ -0,0 +1,118 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/**

+ * @file    ARMCMx/LPC111x/cmparams.h

+ * @brief   ARM Cortex-M0 LPC111x specific parameters.

+ *

+ * @defgroup ARMCMx_LPC111x LPC111x specific parameters

+ * @ingroup ARMCMx

+ * @details This file contains the Cortex-M0 specific parameters for the

+ *          LPC111x platform.

+ * @{

+ */

+

+#ifndef _CMPARAMS_H_

+#define _CMPARAMS_H_

+

+/*===========================================================================*/

+/* Constants parameters.                                                     */

+/*===========================================================================*/

+

+/**

+ * @brief   Cortex core model.

+ */

+#define CORTEX_MODEL            CORTEX_M0

+

+/**

+ * @brief   Systick unit presence.

+ */

+#define CORTEX_HAS_ST           TRUE

+

+/**

+ * @brief   Memory Protection unit presence.

+ */

+#define CORTEX_HAS_MPU          FALSE

+

+/**

+ * @brief   Number of bits in priority masks.

+ * @details The available number of priority levels is equal to

+ *          (1 << @p CORTEX_PRIORITY_BITS).

+ */

+#define CORTEX_PRIORITY_BITS    2

+

+/**

+ * @brief   Priority to priority mask conversion macro.

+ */

+#define CORTEX_PRIORITY(n)      ((n) << (8 - CORTEX_PRIORITY_BITS))

+

+/*===========================================================================*/

+/* Configurable parameters.                                                  */

+/*===========================================================================*/

+

+/**

+ * @brief   BASEPRI user level, 0 = disabled.

+ */

+#ifndef CORTEX_BASEPRI_USER

+#define CORTEX_BASEPRI_USER     CORTEX_PRIORITY(0)

+#endif

+

+/**

+ * @brief   BASEPRI level within kernel lock.

+ * @details Priority levels higher than this one (lower values) are unaffected

+ *          by the OS activity and can be classified as fast interrupt sources,

+ *          see @ref interrupt_classes.

+ */

+#ifndef CORTEX_BASEPRI_KERNEL

+#define CORTEX_BASEPRI_KERNEL   CORTEX_PRIORITY(1)

+#endif

+

+/**

+ * @brief   SVCALL handler priority.

+ * @note    This priority must always be one level above the @p BASEPRI_KERNEL

+ *          value.

+ * @note    It is recommended, but not mandatory, to leave this priority level

+ *          for this handler alone.

+ */

+#ifndef CORTEX_PRIORITY_SVCALL

+#define CORTEX_PRIORITY_SVCALL  CORTEX_PRIORITY(0)

+#endif

+

+/**

+ * @brief   SYSTICK handler priority.

+ */

+#ifndef CORTEX_PRIORITY_SYSTICK

+#define CORTEX_PRIORITY_SYSTICK CORTEX_PRIORITY(2)

+#endif

+

+/**

+ * @brief   PENDSV handler priority.

+ * @note    It is recommended to leave this priority level for this handler

+ *          alone.

+ * @note    This is a reserved handler and its priority must always be the

+ *          lowest priority in the system in order to be always executed last

+ *          in the interrupt servicing chain.

+ */

+#ifndef CORTEX_PRIORITY_PENDSV

+#define CORTEX_PRIORITY_PENDSV  CORTEX_PRIORITY(3)

+#endif

+

+#endif /* _CMPARAMS_H_ */

+

+/** @} */

diff --git a/os/ports/GCC/ARMCMx/LPC11xx/port.mk b/os/ports/GCC/ARMCMx/LPC11xx/port.mk
new file mode 100644
index 000000000..2ea4fc00e
--- /dev/null
+++ b/os/ports/GCC/ARMCMx/LPC11xx/port.mk
@@ -0,0 +1,10 @@
+# List of the ChibiOS/RT Cortex-M0 LPC111x port files.

+PORTSRC = ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \

+          ${CHIBIOS}/os/ports/GCC/ARMCMx/nvic.c

+#          ${CHIBIOS}/os/ports/GCC/ARMCMx/cmsis/core_cm0.c

+

+PORTASM = ${CHIBIOS}/os/ports/GCC/ARMCMx/crt0.s

+

+PORTINC = ${CHIBIOS}/os/ports/GCC/ARMCMx \

+          ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC111x \

+          ${CHIBIOS}/os/ports/GCC/ARMCMx/cmsis

diff --git a/os/ports/GCC/ARMCMx/LPC11xx/vectors.s b/os/ports/GCC/ARMCMx/LPC11xx/vectors.s
new file mode 100644
index 000000000..44ea654ce
--- /dev/null
+++ b/os/ports/GCC/ARMCMx/LPC11xx/vectors.s
@@ -0,0 +1,212 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+.syntax unified

+.thumb

+

+.section vectors

+_vectors:

+        .word   __ram_end__

+        .word   ResetHandler

+        .word   NMIVector

+        .word   HardFaultVector

+        .word   MemManageVector

+        .word   BusFaultVector

+        .word   UsageFaultVector

+        .word   Vector1C

+        .word   Vector20

+        .word   Vector24

+        .word   Vector28

+        .word   SVCallVector

+        .word   DebugMonitorVector

+        .word   Vector34

+        .word   PendSVVector

+        .word   SysTickVector

+        .word   Vector40

+        .word   Vector44

+        .word   Vector48

+        .word   Vector4C

+        .word   Vector50

+        .word   Vector54

+        .word   Vector58

+        .word   Vector5C

+        .word   Vector60

+        .word   Vector64

+        .word   Vector68

+        .word   Vector6C

+        .word   Vector70

+        .word   Vector74

+        .word   Vector78

+        .word   Vector7C

+        .word   Vector80

+        .word   Vector84

+        .word   Vector88

+        .word   Vector8C

+        .word   Vector90

+        .word   Vector94

+        .word   Vector98

+        .word   Vector9C

+        .word   VectorA0

+        .word   VectorA4

+        .word   VectorA8

+        .word   VectorAC

+        .word   VectorB0

+        .word   VectorB4

+        .word   VectorB8

+        .word   VectorBC

+

+.weak NMIVector

+NMIVector:

+

+.weak HardFaultVector

+HardFaultVector:

+

+.weak MemManageVector

+MemManageVector:

+

+.weak BusFaultVector

+BusFaultVector:

+

+.weak UsageFaultVector

+UsageFaultVector:

+

+.weak Vector1C

+Vector1C:

+

+.weak Vector20

+Vector20:

+

+.weak Vector24

+Vector24:

+

+.weak Vector28

+Vector28:

+

+.weak SVCallVector

+SVCallVector:

+

+.weak DebugMonitorVector

+DebugMonitorVector:

+

+.weak Vector34

+Vector34:

+

+.weak PendSVVector

+PendSVVector:

+

+.weak SysTickVector

+SysTickVector:

+

+.weak Vector40

+Vector40:

+

+.weak Vector44

+Vector44:

+

+.weak Vector48

+Vector48:

+

+.weak Vector4C

+Vector4C:

+

+.weak Vector50

+Vector50:

+

+.weak Vector54

+Vector54:

+

+.weak Vector58

+Vector58:

+

+.weak Vector5C

+Vector5C:

+

+.weak Vector60

+Vector60:

+

+.weak Vector64

+Vector64:

+

+.weak Vector68

+Vector68:

+

+.weak Vector6C

+Vector6C:

+

+.weak Vector70

+Vector70:

+

+.weak Vector74

+Vector74:

+

+.weak Vector78

+Vector78:

+

+.weak Vector7C

+Vector7C:

+

+.weak Vector80

+Vector80:

+

+.weak Vector84

+Vector84:

+

+.weak Vector88

+Vector88:

+

+.weak Vector8C

+Vector8C:

+

+.weak Vector90

+Vector90:

+

+.weak Vector94

+Vector94:

+

+.weak Vector98

+Vector98:

+

+.weak Vector9C

+Vector9C:

+

+.weak VectorA0

+VectorA0:

+

+.weak VectorA4

+VectorA4:

+

+.weak VectorA8

+VectorA8:

+

+.weak VectorAC

+VectorAC:

+

+.weak VectorB0

+VectorB0:

+

+.weak VectorB4

+VectorB4:

+

+.weak VectorB8

+VectorB8:

+

+.weak VectorBC

+VectorBC:

+

+here:   b       here