git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1769 35acf78f-673a-0410-8e92-d51de3d6d3f4

4 files changed, 138 insertions, 55 deletions

diff --git a/os/ports/GCC/ARMCM3/STM32F103/cmparams.h b/os/ports/GCC/ARMCM3/STM32F103/cmparams.h
new file mode 100644
index 000000000..29b4093be
--- /dev/null
+++ b/os/ports/GCC/ARMCM3/STM32F103/cmparams.h
@@ -0,0 +1,115 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/**

+ * @file    ARMCM3/STM32F103/cmparams.h

+ * @brief   ARM Cortex-M3 STM32 specific parameters.

+ *

+ * @addtogroup ARMCM3_STM32F103

+ * @{

+ */

+

+#ifndef _CMPARAMS_H_

+#define _CMPARAMS_H_

+

+/*===========================================================================*/

+/* Constants parameters.                                                     */

+/*===========================================================================*/

+

+/**

+ * @brief   Cortex core model.

+ */

+#define CORTEX_MODEL            CORTEX_M3

+

+/**

+ * @brief   Systick unit presence.

+ */

+#define CORTEX_HAS_ST           TRUE

+

+/**

+ * @brief   Memory Protection unit presence.

+ */

+#define CORTEX_HAS_MPU          FALSE

+

+/**

+ * @brief   Number of bits in priority masks.

+ * @details The available number of priority levels is equal to

+ *          (1 << @p CORTEX_PRIORITY_BITS).

+ */

+#define CORTEX_PRIORITY_BITS    4

+

+/**

+ * @brief   Priority to priority mask conversion macro.

+ */

+#define CORTEX_PRIORITY(n)      ((n) << (8 - CORTEX_PRIORITY_BITS))

+

+/*===========================================================================*/

+/* Configurable parameters.                                                  */

+/*===========================================================================*/

+

+/**

+ * @brief   BASEPRI user level, 0 = disabled.

+ */

+#ifndef CORTEX_BASEPRI_USER

+#define CORTEX_BASEPRI_USER     CORTEX_PRIORITY(0)

+#endif

+

+/**

+ * @brief   BASEPRI level within kernel lock.

+ * @details Priority levels higher than this one (lower values) are unaffected

+ *          by the OS activity and can be classified as fast interrupt sources,

+ *          see @ref interrupt_classes.

+ */

+#ifndef CORTEX_BASEPRI_KERNEL

+#define CORTEX_BASEPRI_KERNEL   CORTEX_PRIORITY(4)

+#endif

+

+/**

+ * @brief   SVCALL handler priority.

+ * @note    This priority must always be one level above the @p BASEPRI_KERNEL

+ *          value.

+ * @note    It is recommended, but not mandatory, to leave this priority level

+ *          for this handler alone.

+ */

+#ifndef CORTEX_PRIORITY_SVCALL

+#define CORTEX_PRIORITY_SVCALL  CORTEX_PRIORITY(3)

+#endif

+

+/**

+ * @brief   SYSTICK handler priority.

+ */

+#ifndef CORTEX_PRIORITY_SYSTICK

+#define CORTEX_PRIORITY_SYSTICK CORTEX_PRIORITY(8)

+#endif

+

+/**

+ * @brief   PENDSV handler priority.

+ * @note    It is recommended to leave this priority level for this handler

+ *          alone.

+ * @note    This is a reserved handler and its priority must always be the

+ *          lowest priority in the system in order to be always executed last

+ *          in the interrupt servicing chain.

+ */

+#ifndef CORTEX_PRIORITY_PENDSV

+#define CORTEX_PRIORITY_PENDSV  CORTEX_PRIORITY(15)

+#endif

+

+#endif /* _CMPARAMS_H_ */

+

+/** @} */

diff --git a/os/ports/GCC/ARMCM3/port.mk b/os/ports/GCC/ARMCM3/STM32F103/port.mk
index ccb5ea62e..c656f7b10 100644
--- a/os/ports/GCC/ARMCM3/port.mk
+++ b/os/ports/GCC/ARMCM3/STM32F103/port.mk
@@ -6,4 +6,5 @@ PORTSRC = ${CHIBIOS}/os/ports/GCC/ARMCM3/chcore.c \
 PORTASM = ${CHIBIOS}/os/ports/GCC/ARMCM3/crt0.s

 

 PORTINC = ${CHIBIOS}/os/ports/GCC/ARMCM3 \

+          ${CHIBIOS}/os/ports/GCC/ARMCM3/STM32F103 \

           ${CHIBIOS}/os/ports/GCC/ARMCM3/cmsis

diff --git a/os/ports/GCC/ARMCM3/chcore.c b/os/ports/GCC/ARMCM3/chcore.c
index 2a5727961..350adf9b0 100644
--- a/os/ports/GCC/ARMCM3/chcore.c
+++ b/os/ports/GCC/ARMCM3/chcore.c
@@ -109,7 +109,7 @@ void SVCallVector(Thread *ntp, Thread *otp) {
 

 #ifdef CH_CURRP_REGISTER_CACHE

 #define PUSH_CONTEXT(sp) {                                              \

-  register uint32_t tmp asm ("r3") = BASEPRI_USER;                      \

+  register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_USER;               \

   asm volatile ("mrs     %0, PSP                                \n\t"   \

                 "stmdb   %0!, {r3-r6,r8-r11, lr}" :                     \

                 "=r" (sp) : "r" (sp), "r" (tmp));                       \

@@ -123,7 +123,7 @@ void SVCallVector(Thread *ntp, Thread *otp) {
 }

 #else

 #define PUSH_CONTEXT(sp) {                                              \

-  register uint32_t tmp asm ("r3") = BASEPRI_USER;                      \

+  register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_USER;               \

   asm volatile ("mrs     %0, PSP                                \n\t"   \

                 "stmdb   %0!, {r3-r11,lr}" :                            \

                 "=r" (sp) : "r" (sp), "r" (tmp));                       \

diff --git a/os/ports/GCC/ARMCM3/chcore.h b/os/ports/GCC/ARMCM3/chcore.h
index fbed01054..a615386d2 100644
--- a/os/ports/GCC/ARMCM3/chcore.h
+++ b/os/ports/GCC/ARMCM3/chcore.h
@@ -39,67 +39,34 @@
 #define ENABLE_WFI_IDLE         0

 #endif

 

-/**

- * @brief   BASEPRI user level, 0 = disabled.

- */

-#ifndef BASEPRI_USER

-#define BASEPRI_USER            0

-#endif

-

-/**

- * @brief   BASEPRI level within kernel lock.

- * @details Priority levels higher than this one (lower values) are unaffected

- *          by the OS activity and can be classified as fast interrupt sources,

- *          see @ref interrupt_classes.

- */

-#ifndef BASEPRI_KERNEL

-#define BASEPRI_KERNEL          0x40

-#endif

-

-/**

- * @brief   SVCALL handler priority.

- * @note    This priority must always be one level above the @p BASEPRI_KERNEL

- *          value.

- * @note    It is recommended, but not mandatory, to leave this priority level

- *          for this handler alone.

- */

-#ifndef PRIORITY_SVCALL

-#define PRIORITY_SVCALL         (BASEPRI_KERNEL - 0x10)

-#endif

+#define CORTEX_M0               0       /**< @brief Cortex-M0 variant.      */

+#define CORTEX_M3               3       /**< @brief Cortex-M3 variant.      */

 

 /**

- * @brief   SYSTICK handler priority.

+ * @brief   Name of the implemented architecture.

  */

-#ifndef PRIORITY_SYSTICK

-#define PRIORITY_SYSTICK        0x80

-#endif

+#define CH_ARCHITECTURE_NAME "ARM"

 

-/**

- * @brief   PENDSV handler priority.

- * @note    It is recommended to leave this priority level for this handler

- *          alone.

- * @note    This is a reserved handler and its priority must always be the

- *          lowest priority in the system in order to be always executed last

- *          in the interrupt servicing chain.

- */

-#ifndef PRIORITY_PENDSV

-#define PRIORITY_PENDSV         0xF0

-#endif

+/* Inclusion of the Cortex-Mx implementation specific parameters.*/

+#include "cmparams.h"

 

+/* Generating model-dependent info.*/

+#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)

 /**

  * @brief   Macro defining the ARM Cortex-M3 architecture.

  */

 #define CH_ARCHITECTURE_ARMCM3

 

 /**

- * @brief   Name of the implemented architecture.

- */

-#define CH_ARCHITECTURE_NAME "ARM"

-

-/**

  * @brief   Name of the architecture variant (optional).

  */

-#define CH_CORE_VARIANT_NAME "Cortex-M3"

+#define CH_CORE_VARIANT_NAME    "Cortex-M3"

+#elif (CORTEX_MODEL == CORTEX_M0)

+#define CH_ARCHITECTURE_ARMCM0

+#define CH_CORE_VARIANT_NAME    "Cortex-M0"

+#else

+#error "unknown or unsupported Cortex-M model"

+#endif

 

 /**

  * @brief   32 bits stack and memory alignment enforcement.

@@ -170,7 +137,7 @@ struct context {
   tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace +              \

                                      wsize -                            \

                                      sizeof(struct intctx));            \

-  tp->p_ctx.r13->basepri = BASEPRI_USER;                                \

+  tp->p_ctx.r13->basepri = CORTEX_BASEPRI_USER;                         \

   tp->p_ctx.r13->lr_exc = (regarm_t)0xFFFFFFFD;                         \

   tp->p_ctx.r13->r0 = arg;                                              \

   tp->p_ctx.r13->lr_thd = chThdExit;                                    \

@@ -263,7 +230,7 @@ struct context {
  */

 #if CH_OPTIMIZE_SPEED

 #define port_lock() {                                                   \

-  register uint32_t tmp asm ("r3") = BASEPRI_KERNEL;                    \

+  register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL;             \

   asm volatile ("msr     BASEPRI, %0" : : "r" (tmp));                   \

 }

 #else

@@ -280,7 +247,7 @@ struct context {
  */

 #if CH_OPTIMIZE_SPEED

 #define port_unlock() {                                                 \

-  register uint32_t tmp asm ("r3") = BASEPRI_USER;                      \

+  register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_USER;               \

   asm volatile ("msr     BASEPRI, %0" : : "r" (tmp));                   \

 }

 #else

@@ -321,7 +288,7 @@ struct context {
  * @note    In this port it raises/lowers the base priority to kernel level.

  */

 #define port_suspend() {                                                \

-  register uint32_t tmp asm ("r3") = BASEPRI_KERNEL;                    \

+  register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL;             \

   asm volatile ("msr     BASEPRI, %0                    \n\t"           \

                 "cpsie   i" : : "r" (tmp));                             \

 }

@@ -331,7 +298,7 @@ struct context {
  * @note    In this port it lowers the base priority to user level.

  */

 #define port_enable() {                                                 \

-  register uint32_t tmp asm ("r3") = BASEPRI_USER;                      \

+  register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_USER;               \

   asm volatile ("msr     BASEPRI, %0                    \n\t"           \

                 "cpsie   i" : : "r" (tmp));                             \

 }