git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6254 35acf78f-673a-0410-8e92-d51de3d6d3f4

4 files changed, 29 insertions, 23 deletions

diff --git a/os/nil/ports/ARMCMx/nilcore.c b/os/nil/ports/ARMCMx/nilcore.c
index c66ce160c..e50dc5b80 100644
--- a/os/nil/ports/ARMCMx/nilcore.c
+++ b/os/nil/ports/ARMCMx/nilcore.c
@@ -19,14 +19,14 @@
 */

 

 /**

- * @file    ARMCMx/chcore.c

+ * @file    ARMCMx/nilcore.c

  * @brief   ARM Cortex-Mx port code.

  *

  * @addtogroup ARMCMx_CORE

  * @{

  */

 

-#include "ch.h"

+#include "nil.h"

 

 /*===========================================================================*/

 /* Module local definitions.                                                 */

@@ -52,4 +52,19 @@
 /* Module exported functions.                                                */

 /*===========================================================================*/

 

+/**

+ * @brief   Halts the system.

+ * @note    The function is declared as a weak symbol, it is possible

+ *          to redefine it in your application code.

+ */

+#if !defined(__DOXYGEN__)

+__attribute__((naked, weak))

+#endif

+void port_halt(void) {

+

+  port_disable();

+  while (true) {

+  }

+}

+

 /** @} */

diff --git a/os/nil/ports/ARMCMx/nilcore.h b/os/nil/ports/ARMCMx/nilcore.h
index c2eb68078..9a31f5c87 100644
--- a/os/nil/ports/ARMCMx/nilcore.h
+++ b/os/nil/ports/ARMCMx/nilcore.h
@@ -19,15 +19,15 @@
 */

 

 /**

- * @file    ARMCMx/chcore.h

+ * @file    ARMCMx/nilcore.h

  * @brief   ARM Cortex-Mx port macros and structures.

  *

  * @addtogroup ARMCMx_CORE

  * @{

  */

 

-#ifndef _CHCORE_H_

-#define _CHCORE_H_

+#ifndef _NILCORE_H_

+#define _NILCORE_H_

 

 /*===========================================================================*/

 /* Module constants.                                                         */

@@ -191,11 +191,11 @@ struct port_intctx {};
 /* Includes the sub-architecture-specific part.*/

 #if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M0PLUS) ||       \

     (CORTEX_MODEL == CORTEX_M1)

-#include "chcore_v6m.h"

+#include "nilcore_v6m.h"

 #elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4)

-#include "chcore_v7m.h"

+#include "nilcore_v7m.h"

 #endif

 

-#endif /* _CHCORE_H_ */

+#endif /* _NILCORE_H_ */

 

 /** @} */

diff --git a/os/nil/ports/ARMCMx/nilcore_timer.h b/os/nil/ports/ARMCMx/nilcore_timer.h
index 166610b2c..9079dea8c 100644
--- a/os/nil/ports/ARMCMx/nilcore_timer.h
+++ b/os/nil/ports/ARMCMx/nilcore_timer.h
@@ -19,7 +19,7 @@
 */

 

 /**

- * @file    ARMCMx/chcore_timer.h

+ * @file    ARMCMx/nilcore_timer.h

  * @brief   System timer header file.

  *

  * @addtogroup ARMCMx_TIMER

@@ -33,7 +33,7 @@
 /* If, for some reason, the use of the HAL-provided ST timer port interface

    is not wanted, it is possible to provide the timer interface into a custom

    module.*/

-#include "chcore_timer_ext.h"

+#include "nilcore_timer_ext.h"

 

 #else /* !defined(PORT_DO_NOT_USE_ST) */

 

diff --git a/os/nil/ports/ARMCMx/nilcore_v6m.c b/os/nil/ports/ARMCMx/nilcore_v6m.c
index 78e796087..d8772ca54 100644
--- a/os/nil/ports/ARMCMx/nilcore_v6m.c
+++ b/os/nil/ports/ARMCMx/nilcore_v6m.c
@@ -19,14 +19,14 @@
 */

 

 /**

- * @file    ARMCMx/chcore_v6m.c

+ * @file    ARMCMx/nilcore_v6m.c

  * @brief   ARMv6-M architecture port code.

  *

  * @addtogroup ARMCMx_V6M_CORE

  * @{

  */

 

-#include "ch.h"

+#include "nil.h"

 

 /*===========================================================================*/

 /* Module local definitions.                                                 */

@@ -124,17 +124,8 @@ void _port_irq_epilogue(regarm_t lr) {
     /* Setting up a fake XPSR register value.*/

     ctxp->xpsr = (regarm_t)0x01000000;

 

-    /* The exit sequence is different depending on if a preemption is

-       required or not.*/

-    if (chSchIsPreemptionRequired()) {

-      /* Preemption is required we need to enforce a context switch.*/

-      ctxp->pc = (void *)_port_switch_from_isr;

-    }

-    else {

-      /* Preemption not required, we just need to exit the exception

-         atomically.*/

-      ctxp->pc = (void *)_port_exit_from_isr;

-    }

+    /* The context switch is handled outside the ISR context..*/

+    ctxp->pc = (regarm_t)_port_switch_from_isr;

 

     /* Note, returning without unlocking is intentional, this is done in

        order to keep the rest of the context switch atomic.*/