MISRA fixes on NIL.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7751 35acf78f-673a-0410-8e92-d51de3d6d3f4

4 files changed, 93 insertions, 86 deletions

diff --git a/os/nil/ports/ARMCMx/compilers/GCC/niltypes.h b/os/nil/ports/ARMCMx/compilers/GCC/niltypes.h
index b2e141c6f..402110096 100644
--- a/os/nil/ports/ARMCMx/compilers/GCC/niltypes.h
+++ b/os/nil/ports/ARMCMx/compilers/GCC/niltypes.h
@@ -46,7 +46,7 @@
  * @brief   Generic 'true' boolean constant.

  */

 #if !defined(TRUE) || defined(__DOXYGEN__)

-#define TRUE                    (!FALSE)

+#define TRUE                    1

 #endif

 /** @} */

 

diff --git a/os/nil/ports/ARMCMx/nilcore.h b/os/nil/ports/ARMCMx/nilcore.h
index 525e00542..d2777aeee 100644
--- a/os/nil/ports/ARMCMx/nilcore.h
+++ b/os/nil/ports/ARMCMx/nilcore.h
@@ -155,7 +155,7 @@ struct port_extctx {};
 /**

  * @brief   System saved context.

  * @details This structure represents the inner stack frame during a context

- *          switching.

+ *          switch.

  */

 struct port_intctx {};

 #endif /* defined(__DOXYGEN__) */

@@ -169,7 +169,7 @@ struct port_intctx {};
 /**

  * @brief   Total priority levels.

  */

-#define CORTEX_PRIORITY_LEVELS          (1 << CORTEX_PRIORITY_BITS)

+#define CORTEX_PRIORITY_LEVELS          (1U << CORTEX_PRIORITY_BITS)

 

 /**

  * @brief   Minimum priority level.

@@ -182,7 +182,7 @@ struct port_intctx {};
  * @brief   Maximum priority level.

  * @details The maximum allowed priority level is always zero.

  */

-#define CORTEX_MAXIMUM_PRIORITY         0

+#define CORTEX_MAXIMUM_PRIORITY         0U

 

 /**

  * @brief   Priority level verification macro.

@@ -200,7 +200,7 @@ struct port_intctx {};
  * @brief   Priority level to priority mask conversion macro.

  */

 #define CORTEX_PRIO_MASK(n)                                                 \

-  ((n) << (8 - CORTEX_PRIORITY_BITS))

+  ((n) << (8U - (unsigned)CORTEX_PRIORITY_BITS))

 

 /*===========================================================================*/

 /* External declarations.                                                    */

@@ -221,11 +221,11 @@ struct port_intctx {};
 #if !defined(_FROM_ASM_)

 

 #if NIL_CFG_ST_TIMEDELTA > 0

-#if !PORT_USE_ALT_TIMER

+#if PORT_USE_ALT_TIMER == FALSE

 #include "nilcore_timer.h"

-#else /* PORT_USE_ALT_TIMER */

+#else /* PORT_USE_ALT_TIMER != FALSE */

 #include "nilcore_timer_alt.h"

-#endif /* PORT_USE_ALT_TIMER */

+#endif /* PORT_USE_ALT_TIMER != FALSE */

 #endif /* NIL_CFG_ST_TIMEDELTA > 0 */

 

 #endif /* !defined(_FROM_ASM_) */

diff --git a/os/nil/ports/ARMCMx/nilcore_v7m.c b/os/nil/ports/ARMCMx/nilcore_v7m.c
index 74851c64f..beb9dc393 100644
--- a/os/nil/ports/ARMCMx/nilcore_v7m.c
+++ b/os/nil/ports/ARMCMx/nilcore_v7m.c
@@ -51,17 +51,19 @@
 /* Module interrupt handlers.                                                */

 /*===========================================================================*/

 

-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)

+#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__)

 /**

  * @brief   SVC vector.

  * @details The SVC vector is used for exception mode re-entering after a

  *          context switch.

  * @note    The PendSV vector is only used in advanced kernel mode.

  */

+/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/

 void SVC_Handler(void) {

+/*lint -restore*/

   struct port_extctx *ctxp;

 

-#if CORTEX_USE_FPU

+#if CORTEX_USE_FPU == TRUE

   /* Enforcing unstacking of the FP part of the context.*/

   SCB_FPCCR &= ~FPCCR_LSPACT;

 #endif

@@ -79,19 +81,21 @@ void SVC_Handler(void) {
   /* Restoring the normal interrupts status.*/

   port_unlock_from_isr();

 }

-#endif /* !CORTEX_SIMPLIFIED_PRIORITY */

+#endif /* CORTEX_SIMPLIFIED_PRIORITY == FALSE */

 

-#if CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)

+#if (CORTEX_SIMPLIFIED_PRIORITY == TRUE) || defined(__DOXYGEN__)

 /**

  * @brief   PendSV vector.

  * @details The PendSV vector is used for exception mode re-entering after a

  *          context switch.

  * @note    The PendSV vector is only used in compact kernel mode.

  */

+/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/

 void PendSV_Handler(void) {

+/*lint -restore*/

   struct port_extctx *ctxp;

 

-#if CORTEX_USE_FPU

+#if CORTEX_USE_FPU == TRUE

   /* Enforcing unstacking of the FP part of the context.*/

   SCB_FPCCR &= ~FPCCR_LSPACT;

 #endif

@@ -106,7 +110,7 @@ void PendSV_Handler(void) {
   /* Writing back the modified PSP value.*/

   __set_PSP((uint32_t)ctxp);

 }

-#endif /* CORTEX_SIMPLIFIED_PRIORITY */

+#endif /* CORTEX_SIMPLIFIED_PRIORITY == TRUE */

 

 /*===========================================================================*/

 /* Module exported functions.                                                */

@@ -118,10 +122,10 @@ void PendSV_Handler(void) {
 void _port_irq_epilogue(void) {

 

   port_lock_from_isr();

-  if ((SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) != 0) {

+  if ((SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) != 0U) {

     struct port_extctx *ctxp;

 

-#if CORTEX_USE_FPU

+#if CORTEX_USE_FPU == TRUE

       /* Enforcing a lazy FPU state save by accessing the FPCSR register.*/

       (void) __get_FPSCR();

 #endif

diff --git a/os/nil/ports/ARMCMx/nilcore_v7m.h b/os/nil/ports/ARMCMx/nilcore_v7m.h
index 55cdbb5a5..4a92fd704 100644
--- a/os/nil/ports/ARMCMx/nilcore_v7m.h
+++ b/os/nil/ports/ARMCMx/nilcore_v7m.h
@@ -25,54 +25,14 @@
  * @{

  */

 

-#ifndef _CHCORE_V7M_H_

-#define _CHCORE_V7M_H_

+#ifndef _NILCORE_V7M_H_

+#define _NILCORE_V7M_H_

 

 /*===========================================================================*/

 /* Module constants.                                                         */

 /*===========================================================================*/

 

 /**

- * @name    Architecture and Compiler

- * @{

- */

-#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)

-/**

- * @brief   Macro defining the specific ARM architecture.

- */

-#define PORT_ARCHITECTURE_ARM_v7M

-

-/**

- * @brief   Name of the implemented architecture.

- */

-#define PORT_ARCHITECTURE_NAME          "ARMv7-M"

-

-/**

- * @brief   Name of the architecture variant.

- */

-#define PORT_CORE_VARIANT_NAME          "Cortex-M3"

-

-#elif (CORTEX_MODEL == CORTEX_M4)

-#define PORT_ARCHITECTURE_ARM_v7ME

-#define PORT_ARCHITECTURE_NAME          "ARMv7-ME"

-#if CORTEX_USE_FPU

-#define PORT_CORE_VARIANT_NAME          "Cortex-M4F"

-#else

-#define PORT_CORE_VARIANT_NAME          "Cortex-M4"

-#endif

-#endif

-

-/**

- * @brief   Port-specific information string.

- */

-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)

-#define PORT_INFO                       "Advanced kernel mode"

-#else

-#define PORT_INFO                       "Compact kernel mode"

-#endif

-/** @} */

-

-/**

  * @brief   This port supports a realtime counter.

  */

 #define PORT_SUPPORTS_RT                FALSE //TRUE

@@ -80,7 +40,7 @@
 /**

  * @brief   Disabled value for BASEPRI register.

  */

-#define CORTEX_BASEPRI_DISABLED         0

+#define CORTEX_BASEPRI_DISABLED         0U

 

 /*===========================================================================*/

 /* Module pre-compile time settings.                                         */

@@ -125,7 +85,7 @@
  */

 #if !defined(CORTEX_USE_FPU)

 #define CORTEX_USE_FPU                  CORTEX_HAS_FPU

-#elif CORTEX_USE_FPU && !CORTEX_HAS_FPU

+#elif (CORTEX_USE_FPU == TRUE) && (CORTEX_HAS_FPU == FALSE)

 /* This setting requires an FPU presence check in case it is externally

    redefined.*/

 #error "the selected core does not have an FPU"

@@ -149,7 +109,7 @@
  *          priority level.

  */

 #if !defined(CORTEX_PRIORITY_SVCALL)

-#define CORTEX_PRIORITY_SVCALL          (CORTEX_MAXIMUM_PRIORITY + 1)

+#define CORTEX_PRIORITY_SVCALL          (CORTEX_MAXIMUM_PRIORITY + 1U)

 #elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL)

 /* If it is externally redefined then better perform a validity check on it.*/

 #error "invalid priority level specified for CORTEX_PRIORITY_SVCALL"

@@ -159,7 +119,7 @@
  * @brief   NVIC VTOR initialization expression.

  */

 #if !defined(CORTEX_VTOR_INIT) || defined(__DOXYGEN__)

-#define CORTEX_VTOR_INIT                0x00000000

+#define CORTEX_VTOR_INIT                0x00000000U

 #endif

 

 /**

@@ -175,11 +135,51 @@
 /* Derived constants and error checks.                                       */

 /*===========================================================================*/

 

-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)

+/**

+ * @name    Architecture and Compiler

+ * @{

+ */

+#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)

+/**

+ * @brief   Macro defining the specific ARM architecture.

+ */

+#define PORT_ARCHITECTURE_ARM_v7M

+

+/**

+ * @brief   Name of the implemented architecture.

+ */

+#define PORT_ARCHITECTURE_NAME          "ARMv7-M"

+

+/**

+ * @brief   Name of the architecture variant.

+ */

+#define PORT_CORE_VARIANT_NAME          "Cortex-M3"

+

+#elif (CORTEX_MODEL == CORTEX_M4)

+#define PORT_ARCHITECTURE_ARM_v7ME

+#define PORT_ARCHITECTURE_NAME          "ARMv7-ME"

+#if CORTEX_USE_FPU

+#define PORT_CORE_VARIANT_NAME          "Cortex-M4F"

+#else

+#define PORT_CORE_VARIANT_NAME          "Cortex-M4"

+#endif

+#endif

+

+/**

+ * @brief   Port-specific information string.

+ */

+#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__)

+#define PORT_INFO                       "Advanced kernel mode"

+#else

+#define PORT_INFO                       "Compact kernel mode"

+#endif

+/** @} */

+

+#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__)

 /**

  * @brief   Maximum usable priority for normal ISRs.

  */

-#define CORTEX_MAX_KERNEL_PRIORITY      (CORTEX_PRIORITY_SVCALL + 1)

+#define CORTEX_MAX_KERNEL_PRIORITY      (CORTEX_PRIORITY_SVCALL + 1U)

 

 /**

  * @brief   BASEPRI level within kernel lock.

@@ -188,7 +188,7 @@
   CORTEX_PRIO_MASK(CORTEX_MAX_KERNEL_PRIORITY)

 #else

 

-#define CORTEX_MAX_KERNEL_PRIORITY      0

+#define CORTEX_MAX_KERNEL_PRIORITY      0U

 #endif

 

 /**

@@ -277,16 +277,18 @@ struct port_intctx {
 /*===========================================================================*/

 

 /**

- * @brief   Platform dependent thread stack setup.

+ * @brief   Platform dependent part of the @p chThdCreateI() API.

  * @details This code usually setup the context switching frame represented

  *          by an @p port_intctx structure.

  */

 #define PORT_SETUP_CONTEXT(tp, wend, pf, arg) {                             \

-  (tp)->ctxp = (struct port_intctx *)(((uint8_t *)(wend)) -                 \

+  /*lint -save -e611 -e9074 -e9087 [11.1, 11.3] Casts are planned here.*/   \

+  (tp)->ctxp = (struct port_intctx *)((uint8_t *)(wend) -                   \

                                       sizeof(struct port_intctx));          \

   (tp)->ctxp->r4 = (regarm_t)(pf);                                          \

   (tp)->ctxp->r5 = (regarm_t)(arg);                                         \

   (tp)->ctxp->lr = (regarm_t)(_port_thread_start);                          \

+  /*lint -restore*/                                                         \

 }

 

 /**

@@ -295,7 +297,7 @@ struct port_intctx {
  */

 #define PORT_WA_SIZE(n) (sizeof(struct port_intctx) +                       \

                          sizeof(struct port_extctx) +                       \

-                         (n) + (PORT_INT_REQUIRED_STACK))

+                         ((size_t)(n)) + ((size_t)(PORT_INT_REQUIRED_STACK)))

 

 /**

  * @brief   IRQ prologue code.

@@ -335,13 +337,14 @@ struct port_intctx {
  * @param[in] ntp       the thread to be switched in

  * @param[in] otp       the thread to be switched out

  */

-#if !NIL_CFG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)

+#if (NIL_CFG_ENABLE_STACK_CHECK == FALSE) || defined(__DOXYGEN__)

 #define port_switch(ntp, otp) _port_switch(ntp, otp)

 #else

 #define port_switch(ntp, otp) {                                             \

   struct port_intctx *r13 = (struct port_intctx *)__get_PSP();              \

-  if ((stkalign_t *)(r13 - 1) < (otp)->stklim)                              \

+  if ((stkalign_t *)(r13 - 1) < (otp)->stklim) {                            \

     chSysHalt("stack overflow");                                            \

+  }                                                                         \

   _port_switch(ntp, otp);                                                   \

 }

 #endif

@@ -382,7 +385,7 @@ static inline void port_init(void) {
   DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;

 

   /* Initialization of the system vectors used by the port.*/

-#if !CORTEX_SIMPLIFIED_PRIORITY

+#if CORTEX_SIMPLIFIED_PRIORITY == FALSE

   NVIC_SetPriority(SVCall_IRQn, CORTEX_PRIORITY_SVCALL);

 #endif

   NVIC_SetPriority(PendSV_IRQn, CORTEX_PRIORITY_PENDSV);

@@ -394,12 +397,12 @@ static inline void port_init(void) {
  * @return              The interrupts status.

  */

 static inline syssts_t port_get_irq_status(void) {

-  register uint32_t sts;

+  syssts_t sts;

 

-#if !CORTEX_SIMPLIFIED_PRIORITY

-  sts = __get_BASEPRI();

+#if CORTEX_SIMPLIFIED_PRIORITY == FALSE

+  sts = (syssts_t)__get_BASEPRI();

 #else /* CORTEX_SIMPLIFIED_PRIORITY */

-  sts = __get_PRIMASK();

+  sts = (syssts_t)__get_PRIMASK();

 #endif /* CORTEX_SIMPLIFIED_PRIORITY */

   return sts;

 }

@@ -415,10 +418,10 @@ static inline syssts_t port_get_irq_status(void) {
  */

 static inline bool port_irq_enabled(syssts_t sts) {

 

-#if !CORTEX_SIMPLIFIED_PRIORITY

-  return sts == CORTEX_BASEPRI_DISABLED;

+#if CORTEX_SIMPLIFIED_PRIORITY == FALSE

+  return sts == (syssts_t)CORTEX_BASEPRI_DISABLED;

 #else /* CORTEX_SIMPLIFIED_PRIORITY */

-  return (sts & 1) == 0;

+  return (sts & (syssts_t)1) == (syssts_t)0;

 #endif /* CORTEX_SIMPLIFIED_PRIORITY */

 }

 

@@ -431,7 +434,7 @@ static inline bool port_irq_enabled(syssts_t sts) {
  */

 static inline bool port_is_isr_context(void) {

 

-  return (bool)((__get_IPSR() & 0x1FF) != 0);

+  return (bool)((__get_IPSR() & 0x1FFU) != 0U);

 }

 

 /**

@@ -441,7 +444,7 @@ static inline bool port_is_isr_context(void) {
  */

 static inline void port_lock(void) {

 

-#if !CORTEX_SIMPLIFIED_PRIORITY

+#if CORTEX_SIMPLIFIED_PRIORITY == FALSE

   __set_BASEPRI(CORTEX_BASEPRI_KERNEL);

 #else /* CORTEX_SIMPLIFIED_PRIORITY */

   __disable_irq();

@@ -455,7 +458,7 @@ static inline void port_lock(void) {
  */

 static inline void port_unlock(void) {

 

-#if !CORTEX_SIMPLIFIED_PRIORITY

+#if CORTEX_SIMPLIFIED_PRIORITY == FALSE

   __set_BASEPRI(CORTEX_BASEPRI_DISABLED);

 #else /* CORTEX_SIMPLIFIED_PRIORITY */

   __enable_irq();

@@ -501,7 +504,7 @@ static inline void port_disable(void) {
  */

 static inline void port_suspend(void) {

 

-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)

+#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__)

   __set_BASEPRI(CORTEX_BASEPRI_KERNEL);

   __enable_irq();

 #else

@@ -515,7 +518,7 @@ static inline void port_suspend(void) {
  */

 static inline void port_enable(void) {

 

-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)

+#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__)

   __set_BASEPRI(CORTEX_BASEPRI_DISABLED);

 #endif

   __enable_irq();

@@ -531,8 +534,8 @@ static inline void port_enable(void) {
  */

 static inline void port_wait_for_interrupt(void) {

 

-#if CORTEX_ENABLE_WFI_IDLE

-  __WFI;

+#if CORTEX_ENABLE_WFI_IDLE == TRUE

+  __WFI();

 #endif

 }

 

@@ -548,6 +551,6 @@ static inline rtcnt_t port_rt_get_counter_value(void) {
 

 #endif /* !defined(_FROM_ASM_) */

 

-#endif /* _CHCORE_V7M_H_ */

+#endif /* _NILCORE_V7M_H_ */

 

 /** @} */