git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6263 35acf78f-673a-0410-8e92-d51de3d6d3f4

3 files changed, 136 insertions, 2 deletions

diff --git a/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk
new file mode 100644
index 000000000..18df7e0a9
--- /dev/null
+++ b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk
@@ -0,0 +1,15 @@
+# List of the ChibiOS/NIL Cortex-M4 STM32F30x port files.

+PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \

+          $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \

+          ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore.c \

+          ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore_v7m.c

+          

+PORTASM = $(CHIBIOS)/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v7m.s

+

+PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \

+          ${CHIBIOS}/os/ext/CMSIS/ST \

+          ${CHIBIOS}/os/common/ports/ARMCMx/devices/STM32F30x \

+          ${CHIBIOS}/os/nil/ports/ARMCMx \

+          ${CHIBIOS}/os/nil/ports/ARMCMx/compilers/GCC

+

+PORTLD  = ${CHIBIOS}/os/common/ports/ARMCMx/compilers/GCC/ld

diff --git a/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v6m.s b/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v6m.s
index 8112d9802..1c1a39067 100644
--- a/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v6m.s
+++ b/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v6m.s
@@ -18,7 +18,7 @@
 */

 

 /**

- * @file    ARMCMx/GCC/nilcoreasm_v6m.s

+ * @file    nilcoreasm_v6m.s

  * @brief   ARMv6-M architecture port low level code.

  *

  * @addtogroup ARMCMx_CORE

@@ -39,7 +39,6 @@
 

 #if !defined(__DOXYGEN__)

 

-

                 .set    CONTEXT_OFFSET, 0

                 .set    SCB_ICSR, 0xE000ED04

                 .set    ICSR_PENDSVSET, 0x10000000

diff --git a/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v7m.s b/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v7m.s
new file mode 100644
index 000000000..97d15e5d8
--- /dev/null
+++ b/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v7m.s
@@ -0,0 +1,120 @@
+/*

+    ChibiOS/NIL - Copyright (C) 2012,2013 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/NIL.

+

+    ChibiOS/NIL is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/NIL is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/**

+ * @file    nilcoreasm_v7m.s

+ * @brief   ARMv7-M architecture port low level code.

+ *

+ * @addtogroup ARMCMx_CORE

+ * @{

+ */

+

+#define _FROM_ASM_

+#include "nilconf.h"

+#include "nilcore.h"

+

+#if !defined(FALSE) || defined(__DOXYGEN__)

+#define FALSE   0

+#endif

+

+#if !defined(TRUE) || defined(__DOXYGEN__)

+#define TRUE    1

+#endif

+

+#if !defined(__DOXYGEN__)

+

+                .set    CONTEXT_OFFSET, 0

+                .set    SCB_ICSR, 0xE000ED04

+                .set    ICSR_PENDSVSET, 0x10000000

+

+                .syntax unified

+                .cpu    cortex-m4

+#if CORTEX_USE_FPU

+                .fpu    fpv4-sp-d16

+#else

+                .fpu    softvfp

+#endif

+

+                .thumb

+                .text

+

+/*--------------------------------------------------------------------------*

+ * Performs a context switch between two threads.

+ *--------------------------------------------------------------------------*/

+                .thumb_func

+                .globl  _port_switch

+_port_switch:

+                push    {r4, r5, r6, r7, r8, r9, r10, r11, lr}

+#if CORTEX_USE_FPU

+                vpush   {s16-s31}

+#endif

+                str     sp, [r1, #CONTEXT_OFFSET]

+                ldr     sp, [r0, #CONTEXT_OFFSET]

+#if CORTEX_USE_FPU

+                vpop    {s16-s31}

+#endif

+                pop     {r4, r5, r6, r7, r8, r9, r10, r11, pc}

+

+/*--------------------------------------------------------------------------*

+ * Start a thread by invoking its work function.

+ *

+ * Threads execution starts here, the code leaves the system critical zone

+ * and then jumps into the thread function passed in register R4. The

+ * register R5 contains the thread parameter. The function chThdExit() is

+ * called on thread function return.

+ *--------------------------------------------------------------------------*/

+                .thumb_func

+                .globl  _port_thread_start

+_port_thread_start:

+#if !CORTEX_SIMPLIFIED_PRIORITY

+                movs    r3, #0

+                msr     BASEPRI, r3

+#else /* CORTEX_SIMPLIFIED_PRIORITY */

+                cpsie   i

+#endif /* CORTEX_SIMPLIFIED_PRIORITY */

+                mov     r0, r5

+                blx     r4

+                mov     r3, #0

+                bl      chSysHalt

+

+/*--------------------------------------------------------------------------*

+ * Post-IRQ switch code.

+ *

+ * Exception handlers return here for context switching.

+ *--------------------------------------------------------------------------*/

+                .thumb_func

+                .globl  _port_switch_from_isr

+_port_switch_from_isr:

+                bl      chSchRescheduleS

+                .globl  _port_exit_from_isr

+_port_exit_from_isr:

+#if CORTEX_SIMPLIFIED_PRIORITY

+                movw    r3, #:lower16:SCB_ICSR

+                movt    r3, #:upper16:SCB_ICSR

+                mov     r2, ICSR_PENDSVSET

+                str     r2, [r3, #0]

+                cpsie   i

+#else /* !CORTEX_SIMPLIFIED_PRIORITY */

+                svc     #0

+#endif /* !CORTEX_SIMPLIFIED_PRIORITY */

+.L1:            b       .L1

+

+#endif /* !defined(__DOXYGEN__) */

+

+/** @} */