git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6199 35acf78f-673a-0410-8e92-d51de3d6d3f4

10 files changed, 324 insertions, 391 deletions

diff --git a/os/hal/boards/ST_STM32F4_DISCOVERY/board.c b/os/hal/boards/ST_STM32F4_DISCOVERY/board.c
index 99569f695..c76d97d55 100644
--- a/os/hal/boards/ST_STM32F4_DISCOVERY/board.c
+++ b/os/hal/boards/ST_STM32F4_DISCOVERY/board.c
@@ -14,7 +14,6 @@
     limitations under the License.

 */

 

-#include "ch.h"

 #include "hal.h"

 

 #if HAL_USE_PAL || defined(__DOXYGEN__)

diff --git a/os/hal/boards/ST_STM32F4_DISCOVERY/board.h b/os/hal/boards/ST_STM32F4_DISCOVERY/board.h
index 6e636db9e..85afb6de5 100644
--- a/os/hal/boards/ST_STM32F4_DISCOVERY/board.h
+++ b/os/hal/boards/ST_STM32F4_DISCOVERY/board.h
@@ -50,7 +50,7 @@
 /*

  * MCU type as defined in the ST header file stm32f4xx.h.

  */

-#define STM32F4XX

+#define STM32F40XX

 

 /*

  * IO pins assignments.

diff --git a/os/hal/boards/ST_STM32F4_DISCOVERY/board.mk b/os/hal/boards/ST_STM32F4_DISCOVERY/board.mk
index eb47aa2af..0c11b6fe3 100644
--- a/os/hal/boards/ST_STM32F4_DISCOVERY/board.mk
+++ b/os/hal/boards/ST_STM32F4_DISCOVERY/board.mk
@@ -1,5 +1,5 @@
 # List of all the board related files.

-BOARDSRC = ${CHIBIOS}/boards/ST_STM32F4_DISCOVERY/board.c

+BOARDSRC = ${CHIBIOS}/os/hal/boards/ST_STM32F4_DISCOVERY/board.c

 

 # Required include directories

-BOARDINC = ${CHIBIOS}/boards/ST_STM32F4_DISCOVERY

+BOARDINC = ${CHIBIOS}/os/hal/boards/ST_STM32F4_DISCOVERY

diff --git a/os/hal/platforms/STM32/USARTv1/serial_lld.c b/os/hal/platforms/STM32/USARTv1/serial_lld.c
index a8333bf77..ae6042a8d 100644
--- a/os/hal/platforms/STM32/USARTv1/serial_lld.c
+++ b/os/hal/platforms/STM32/USARTv1/serial_lld.c
@@ -22,7 +22,6 @@
  * @{

  */

 

-#include "ch.h"

 #include "hal.h"

 

 #if HAL_USE_SERIAL || defined(__DOXYGEN__)

@@ -133,7 +132,7 @@ static void usart_deinit(USART_TypeDef *u) {
  * @param[in] sr        USART SR register value

  */

 static void set_error(SerialDriver *sdp, uint16_t sr) {

-  flagsmask_t sts = 0;

+  eventflags_t sts = 0;

 

   if (sr & USART_SR_ORE)

     sts |= SD_OVERRUN_ERROR;

@@ -143,9 +142,9 @@ static void set_error(SerialDriver *sdp, uint16_t sr) {
     sts |= SD_FRAMING_ERROR;

   if (sr & USART_SR_NE)

     sts |= SD_NOISE_ERROR;

-  chSysLockFromIsr();

+  osalSysLockFromISR();

   chnAddFlagsI(sdp, sts);

-  chSysUnlockFromIsr();

+  osalSysUnlockFromISR();

 }

 

 /**

@@ -164,42 +163,42 @@ static void serve_interrupt(SerialDriver *sdp) {
     set_error(sdp, sr);

   /* Special case, LIN break detection.*/

   if (sr & USART_SR_LBD) {

-    chSysLockFromIsr();

+    osalSysLockFromISR();

     chnAddFlagsI(sdp, SD_BREAK_DETECTED);

-    chSysUnlockFromIsr();

+    osalSysUnlockFromISR();

     u->SR &= ~USART_SR_LBD;

   }

   /* Data available.*/

   if (sr & USART_SR_RXNE) {

-    chSysLockFromIsr();

+    osalSysLockFromISR();

     sdIncomingDataI(sdp, (uint8_t)dr);

-    chSysUnlockFromIsr();

+    osalSysUnlockFromISR();

   }

   /* Transmission buffer empty.*/

   if ((cr1 & USART_CR1_TXEIE) && (sr & USART_SR_TXE)) {

     msg_t b;

-    chSysLockFromIsr();

-    b = chOQGetI(&sdp->oqueue);

+    osalSysLockFromISR();

+    b = oqGetI(&sdp->oqueue);

     if (b < Q_OK) {

       chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);

       u->CR1 = (cr1 & ~USART_CR1_TXEIE) | USART_CR1_TCIE;

     }

     else

       u->DR = b;

-    chSysUnlockFromIsr();

+    osalSysUnlockFromISR();

   }

   /* Physical transmission end.*/

   if (sr & USART_SR_TC) {

-    chSysLockFromIsr();

+    osalSysLockFromISR();

     chnAddFlagsI(sdp, CHN_TRANSMISSION_END);

-    chSysUnlockFromIsr();

+    osalSysUnlockFromISR();

     u->CR1 = cr1 & ~USART_CR1_TCIE;

     u->SR &= ~USART_SR_TC;

   }

 }

 

 #if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)

-static void notify1(GenericQueue *qp) {

+static void notify1(io_queue_t *qp) {

 

   (void)qp;

   USART1->CR1 |= USART_CR1_TXEIE;

@@ -207,7 +206,7 @@ static void notify1(GenericQueue *qp) {
 #endif

 

 #if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)

-static void notify2(GenericQueue *qp) {

+static void notify2(io_queue_t *qp) {

 

   (void)qp;

   USART2->CR1 |= USART_CR1_TXEIE;

@@ -215,7 +214,7 @@ static void notify2(GenericQueue *qp) {
 #endif

 

 #if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)

-static void notify3(GenericQueue *qp) {

+static void notify3(io_queue_t *qp) {

 

   (void)qp;

   USART3->CR1 |= USART_CR1_TXEIE;

@@ -223,7 +222,7 @@ static void notify3(GenericQueue *qp) {
 #endif

 

 #if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)

-static void notify4(GenericQueue *qp) {

+static void notify4(io_queue_t *qp) {

 

   (void)qp;

   UART4->CR1 |= USART_CR1_TXEIE;

@@ -231,7 +230,7 @@ static void notify4(GenericQueue *qp) {
 #endif

 

 #if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)

-static void notify5(GenericQueue *qp) {

+static void notify5(io_queue_t *qp) {

 

   (void)qp;

   UART5->CR1 |= USART_CR1_TXEIE;

@@ -239,7 +238,7 @@ static void notify5(GenericQueue *qp) {
 #endif

 

 #if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)

-static void notify6(GenericQueue *qp) {

+static void notify6(io_queue_t *qp) {

 

   (void)qp;

   USART6->CR1 |= USART_CR1_TXEIE;

@@ -259,13 +258,13 @@ static void notify6(GenericQueue *qp) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(STM32_USART1_HANDLER) {

+OSAL_IRQ_HANDLER(STM32_USART1_HANDLER) {

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   serve_interrupt(&SD1);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 #endif

 

@@ -278,13 +277,13 @@ CH_IRQ_HANDLER(STM32_USART1_HANDLER) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(STM32_USART2_HANDLER) {

+OSAL_IRQ_HANDLER(STM32_USART2_HANDLER) {

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   serve_interrupt(&SD2);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 #endif

 

@@ -297,13 +296,13 @@ CH_IRQ_HANDLER(STM32_USART2_HANDLER) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(STM32_USART3_HANDLER) {

+OSAL_IRQ_HANDLER(STM32_USART3_HANDLER) {

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   serve_interrupt(&SD3);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 #endif

 

@@ -316,13 +315,13 @@ CH_IRQ_HANDLER(STM32_USART3_HANDLER) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(STM32_UART4_HANDLER) {

+OSAL_IRQ_HANDLER(STM32_UART4_HANDLER) {

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   serve_interrupt(&SD4);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 #endif

 

@@ -335,13 +334,13 @@ CH_IRQ_HANDLER(STM32_UART4_HANDLER) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(STM32_UART5_HANDLER) {

+OSAL_IRQ_HANDLER(STM32_UART5_HANDLER) {

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   serve_interrupt(&SD5);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 #endif

 

@@ -354,13 +353,13 @@ CH_IRQ_HANDLER(STM32_UART5_HANDLER) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(STM32_USART6_HANDLER) {

+OSAL_IRQ_HANDLER(STM32_USART6_HANDLER) {

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   serve_interrupt(&SD6);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 #endif

 

@@ -425,43 +424,37 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
 #if STM32_SERIAL_USE_USART1

     if (&SD1 == sdp) {

       rccEnableUSART1(FALSE);

-      nvicEnableVector(STM32_USART1_NUMBER,

-                       CORTEX_PRIORITY_MASK(STM32_SERIAL_USART1_PRIORITY));

+      nvicEnableVector(STM32_USART1_NUMBER, STM32_SERIAL_USART1_PRIORITY);

     }

 #endif

 #if STM32_SERIAL_USE_USART2

     if (&SD2 == sdp) {

       rccEnableUSART2(FALSE);

-      nvicEnableVector(STM32_USART2_NUMBER,

-                       CORTEX_PRIORITY_MASK(STM32_SERIAL_USART2_PRIORITY));

+      nvicEnableVector(STM32_USART2_NUMBER, STM32_SERIAL_USART2_PRIORITY);

     }

 #endif

 #if STM32_SERIAL_USE_USART3

     if (&SD3 == sdp) {

       rccEnableUSART3(FALSE);

-      nvicEnableVector(STM32_USART3_NUMBER,

-                       CORTEX_PRIORITY_MASK(STM32_SERIAL_USART3_PRIORITY));

+      nvicEnableVector(STM32_USART3_NUMBER, STM32_SERIAL_USART3_PRIORITY);

     }

 #endif

 #if STM32_SERIAL_USE_UART4

     if (&SD4 == sdp) {

       rccEnableUART4(FALSE);

-      nvicEnableVector(STM32_UART4_NUMBER,

-                       CORTEX_PRIORITY_MASK(STM32_SERIAL_UART4_PRIORITY));

+      nvicEnableVector(STM32_UART4_NUMBER, STM32_SERIAL_UART4_PRIORITY);

     }

 #endif

 #if STM32_SERIAL_USE_UART5

     if (&SD5 == sdp) {

       rccEnableUART5(FALSE);

-      nvicEnableVector(STM32_UART5_NUMBER,

-                       CORTEX_PRIORITY_MASK(STM32_SERIAL_UART5_PRIORITY));

+      nvicEnableVector(STM32_UART5_NUMBER, STM32_SERIAL_UART5_PRIORITY);

     }

 #endif

 #if STM32_SERIAL_USE_USART6

     if (&SD6 == sdp) {

       rccEnableUSART6(FALSE);

-      nvicEnableVector(STM32_USART6_NUMBER,

-                       CORTEX_PRIORITY_MASK(STM32_SERIAL_USART6_PRIORITY));

+      nvicEnableVector(STM32_USART6_NUMBER, STM32_SERIAL_USART6_PRIORITY);

     }

 #endif

   }

diff --git a/os/hal/platforms/STM32/USARTv1/serial_lld.h b/os/hal/platforms/STM32/USARTv1/serial_lld.h
index 7242537d7..bdf8e9bdb 100644
--- a/os/hal/platforms/STM32/USARTv1/serial_lld.h
+++ b/os/hal/platforms/STM32/USARTv1/serial_lld.h
@@ -240,9 +240,9 @@ typedef struct {
   /* Driver state.*/                                                        \

   sdstate_t                 state;                                          \

   /* Input queue.*/                                                         \

-  InputQueue                iqueue;                                         \

+  input_queue_t             iqueue;                                         \

   /* Output queue.*/                                                        \

-  OutputQueue               oqueue;                                         \

+  output_queue_t            oqueue;                                         \

   /* Input circular buffer.*/                                               \

   uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \

   /* Output circular buffer.*/                                              \

diff --git a/os/hal/platforms/STM32/mac_lld.c b/os/hal/platforms/STM32/mac_lld.c
index c1244aa39..f766698e8 100644
--- a/os/hal/platforms/STM32/mac_lld.c
+++ b/os/hal/platforms/STM32/mac_lld.c
@@ -26,10 +26,11 @@
 

 #include "ch.h"

 #include "hal.h"

-#include "mii.h"

 

 #if HAL_USE_MAC || defined(__DOXYGEN__)

 

+#include "mii.h"

+

 /*===========================================================================*/

 /* Driver local definitions.                                                 */

 /*===========================================================================*/

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index 7ec69c5f7..e414043cc 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -110,17 +110,6 @@ void hal_lld_init(void) {
   rccResetAPB1(~RCC_APB1RSTR_PWRRST);

   rccResetAPB2(~0);

 

-  /* SysTick initialization using the system clock.*/

-  SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;

-  SysTick->VAL = 0;

-  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |

-                  SysTick_CTRL_ENABLE_Msk |

-                  SysTick_CTRL_TICKINT_Msk;

-

-  /* DWT cycle counter enable.*/

-  SCS_DEMCR |= SCS_DEMCR_TRCENA;

-  DWT_CTRL  |= DWT_CTRL_CYCCNTENA;

-

   /* PWR clock enabled.*/

   rccEnablePWRInterface(FALSE);

 

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h
index 0a7291420..ae5378c23 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.h
+++ b/os/hal/platforms/STM32F4xx/hal_lld.h
@@ -37,6 +37,7 @@
 #define _HAL_LLD_H_

 

 #include "stm32.h"

+#include "stm32_registry.h"

 

 /*===========================================================================*/

 /* Driver constants.                                                         */

@@ -280,294 +281,6 @@
 /** @} */

 

 /*===========================================================================*/

-/* Platform capabilities.                                                    */

-/*===========================================================================*/

-

-/**

- * @name    STM32F4xx capabilities

- * @{

- */

-/* ADC attributes.*/

-#define STM32_HAS_ADC1          TRUE

-#define STM32_ADC1_DMA_MSK      (STM32_DMA_STREAM_ID_MSK(2, 0) |            \

-                                 STM32_DMA_STREAM_ID_MSK(2, 4))

-#define STM32_ADC1_DMA_CHN      0x00000000

-

-#define STM32_HAS_ADC2          TRUE

-#define STM32_ADC2_DMA_MSK      (STM32_DMA_STREAM_ID_MSK(2, 2) |            \

-                                 STM32_DMA_STREAM_ID_MSK(2, 3))

-#define STM32_ADC2_DMA_CHN      0x00001100

-

-#define STM32_HAS_ADC3          TRUE

-#define STM32_ADC3_DMA_MSK      (STM32_DMA_STREAM_ID_MSK(2, 0) |            \

-                                 STM32_DMA_STREAM_ID_MSK(2, 1))

-#define STM32_ADC3_DMA_CHN      0x00000022

-

-#define STM32_HAS_ADC4          FALSE

-#define STM32_ADC4_DMA_MSK      0x00000000

-#define STM32_ADC4_DMA_CHN      0x00000000

-

-/* CAN attributes.*/

-#define STM32_HAS_CAN1          TRUE

-#define STM32_HAS_CAN2          TRUE

-#define STM32_CAN_MAX_FILTERS   28

-

-/* DAC attributes.*/

-#define STM32_HAS_DAC           TRUE

-

-/* DMA attributes.*/

-#define STM32_ADVANCED_DMA      TRUE

-#define STM32_HAS_DMA1          TRUE

-#define STM32_HAS_DMA2          TRUE

-

-/* ETH attributes.*/

-#define STM32_HAS_ETH           TRUE

-

-/* EXTI attributes.*/

-#define STM32_EXTI_NUM_CHANNELS 23

-

-/* GPIO attributes.*/

-#define STM32_HAS_GPIOA         TRUE

-#define STM32_HAS_GPIOB         TRUE

-#define STM32_HAS_GPIOC         TRUE

-#define STM32_HAS_GPIOD         TRUE

-#define STM32_HAS_GPIOE         TRUE

-#define STM32_HAS_GPIOF         TRUE

-#define STM32_HAS_GPIOG         TRUE

-#define STM32_HAS_GPIOH         TRUE

-#define STM32_HAS_GPIOI         TRUE

-

-/* I2C attributes.*/

-#define STM32_HAS_I2C1          TRUE

-#define STM32_I2C1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 0) |            \

-                                 STM32_DMA_STREAM_ID_MSK(1, 5))

-#define STM32_I2C1_RX_DMA_CHN   0x00100001

-#define STM32_I2C1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 7)) |           \

-                                 (STM32_DMA_STREAM_ID_MSK(1, 6))

-#define STM32_I2C1_TX_DMA_CHN   0x11000000

-

-#define STM32_HAS_I2C2          TRUE

-#define STM32_I2C2_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 2) |            \

-                                 STM32_DMA_STREAM_ID_MSK(1, 3))

-#define STM32_I2C2_RX_DMA_CHN   0x00007700

-#define STM32_I2C2_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 7))

-#define STM32_I2C2_TX_DMA_CHN   0x70000000

-

-#define STM32_HAS_I2C3          TRUE

-#define STM32_I2C3_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 2))

-#define STM32_I2C3_RX_DMA_CHN   0x00000300

-#define STM32_I2C3_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 4))

-#define STM32_I2C3_TX_DMA_CHN   0x00030000

-

-/* RTC attributes.*/

-#define STM32_HAS_RTC           TRUE

-#if defined(STM32F4XX) || defined(__DOXYGEN__)

-#define STM32_RTC_HAS_SUBSECONDS TRUE

-#else

-#define STM32_RTC_HAS_SUBSECONDS FALSE

-#endif

-#define STM32_RTC_IS_CALENDAR   TRUE

-

-/* SDIO attributes.*/

-#define STM32_HAS_SDIO          TRUE

-#define STM32_SDC_SDIO_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(2, 3) |            \

-                                 STM32_DMA_STREAM_ID_MSK(2, 6))

-#define STM32_SDC_SDIO_DMA_CHN  0x04004000

-

-/* SPI attributes.*/

-#define STM32_HAS_SPI1          TRUE

-#define STM32_SPI1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(2, 0) |            \

-                                 STM32_DMA_STREAM_ID_MSK(2, 2))

-#define STM32_SPI1_RX_DMA_CHN   0x00000303

-#define STM32_SPI1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(2, 3) |            \

-                                 STM32_DMA_STREAM_ID_MSK(2, 5))

-#define STM32_SPI1_TX_DMA_CHN   0x00303000

-

-#define STM32_HAS_SPI2          TRUE

-#define STM32_SPI2_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 3))

-#define STM32_SPI2_RX_DMA_CHN   0x00000000

-#define STM32_SPI2_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 4))

-#define STM32_SPI2_TX_DMA_CHN   0x00000000

-

-#define STM32_HAS_SPI3          TRUE

-#define STM32_SPI3_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 0) |            \

-                                 STM32_DMA_STREAM_ID_MSK(1, 2))

-#define STM32_SPI3_RX_DMA_CHN   0x00000000

-#define STM32_SPI3_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 5) |            \

-                                 STM32_DMA_STREAM_ID_MSK(1, 7))

-#define STM32_SPI3_TX_DMA_CHN   0x00000000

-

-/* TIM attributes.*/

-#define STM32_HAS_TIM1          TRUE

-#define STM32_HAS_TIM2          TRUE

-#define STM32_HAS_TIM3          TRUE

-#define STM32_HAS_TIM4          TRUE

-#define STM32_HAS_TIM5          TRUE

-#define STM32_HAS_TIM6          TRUE

-#define STM32_HAS_TIM7          TRUE

-#define STM32_HAS_TIM8          TRUE

-#define STM32_HAS_TIM9          TRUE

-#define STM32_HAS_TIM10         TRUE

-#define STM32_HAS_TIM11         TRUE

-#define STM32_HAS_TIM12         TRUE

-#define STM32_HAS_TIM13         TRUE

-#define STM32_HAS_TIM14         TRUE

-#define STM32_HAS_TIM15         FALSE

-#define STM32_HAS_TIM16         FALSE

-#define STM32_HAS_TIM17         FALSE

-#define STM32_HAS_TIM18         FALSE

-#define STM32_HAS_TIM19         FALSE

-

-/* USART attributes.*/

-#define STM32_HAS_USART1        TRUE

-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |            \

-                                 STM32_DMA_STREAM_ID_MSK(2, 5))

-#define STM32_USART1_RX_DMA_CHN 0x00400400

-#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 7))

-#define STM32_USART1_TX_DMA_CHN 0x40000000

-

-#define STM32_HAS_USART2        TRUE

-#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))

-#define STM32_USART2_RX_DMA_CHN 0x00400000

-#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))

-#define STM32_USART2_TX_DMA_CHN 0x04000000

-

-#define STM32_HAS_USART3        TRUE

-#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))

-#define STM32_USART3_RX_DMA_CHN 0x00000040

-#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |            \

-                                 STM32_DMA_STREAM_ID_MSK(1, 4))

-#define STM32_USART3_TX_DMA_CHN 0x00074000

-

-#define STM32_HAS_UART4         TRUE

-#define STM32_UART4_RX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(1, 2))

-#define STM32_UART4_RX_DMA_CHN  0x00000400

-#define STM32_UART4_TX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(1, 4))

-#define STM32_UART4_TX_DMA_CHN  0x00040000

-

-#define STM32_HAS_UART5         TRUE

-#define STM32_UART5_RX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(1, 0))

-#define STM32_UART5_RX_DMA_CHN  0x00000004

-#define STM32_UART5_TX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(1, 7))

-#define STM32_UART5_TX_DMA_CHN  0x40000000

-

-#define STM32_HAS_USART6        TRUE

-#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |            \

-                                 STM32_DMA_STREAM_ID_MSK(2, 2))

-#define STM32_USART6_RX_DMA_CHN 0x00000550

-#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |            \

-                                 STM32_DMA_STREAM_ID_MSK(2, 7))

-#define STM32_USART6_TX_DMA_CHN 0x55000000

-

-/* USB attributes.*/

-#define STM32_HAS_USB           FALSE

-#define STM32_HAS_OTG1          TRUE

-#define STM32_HAS_OTG2          TRUE

-/** @} */

-

-/*===========================================================================*/

-/* Platform specific friendly IRQ names.                                     */

-/*===========================================================================*/

-

-/**

- * @name    IRQ VECTOR names

- * @{

- */

-#define WWDG_IRQHandler         Vector40    /**< Window Watchdog.           */

-#define PVD_IRQHandler          Vector44    /**< PVD through EXTI Line

-                                                 detect.                    */

-#define TAMP_STAMP_IRQHandler   Vector48    /**< Tamper and TimeStamp

-                                                 through EXTI Line.         */

-#define RTC_WKUP_IRQHandler     Vector4C    /**< RTC wakeup EXTI Line.      */

-#define FLASH_IRQHandler        Vector50    /**< Flash.                     */

-#define RCC_IRQHandler          Vector54    /**< RCC.                       */

-#define EXTI0_IRQHandler        Vector58    /**< EXTI Line 0.               */

-#define EXTI1_IRQHandler        Vector5C    /**< EXTI Line 1.               */

-#define EXTI2_IRQHandler        Vector60    /**< EXTI Line 2.               */

-#define EXTI3_IRQHandler        Vector64    /**< EXTI Line 3.               */

-#define EXTI4_IRQHandler        Vector68    /**< EXTI Line 4.               */

-#define DMA1_Stream0_IRQHandler Vector6C    /**< DMA1 Stream 0.             */

-#define DMA1_Stream1_IRQHandler Vector70    /**< DMA1 Stream 1.             */

-#define DMA1_Stream2_IRQHandler Vector74    /**< DMA1 Stream 2.             */

-#define DMA1_Stream3_IRQHandler Vector78    /**< DMA1 Stream 3.             */

-#define DMA1_Stream4_IRQHandler Vector7C    /**< DMA1 Stream 4.             */

-#define DMA1_Stream5_IRQHandler Vector80    /**< DMA1 Stream 5.             */

-#define DMA1_Stream6_IRQHandler Vector84    /**< DMA1 Stream 6.             */

-#define ADC1_2_3_IRQHandler     Vector88    /**< ADC1, ADC2 and ADC3.       */

-#define CAN1_TX_IRQHandler      Vector8C    /**< CAN1 TX.                   */

-#define CAN1_RX0_IRQHandler     Vector90    /**< CAN1 RX0.                  */

-#define CAN1_RX1_IRQHandler     Vector94    /**< CAN1 RX1.                  */

-#define CAN1_SCE_IRQHandler     Vector98    /**< CAN1 SCE.                  */

-#define EXTI9_5_IRQHandler      Vector9C    /**< EXTI Line 9..5.            */

-#define TIM1_BRK_IRQHandler     VectorA0    /**< TIM1 Break.                */

-#define TIM1_UP_IRQHandler      VectorA4    /**< TIM1 Update.               */

-#define TIM1_TRG_COM_IRQHandler VectorA8    /**< TIM1 Trigger and

-                                                 Commutation.               */

-#define TIM1_CC_IRQHandler      VectorAC    /**< TIM1 Capture Compare.      */

-#define TIM2_IRQHandler         VectorB0    /**< TIM2.                      */

-#define TIM3_IRQHandler         VectorB4    /**< TIM3.                      */

-#define TIM4_IRQHandler         VectorB8    /**< TIM4.                      */

-#define I2C1_EV_IRQHandler      VectorBC    /**< I2C1 Event.                */

-#define I2C1_ER_IRQHandler      VectorC0    /**< I2C1 Error.                */

-#define I2C2_EV_IRQHandler      VectorC4    /**< I2C2 Event.                */

-#define I2C2_ER_IRQHandler      VectorC8    /**< I2C1 Error.                */

-#define SPI1_IRQHandler         VectorCC    /**< SPI1.                      */

-#define SPI2_IRQHandler         VectorD0    /**< SPI2.                      */

-#define USART1_IRQHandler       VectorD4    /**< USART1.                    */

-#define USART2_IRQHandler       VectorD8    /**< USART2.                    */

-#define USART3_IRQHandler       VectorDC    /**< USART3.                    */

-#define EXTI15_10_IRQHandler    VectorE0    /**< EXTI Line 15..10.          */

-#define RTC_Alarm_IRQHandler    VectorE4    /**< RTC alarms (A and B)

-                                                 through EXTI line.         */

-#define OTG_FS_WKUP_IRQHandler  VectorE8    /**< USB OTG FS Wakeup through

-                                                 EXTI line.                 */

-#define TIM8_BRK_IRQHandler     VectorEC    /**< TIM8 Break.                */

-#define TIM8_UP_IRQHandler      VectorF0    /**< TIM8 Update.               */

-#define TIM8_TRG_COM_IRQHandler VectorF4    /**< TIM8 Trigger and

-                                                 Commutation.               */

-#define TIM8_CC_IRQHandler      VectorF8    /**< TIM8 Capture Compare.      */

-#define DMA1_Stream7_IRQHandler VectorFC    /**< DMA1 Stream 7.             */

-#define FSMC_IRQHandler         Vector100   /**< FSMC.                      */

-#define SDIO_IRQHandler         Vector104   /**< SDIO.                      */

-#define TIM5_IRQHandler         Vector108   /**< TIM5.                      */

-#define SPI3_IRQHandler         Vector10C   /**< SPI3.                      */

-#define UART4_IRQHandler        Vector110   /**< UART4.                     */

-#define UART5_IRQHandler        Vector114   /**< UART5.                     */

-#define TIM6_IRQHandler         Vector118   /**< TIM6.                      */

-#define TIM7_IRQHandler         Vector11C   /**< TIM7.                      */

-#define DMA2_Stream0_IRQHandler Vector120   /**< DMA2 Stream0.              */

-#define DMA2_Stream1_IRQHandler Vector124   /**< DMA2 Stream1.              */

-#define DMA2_Stream2_IRQHandler Vector128   /**< DMA2 Stream2.              */

-#define DMA2_Stream3_IRQHandler Vector12C   /**< DMA2 Stream3.              */

-#define DMA2_Stream4_IRQHandler Vector130   /**< DMA2 Stream4.              */

-#define ETH_IRQHandler          Vector134   /**< Ethernet.                  */

-#define ETH_WKUP_IRQHandler     Vector138   /**< Ethernet Wakeup through

-                                                 EXTI line.                 */

-#define CAN2_TX_IRQHandler      Vector13C   /**< CAN2 TX.                   */

-#define CAN2_RX0_IRQHandler     Vector140   /**< CAN2 RX0.                  */

-#define CAN2_RX1_IRQHandler     Vector144   /**< CAN2 RX1.                  */

-#define CAN2_SCE_IRQHandler     Vector148   /**< CAN2 SCE.                  */

-#define OTG_FS_IRQHandler       Vector14C   /**< USB OTG FS.                */

-#define DMA2_Stream5_IRQHandler Vector150   /**< DMA2 Stream5.              */

-#define DMA2_Stream6_IRQHandler Vector154   /**< DMA2 Stream6.              */

-#define DMA2_Stream7_IRQHandler Vector158   /**< DMA2 Stream7.              */

-#define USART6_IRQHandler       Vector15C   /**< USART6.                    */

-#define I2C3_EV_IRQHandler      Vector160   /**< I2C3 Event.                */

-#define I2C3_ER_IRQHandler      Vector164   /**< I2C3 Error.                */

-#define OTG_HS_EP1_OUT_IRQHandler Vector168 /**< USB OTG HS End Point 1 Out.*/

-#define OTG_HS_EP1_IN_IRQHandler Vector16C  /**< USB OTG HS End Point 1 In. */                                                 

-#define OTG_HS_WKUP_IRQHandler  Vector170   /**< USB OTG HS Wakeup through

-                                                 EXTI line.                 */

-#define OTG_HS_IRQHandler       Vector174   /**< USB OTG HS.                */ 

-#define DCMI_IRQHandler         Vector178   /**< DCMI.                      */ 

-#define CRYP_IRQHandler         Vector17C   /**< CRYP.                      */ 

-#define HASH_RNG_IRQHandler     Vector180   /**< Hash and Rng.              */ 

-#if defined(STM32F4XX) || defined(__DOXYGEN__)

-#define FPU_IRQHandler          Vector184   /**< Floating Point Unit.       */

-#endif

-/** @} */

-

-/*===========================================================================*/

 /* Driver pre-compile time settings.                                         */

 /*===========================================================================*/

 

@@ -1478,59 +1191,29 @@
 

 /* There are differences in vector names in the various sub-families,

    normalizing.*/

+#if 0

 #define TIM1_BRK_IRQn       TIM1_BRK_TIM9_IRQn

 #define TIM1_UP_IRQn        TIM1_UP_TIM10_IRQn

 #define TIM1_TRG_COM_IRQn   TIM1_TRG_COM_TIM11_IRQn

 #define TIM8_BRK_IRQn       TIM8_BRK_TIM12_IRQn

 #define TIM8_UP_IRQn        TIM8_UP_TIM13_IRQn

 #define TIM8_TRG_COM_IRQn   TIM8_TRG_COM_TIM14_IRQn

+#endif

 

 /*===========================================================================*/

 /* Driver data structures and types.                                         */

 /*===========================================================================*/

 

-/**

- * @brief   Type representing a system clock frequency.

- */

-typedef uint32_t halclock_t;

-

-/**

- * @brief   Type of the realtime free counter value.

- */

-typedef uint32_t halrtcnt_t;

-

 /*===========================================================================*/

 /* Driver macros.                                                            */

 /*===========================================================================*/

 

-/**

- * @brief   Returns the current value of the system free running counter.

- * @note    This service is implemented by returning the content of the

- *          DWT_CYCCNT register.

- *

- * @return              The value of the system free running counter of

- *                      type halrtcnt_t.

- *

- * @notapi

- */

-#define hal_lld_get_counter_value()         DWT_CYCCNT

-

-/**

- * @brief   Realtime counter frequency.

- * @note    The DWT_CYCCNT register is incremented directly by the system

- *          clock so this function returns STM32_HCLK.

- *

- * @return              The realtime counter frequency of type halclock_t.

- *

- * @notapi

- */

-#define hal_lld_get_counter_frequency()     STM32_HCLK

-

 /*===========================================================================*/

 /* External declarations.                                                    */

 /*===========================================================================*/

 

-/* STM32 ISR, DMA and RCC helpers.*/

+/* Various helpers.*/

+#include "nvic.h"

 #include "stm32_isr.h"

 #include "stm32_dma.h"

 #include "stm32_rcc.h"

diff --git a/os/hal/platforms/STM32F4xx/platform.mk b/os/hal/platforms/STM32F4xx/platform.mk
index 99c3263a7..fdd725faf 100644
--- a/os/hal/platforms/STM32F4xx/platform.mk
+++ b/os/hal/platforms/STM32F4xx/platform.mk
@@ -1,5 +1,6 @@
 # List of all the STM32F2xx/STM32F4xx platform files.

-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F4xx/stm32_dma.c \

+PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/common/ARMCMx/nvic.c \

+              ${CHIBIOS}/os/hal/platforms/STM32F4xx/stm32_dma.c \

               ${CHIBIOS}/os/hal/platforms/STM32F4xx/hal_lld.c \

               ${CHIBIOS}/os/hal/platforms/STM32F4xx/adc_lld.c \

               ${CHIBIOS}/os/hal/platforms/STM32F4xx/ext_lld_isr.c \

@@ -15,11 +16,13 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F4xx/stm32_dma.c \
               ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/gpt_lld.c \

               ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/icu_lld.c \

               ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/pwm_lld.c \

+              ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/st_lld.c \

               ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/serial_lld.c \

               ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/uart_lld.c

 

 # Required include directories

-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F4xx \

+PLATFORMINC = ${CHIBIOS}/os/hal/platforms/common/ARMCMx \

+              ${CHIBIOS}/os/hal/platforms/STM32F4xx \

               ${CHIBIOS}/os/hal/platforms/STM32 \

               ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \

               ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1 \

diff --git a/os/hal/platforms/STM32F4xx/stm32_registry.h b/os/hal/platforms/STM32F4xx/stm32_registry.h
new file mode 100644
index 000000000..ba462175c
--- /dev/null
+++ b/os/hal/platforms/STM32F4xx/stm32_registry.h
@@ -0,0 +1,265 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    STM32F4xx/stm32_registry.h

+ * @brief   STM32F4xx capabilities registry.

+ *

+ * @addtogroup HAL

+ * @{

+ */

+

+#ifndef _STM32_REGISTRY_H_

+#define _STM32_REGISTRY_H_

+

+#if defined(STM32F40XX) || defined(STM32F427X)

+#define STM32F4XX

+#endif

+

+/*===========================================================================*/

+/* Platform capabilities.                                                    */

+/*===========================================================================*/

+

+/**

+ * @name    STM32F30x capabilities

+ * @{

+ */

+/* ADC attributes.*/

+#define STM32_HAS_ADC1                      TRUE

+#define STM32_ADC1_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(2, 0) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 4))

+#define STM32_ADC1_DMA_CHN                  0x00000000

+

+#define STM32_HAS_ADC2                      TRUE

+#define STM32_ADC2_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(2, 2) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 3))

+#define STM32_ADC2_DMA_CHN                  0x00001100

+

+#define STM32_HAS_ADC3                      TRUE

+#define STM32_ADC3_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(2, 0) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 1))

+#define STM32_ADC3_DMA_CHN                  0x00000022

+

+#define STM32_HAS_ADC4                      FALSE

+

+#define STM32_HAS_SDADC1                    FALSE

+#define STM32_HAS_SDADC2                    FALSE

+#define STM32_HAS_SDADC3                    FALSE

+

+/* CAN attributes.*/

+#define STM32_HAS_CAN1                      TRUE

+#define STM32_HAS_CAN2                      TRUE

+#define STM32_CAN_MAX_FILTERS               28

+

+/* DAC attributes.*/

+#define STM32_HAS_DAC1                      TRUE

+#define STM32_HAS_DAC2                      FALSE

+

+/* DMA attributes.*/

+#define STM32_ADVANCED_DMA                  TRUE

+#define STM32_HAS_DMA1                      TRUE

+#define STM32_HAS_DMA2                      TRUE

+

+/* ETH attributes.*/

+#define STM32_HAS_ETH                       TRUE

+

+/* EXTI attributes.*/

+#define STM32_EXTI_NUM_CHANNELS             23

+

+/* GPIO attributes.*/

+#define STM32_HAS_GPIOA                     TRUE

+#define STM32_HAS_GPIOB                     TRUE

+#define STM32_HAS_GPIOC                     TRUE

+#define STM32_HAS_GPIOD                     TRUE

+#define STM32_HAS_GPIOE                     TRUE

+#define STM32_HAS_GPIOF                     TRUE

+#define STM32_HAS_GPIOG                     TRUE

+#define STM32_HAS_GPIOH                     TRUE

+#define STM32_HAS_GPIOI                     TRUE

+

+/* I2C attributes.*/

+#define STM32_HAS_I2C1                      TRUE

+#define STM32_I2C1_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 0) |\

+                                             STM32_DMA_STREAM_ID_MSK(1, 5))

+#define STM32_I2C1_RX_DMA_CHN               0x00100001

+#define STM32_I2C1_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 7) |\

+                                             STM32_DMA_STREAM_ID_MSK(1, 6))

+#define STM32_I2C1_TX_DMA_CHN               0x11000000

+

+#define STM32_HAS_I2C2                      TRUE

+#define STM32_I2C2_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 2) |\

+                                             STM32_DMA_STREAM_ID_MSK(1, 3))

+#define STM32_I2C2_RX_DMA_CHN               0x00007700

+#define STM32_I2C2_TX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 7)

+#define STM32_I2C2_TX_DMA_CHN               0x70000000

+

+#define STM32_HAS_I2C3                      TRUE

+#define STM32_I2C3_RX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 2)

+#define STM32_I2C3_RX_DMA_CHN               0x00000300

+#define STM32_I2C3_TX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 4)

+#define STM32_I2C3_TX_DMA_CHN               0x00030000

+

+/* RTC attributes.*/

+#define STM32_HAS_RTC                       TRUE

+#if defined(STM32F4XX) || defined(__DOXYGEN__)

+#define STM32_RTC_HAS_SUBSECONDS            TRUE

+#else

+#define STM32_RTC_HAS_SUBSECONDS            FALSE

+#endif

+#define STM32_RTC_IS_CALENDAR               TRUE

+

+/* SDIO attributes.*/

+#define STM32_HAS_SDIO                      TRUE

+#define STM32_SDC_SDIO_DMA_MSK              (STM32_DMA_STREAM_ID_MSK(2, 3) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 6))

+#define STM32_SDC_SDIO_DMA_CHN              0x04004000

+

+/* SPI attributes.*/

+#define STM32_HAS_SPI1                      TRUE

+#define STM32_SPI1_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 0) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 2))

+#define STM32_SPI1_RX_DMA_CHN               0x00000303

+#define STM32_SPI1_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 3) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 5))

+#define STM32_SPI1_TX_DMA_CHN               0x00303000

+

+#define STM32_HAS_SPI2                      TRUE

+#define STM32_SPI2_RX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 3)

+#define STM32_SPI2_RX_DMA_CHN               0x00000000

+#define STM32_SPI2_TX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 4)

+#define STM32_SPI2_TX_DMA_CHN               0x00000000

+

+#define STM32_HAS_SPI3                      TRUE

+#define STM32_SPI3_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 0) |\

+                                             STM32_DMA_STREAM_ID_MSK(1, 2))

+#define STM32_SPI3_RX_DMA_CHN               0x00000000

+#define STM32_SPI3_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 5) |\

+                                             STM32_DMA_STREAM_ID_MSK(1, 7))

+#define STM32_SPI3_TX_DMA_CHN               0x00000000

+

+/* TIM attributes.*/

+#define STM32_HAS_TIM1                      TRUE

+#define STM32_TIM1_IS_32BITS                FALSE

+#define STM32_TIM1_CHANNELS                 4

+

+#define STM32_HAS_TIM2                      TRUE

+#define STM32_TIM2_IS_32BITS                TRUE

+#define STM32_TIM2_CHANNELS                 4

+

+#define STM32_HAS_TIM3                      TRUE

+#define STM32_TIM3_IS_32BITS                FALSE

+#define STM32_TIM3_CHANNELS                 4

+

+#define STM32_HAS_TIM4                      TRUE

+#define STM32_TIM4_IS_32BITS                FALSE

+#define STM32_TIM4_CHANNELS                 4

+

+#define STM32_HAS_TIM5                      TRUE

+#define STM32_TIM5_IS_32BITS                TRUE

+#define STM32_TIM5_CHANNELS                 4

+

+#define STM32_HAS_TIM6                      TRUE

+#define STM32_TIM6_IS_32BITS                FALSE

+#define STM32_TIM6_CHANNELS                 0

+

+#define STM32_HAS_TIM7                      TRUE

+#define STM32_TIM7_IS_32BITS                FALSE

+#define STM32_TIM7_CHANNELS                 0

+

+#define STM32_HAS_TIM8                      TRUE

+#define STM32_TIM8_IS_32BITS                FALSE

+#define STM32_TIM8_CHANNELS                 6

+

+#define STM32_HAS_TIM9                      TRUE

+#define STM32_TIM9_IS_32BITS                FALSE

+#define STM32_TIM9_CHANNELS                 2

+

+#define STM32_HAS_TIM10                     TRUE

+#define STM32_TIM10_IS_32BITS               FALSE

+#define STM32_TIM10_CHANNELS                2

+

+#define STM32_HAS_TIM11                     TRUE

+#define STM32_TIM11_IS_32BITS               FALSE

+#define STM32_TIM11_CHANNELS                2

+

+#define STM32_HAS_TIM12                     TRUE

+#define STM32_TIM12_IS_32BITS               FALSE

+#define STM32_TIM12_CHANNELS                2

+

+#define STM32_HAS_TIM13                     TRUE

+#define STM32_TIM13_IS_32BITS               FALSE

+#define STM32_TIM13_CHANNELS                2

+

+#define STM32_HAS_TIM14                     TRUE

+#define STM32_TIM14_IS_32BITS               FALSE

+#define STM32_TIM14_CHANNELS                2

+

+#define STM32_HAS_TIM15                     FALSE

+#define STM32_HAS_TIM16                     FALSE

+#define STM32_HAS_TIM17                     FALSE

+#define STM32_HAS_TIM18                     FALSE

+#define STM32_HAS_TIM19                     FALSE

+

+/* USART attributes.*/

+#define STM32_HAS_USART1                    TRUE

+#define STM32_USART1_RX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(2, 2) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 5))

+#define STM32_USART1_RX_DMA_CHN             0x00400400

+#define STM32_USART1_TX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(2, 7)

+#define STM32_USART1_TX_DMA_CHN             0x40000000

+

+#define STM32_HAS_USART2                    TRUE

+#define STM32_USART2_RX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(1, 5)

+#define STM32_USART2_RX_DMA_CHN             0x00400000

+#define STM32_USART2_TX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(1, 6)

+#define STM32_USART2_TX_DMA_CHN             0x04000000

+

+#define STM32_HAS_USART3                    TRUE

+#define STM32_USART3_RX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(1, 1)

+#define STM32_USART3_RX_DMA_CHN             0x00000040

+#define STM32_USART3_TX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(1, 3) |\

+                                             STM32_DMA_STREAM_ID_MSK(1, 4))

+#define STM32_USART3_TX_DMA_CHN             0x00074000

+

+#define STM32_HAS_UART4                     TRUE

+#define STM32_UART4_RX_DMA_MSK              STM32_DMA_STREAM_ID_MSK(1, 2)

+#define STM32_UART4_RX_DMA_CHN              0x00000400

+#define STM32_UART4_TX_DMA_MSK              STM32_DMA_STREAM_ID_MSK(1, 4)

+#define STM32_UART4_TX_DMA_CHN              0x00040000

+

+#define STM32_HAS_UART5                     TRUE

+#define STM32_UART5_RX_DMA_MSK              STM32_DMA_STREAM_ID_MSK(1, 0)

+#define STM32_UART5_RX_DMA_CHN              0x00000004

+#define STM32_UART5_TX_DMA_MSK              STM32_DMA_STREAM_ID_MSK(1, 7)

+#define STM32_UART5_TX_DMA_CHN              0x40000000

+

+#define STM32_HAS_USART6                    TRUE

+#define STM32_USART6_RX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(2, 1) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 2))

+#define STM32_USART6_RX_DMA_CHN             0x00000550

+#define STM32_USART6_TX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(2, 6) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 7))

+#define STM32_USART6_TX_DMA_CHN             0x55000000

+

+/* USB attributes.*/

+#define STM32_HAS_USB                       FALSE

+#define STM32_HAS_OTG1                      TRUE

+#define STM32_HAS_OTG2                      TRUE

+/** @} */

+

+#endif /* _STM32_REGISTRY_H_ */

+

+/** @} */