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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2016-02-06 10:57:37 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2016-02-06 10:57:37 +0000 |
| commit | e830caa11c88812d1c738c446c83946803e49d05 (patch) | |
| tree | 171afde9efe137e7be60a0db4545cf645e7c6ba4 /os/hal | |
| parent | b566f82aea098fedc61f0d3b8acb7fd7789b4457 (diff) | |
| download | ChibiOS-e830caa11c88812d1c738c446c83946803e49d05.tar.gz ChibiOS-e830caa11c88812d1c738c446c83946803e49d05.tar.bz2 ChibiOS-e830caa11c88812d1c738c446c83946803e49d05.zip | |
Fixed bug #698.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8838 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal')
| -rw-r--r-- | os/hal/include/hal.h | 4 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F0xx/stm32_rcc.h | 18 |
2 files changed, 11 insertions, 11 deletions
diff --git a/os/hal/include/hal.h b/os/hal/include/hal.h index b030ae7ae..0f501c794 100644 --- a/os/hal/include/hal.h +++ b/os/hal/include/hal.h @@ -103,7 +103,7 @@ /**
* @brief HAL version string.
*/
-#define HAL_VERSION "4.0.0dev"
+#define HAL_VERSION "4.1.0"
/**
* @brief HAL version major number.
@@ -113,7 +113,7 @@ /**
* @brief HAL version minor number.
*/
-#define CH_HAL_MINOR 0
+#define CH_HAL_MINOR 1
/**
* @brief HAL version patch number.
diff --git a/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h index 22b0e8806..82d923159 100644 --- a/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h @@ -645,7 +645,7 @@ *
* @api
*/
-#define rccEnableTIM15(lp) rccEnableAPB1(RCC_APB2ENR_TIM15EN, lp)
+#define rccEnableTIM15(lp) rccEnableAPB2(RCC_APB2ENR_TIM15EN, lp)
/**
* @brief Disables the TIM15 peripheral clock.
@@ -655,14 +655,14 @@ *
* @api
*/
-#define rccDisableTIM15(lp) rccDisableAPB1(RCC_APB2ENR_TIM15EN, lp)
+#define rccDisableTIM15(lp) rccDisableAPB2(RCC_APB2ENR_TIM15EN, lp)
/**
* @brief Resets the TIM15 peripheral.
*
* @api
*/
-#define rccResetTIM15() rccResetAPB1(RCC_APB2RSTR_TIM15RST)
+#define rccResetTIM15() rccResetAPB2(RCC_APB2RSTR_TIM15RST)
/**
* @brief Enables the TIM16 peripheral clock.
@@ -672,7 +672,7 @@ *
* @api
*/
-#define rccEnableTIM16(lp) rccEnableAPB1(RCC_APB2ENR_TIM16EN, lp)
+#define rccEnableTIM16(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp)
/**
* @brief Disables the TIM16 peripheral clock.
@@ -682,14 +682,14 @@ *
* @api
*/
-#define rccDisableTIM16(lp) rccDisableAPB1(RCC_APB2ENR_TIM16EN, lp)
+#define rccDisableTIM16(lp) rccDisableAPB2(RCC_APB2ENR_TIM16EN, lp)
/**
* @brief Resets the TIM16 peripheral.
*
* @api
*/
-#define rccResetTIM16() rccResetAPB1(RCC_APB2RSTR_TIM16RST)
+#define rccResetTIM16() rccResetAPB2(RCC_APB2RSTR_TIM16RST)
/**
* @brief Enables the TIM17 peripheral clock.
@@ -699,7 +699,7 @@ *
* @api
*/
-#define rccEnableTIM17(lp) rccEnableAPB1(RCC_APB2ENR_TIM17EN, lp)
+#define rccEnableTIM17(lp) rccEnableAPB2(RCC_APB2ENR_TIM17EN, lp)
/**
* @brief Disables the TIM17 peripheral clock.
@@ -709,14 +709,14 @@ *
* @api
*/
-#define rccDisableTIM17(lp) rccDisableAPB1(RCC_APB2ENR_TIM17EN, lp)
+#define rccDisableTIM17(lp) rccDisableAPB2(RCC_APB2ENR_TIM17EN, lp)
/**
* @brief Resets the TIM17 peripheral.
*
* @api
*/
-#define rccResetTIM17() rccResetAPB1(RCC_APB2RSTR_TIM17RST)
+#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST)
/** @} */
/**
|