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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-06-02 12:49:52 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-06-02 12:49:52 +0000 |
| commit | e2995ec061e53af408ae28525626e630cf970ad1 (patch) | |
| tree | 2fe16eb1499fba2114d316933b7d9a2d89353a1e /os/hal | |
| parent | d511d35dea0fe7bfcc5c241eb1410a81bf0c8142 (diff) | |
| download | ChibiOS-e2995ec061e53af408ae28525626e630cf970ad1.tar.gz ChibiOS-e2995ec061e53af408ae28525626e630cf970ad1.tar.bz2 ChibiOS-e2995ec061e53af408ae28525626e630cf970ad1.zip | |
ADCv3 oversampling support.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12074 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'os/hal')
| -rw-r--r-- | os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c | 3 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h | 25 |
2 files changed, 23 insertions, 5 deletions
diff --git a/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c b/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c index 8885b3a81..7c09ed160 100644 --- a/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c +++ b/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c @@ -863,6 +863,9 @@ void adc_lld_start_conversion(ADCDriver *adcp) { /* ADC configuration.*/
adcp->adcm->CFGR = cfgr;
+#if (STM32_ADCV3_OVERSAMPLING == TRUE) || defined(__DOXYGEN__)
+ adcp->adcm->CFGR2 = grpp->cfgr2;
+#endif
/* Starting conversion.*/
adcp->adcm->CR |= ADC_CR_ADSTART;
diff --git a/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h b/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h index 847dbbd17..c274fa96d 100644 --- a/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h +++ b/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h @@ -335,8 +335,14 @@ /*===========================================================================*/
/* Supported devices checks.*/
-#if !defined(STM32F3XX) && !defined(STM32L4XX)
-#error "ADCv3 only supports F3 and L4 STM32 devices"
+#if !defined(STM32F3XX) && !defined(STM32L4XX) && !defined(STM32L4XXP)
+#error "ADCv3 only supports F3, L4 and L4+ STM32 devices"
+#endif
+
+#if defined(STM32L4XX) || defined(STM32L4XXP) || defined(__DOXYGEN__)
+#define STM32_ADCV3_OVERSAMPLING TRUE
+#else
+#define STM32_ADCV3_OVERSAMPLING FALSE
#endif
/* Registry checks.*/
@@ -668,6 +674,17 @@ typedef struct { * greater than one.
*/
uint32_t cfgr;
+#if (STM32_ADCV3_OVERSAMPLING == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief ADC CFGR2 register initialization data.
+ * @note The bits DMAEN and DMACFG are enforced internally
+ * to the driver, keep them to zero.
+ * @note The bits @p ADC_CFGR_CONT or @p ADC_CFGR_DISCEN must be
+ * specified in continuous mode or if the buffer depth is
+ * greater than one.
+ */
+ uint32_t cfgr2;
+#endif
/**
* @brief ADC TR1 register initialization data.
*/
@@ -675,9 +692,7 @@ typedef struct { #if STM32_ADC_DUAL_MODE || defined(__DOXYGEN__)
/**
* @brief ADC CCR register initialization data.
- * @note The bits CKMODE, MDMA, DMACFG are enforced internally to the
- * driver, keep them to zero.
- * @note This field is only present in dual mode.
+ * @note Put this field to zero if not using oversampling.
*/
uint32_t ccr;
#endif
|