git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4307 35acf78f-673a-0410-8e92-d51de3d6d3f4

14 files changed, 174 insertions, 20 deletions

diff --git a/os/hal/platforms/STM32/can_lld.c b/os/hal/platforms/STM32/can_lld.c
index 3c577c346..a252d6889 100644
--- a/os/hal/platforms/STM32/can_lld.c
+++ b/os/hal/platforms/STM32/can_lld.c
@@ -184,9 +184,9 @@ void can_lld_start(CANDriver *canp) {
   /* Clock activation.*/

 #if STM32_CAN_USE_CAN1

   if (&CAND1 == canp) {

-    nvicEnableVector(USB_HP_CAN1_TX_IRQn,

+    nvicEnableVector(CAN1_TX_IRQn,

                      CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));

-    nvicEnableVector(USB_LP_CAN1_RX0_IRQn,

+    nvicEnableVector(CAN1_RX0_IRQn,

                      CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));

     nvicEnableVector(CAN1_RX1_IRQn,

                      CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));

@@ -217,7 +217,7 @@ void can_lld_start(CANDriver *canp) {
     canp->can->FFA1R = 0;

     cfp = canp->can->sFilterRegister;

     fmask = 1;

-    for (i = 0; i < CAN_MAX_FILTERS; i++) {

+    for (i = 0; i < STM32_CAN_MAX_FILTERS; i++) {

       if (i < canp->config->num) {

         if (canp->config->filters[i].mode)

           canp->can->FM1R |= fmask;

@@ -272,8 +272,8 @@ void can_lld_stop(CANDriver *canp) {
     if (&CAND1 == canp) {

       CAN1->MCR = 0x00010002;                   /* Register reset value.    */

       CAN1->IER = 0x00000000;                   /* All sources disabled.    */

-      nvicDisableVector(USB_HP_CAN1_TX_IRQn);

-      nvicDisableVector(USB_LP_CAN1_RX0_IRQn);

+      nvicDisableVector(CAN1_TX_IRQn);

+      nvicDisableVector(CAN1_RX0_IRQn);

       nvicDisableVector(CAN1_RX1_IRQn);

       nvicDisableVector(CAN1_SCE_IRQn);

       rccDisableCAN1(FALSE);

diff --git a/os/hal/platforms/STM32/can_lld.h b/os/hal/platforms/STM32/can_lld.h
index d9bf3bb39..273b95fa0 100644
--- a/os/hal/platforms/STM32/can_lld.h
+++ b/os/hal/platforms/STM32/can_lld.h
@@ -51,14 +51,9 @@
 #define CAN_SUPPORTS_SLEEP          TRUE

 

 /**

- * @brief   Minimum number of CAN filters.

+ * @name    CAN registers helper macros

+ * @{

  */

-#if defined(STM32F10X_CL) || defined(__DOXYGEN__)

-#define CAN_MAX_FILTERS             28

-#else

-#define CAN_MAX_FILTERS             14

-#endif

-

 #define CAN_BTR_BRP(n)              (n)         /**< @brief BRP field macro.*/

 #define CAN_BTR_TS1(n)              ((n) << 16) /**< @brief TS1 field macro.*/

 #define CAN_BTR_TS2(n)              ((n) << 20) /**< @brief TS2 field macro.*/

@@ -69,6 +64,7 @@
 

 #define CAN_RTR_DATA                0           /**< @brief Data frame.     */

 #define CAN_RTR_REMOTE              1           /**< @brief Remote frame.   */

+/** @} */

 

 /*===========================================================================*/

 /* Driver pre-compile time settings.                                         */

diff --git a/os/hal/platforms/STM32/stm32.h b/os/hal/platforms/STM32/stm32.h
index 49c1c08bb..a872a2a00 100644
--- a/os/hal/platforms/STM32/stm32.h
+++ b/os/hal/platforms/STM32/stm32.h
@@ -54,13 +54,17 @@
       defined(__DOXYGEN__)

 #include "stm32f10x.h"

 

-#elif defined(STM32F2XX) || defined(__DOXYGEN__)

+/* Resolving naming anomalies related to the STM32F1xx sub-family.*/

+#define CAN1_TX_IRQn        USB_HP_CAN1_TX_IRQn

+#define CAN1_RX0_IRQn       USB_LP_CAN1_RX0_IRQn

+

+#elif defined(STM32F2XX)

 #include "stm32f2xx.h"

 

-#elif defined(STM32F4XX) || defined(__DOXYGEN__)

+#elif defined(STM32F4XX)

 #include "stm32f4xx.h"

 

-#elif defined(STM32L1XX_MD) || defined(__DOXYGEN__)

+#elif defined(STM32L1XX_MD)

 #include "stm32l1xx.h"

 

 #else

diff --git a/os/hal/platforms/STM32F0xx/hal_lld.h b/os/hal/platforms/STM32F0xx/hal_lld.h
index f5c32a82d..93403c91f 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.h
+++ b/os/hal/platforms/STM32F0xx/hal_lld.h
@@ -238,6 +238,7 @@
 /* CAN attributes.*/

 #define STM32_HAS_CAN1          FALSE

 #define STM32_HAS_CAN2          FALSE

+#define STM32_CAN_MAX_FILTERS   0

 

 /* DAC attributes.*/

 #define STM32_HAS_DAC           TRUE

diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/os/hal/platforms/STM32F1xx/hal_lld_f100.h
index 3237fd5d0..4cf678935 100644
--- a/os/hal/platforms/STM32F1xx/hal_lld_f100.h
+++ b/os/hal/platforms/STM32F1xx/hal_lld_f100.h
@@ -199,6 +199,7 @@
 /* CAN attributes.*/

 #define STM32_HAS_CAN1          FALSE

 #define STM32_HAS_CAN2          FALSE

+#define STM32_CAN_MAX_FILTERS   0

 

 /* DAC attributes.*/

 #define STM32_HAS_DAC           TRUE

@@ -342,6 +343,7 @@
 /* CAN attributes.*/

 #define STM32_HAS_CAN1          FALSE

 #define STM32_HAS_CAN2          FALSE

+#define STM32_CAN_MAX_FILTERS   0

 

 /* DAC attributes.*/

 #define STM32_HAS_DAC           TRUE

diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f103.h b/os/hal/platforms/STM32F1xx/hal_lld_f103.h
index 02b08cb8f..7c58c502c 100644
--- a/os/hal/platforms/STM32F1xx/hal_lld_f103.h
+++ b/os/hal/platforms/STM32F1xx/hal_lld_f103.h
@@ -209,6 +209,7 @@
 /* CAN attributes.*/

 #define STM32_HAS_CAN1          TRUE

 #define STM32_HAS_CAN2          FALSE

+#define STM32_CAN_MAX_FILTERS   14

 

 /* DAC attributes.*/

 #define STM32_HAS_DAC           FALSE

@@ -352,6 +353,7 @@
 /* CAN attributes.*/

 #define STM32_HAS_CAN1          TRUE

 #define STM32_HAS_CAN2          FALSE

+#define STM32_CAN_MAX_FILTERS   14

 

 /* DAC attributes.*/

 #define STM32_HAS_DAC           FALSE

@@ -499,6 +501,7 @@
 /* CAN attributes.*/

 #define STM32_HAS_CAN1          TRUE

 #define STM32_HAS_CAN2          FALSE

+#define STM32_CAN_MAX_FILTERS   14

 

 /* DAC attributes.*/

 #define STM32_HAS_DAC           TRUE

@@ -646,6 +649,7 @@
 /* CAN attributes.*/

 #define STM32_HAS_CAN1          TRUE

 #define STM32_HAS_CAN2          FALSE

+#define STM32_CAN_MAX_FILTERS   14

 

 /* DAC attributes.*/

 #define STM32_HAS_DAC           TRUE

diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h
index 139402bd4..5b641dfcf 100644
--- a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h
+++ b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h
@@ -226,6 +226,7 @@
 /* CAN attributes.*/

 #define STM32_HAS_CAN1          TRUE

 #define STM32_HAS_CAN2          TRUE

+#define STM32_CAN_MAX_FILTERS   28

 

 /* DAC attributes.*/

 #define STM32_HAS_DAC           TRUE

diff --git a/os/hal/platforms/STM32F2xx/hal_lld.h b/os/hal/platforms/STM32F2xx/hal_lld.h
index ee260fdbb..4bccae76b 100644
--- a/os/hal/platforms/STM32F2xx/hal_lld.h
+++ b/os/hal/platforms/STM32F2xx/hal_lld.h
@@ -287,6 +287,7 @@
 /* CAN attributes.*/

 #define STM32_HAS_CAN1          TRUE

 #define STM32_HAS_CAN2          TRUE

+#define STM32_CAN_MAX_FILTERS   28

 

 /* DAC attributes.*/

 #define STM32_HAS_DAC           TRUE

diff --git a/os/hal/platforms/STM32F2xx/platform.mk b/os/hal/platforms/STM32F2xx/platform.mk
index 92dca2228..b4793c02b 100644
--- a/os/hal/platforms/STM32F2xx/platform.mk
+++ b/os/hal/platforms/STM32F2xx/platform.mk
@@ -2,6 +2,7 @@
 PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F2xx/stm32_dma.c \

               ${CHIBIOS}/os/hal/platforms/STM32F2xx/hal_lld.c \

               ${CHIBIOS}/os/hal/platforms/STM32F2xx/adc_lld.c \

+              ${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \

               ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \

               ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \

               ${CHIBIOS}/os/hal/platforms/STM32/i2c_lld.c \

diff --git a/os/hal/platforms/STM32F2xx/stm32_rcc.h b/os/hal/platforms/STM32F2xx/stm32_rcc.h
index 226164ba4..0bd3a6401 100644
--- a/os/hal/platforms/STM32F2xx/stm32_rcc.h
+++ b/os/hal/platforms/STM32F2xx/stm32_rcc.h
@@ -391,12 +391,11 @@
 /** @} */

 

 /**

- * @name   PWR interface specific RCC operations

+ * @name    PWR interface specific RCC operations

  * @{

  */

 /**

  * @brief   Enables the PWR interface clock.

- * @note    The @p lp parameter is ignored in this family.

  *

  * @param[in] lp        low power enable flag

  *

@@ -406,7 +405,6 @@
 

 /**

  * @brief   Disables PWR interface clock.

- * @note    The @p lp parameter is ignored in this family.

  *

  * @param[in] lp        low power enable flag

  *

@@ -422,6 +420,62 @@
 #define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)

 /** @} */

 

+

+/**

+ * @name    CAN peripherals specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the CAN1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CAN1EN, lp)

+

+/**

+ * @brief   Disables the CAN1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CAN1EN, lp)

+

+/**

+ * @brief   Resets the CAN1 peripheral.

+ *

+ * @api

+ */

+#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CAN1RST)

+

+/**

+ * @brief   Enables the CAN2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableCAN2(lp) rccEnableAPB1(RCC_APB1ENR_CAN2EN, lp)

+

+/**

+ * @brief   Disables the CAN2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableCAN2(lp) rccDisableAPB1(RCC_APB1ENR_CAN2EN, lp)

+

+/**

+ * @brief   Resets the CAN2 peripheral.

+ *

+ * @api

+ */

+#define rccResetCAN2() rccResetAPB1(RCC_APB1RSTR_CAN2RST)

+/** @} */

+

 /**

  * @name    ETH peripheral specific RCC operations

  * @{

@@ -569,6 +623,39 @@
 /** @} */

 

 /**

+ * @name    SDIO peripheral specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the SDIO peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableSDIO(lp) rccEnableAPB2(RCC_APB2ENR_SDIOEN, lp)

+

+/**

+ * @brief   Disables the SDIO peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableSDIO(lp) rccDisableAPB2(RCC_APB2ENR_SDIOEN, lp)

+

+/**

+ * @brief   Resets the SDIO peripheral.

+ * @note    Not supported in this family, does nothing.

+ *

+ * @api

+ */

+#define rccResetSDIO() rccResetAPB2(RCC_APB2RSTR_SDIORST)

+/** @} */

+

+/**

  * @name    SPI peripherals specific RCC operations

  * @{

  */

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h
index 8c5303350..a755f5aa5 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.h
+++ b/os/hal/platforms/STM32F4xx/hal_lld.h
@@ -286,6 +286,7 @@
 /* CAN attributes.*/

 #define STM32_HAS_CAN1          TRUE

 #define STM32_HAS_CAN2          TRUE

+#define STM32_CAN_MAX_FILTERS   28

 

 /* DAC attributes.*/

 #define STM32_HAS_DAC           TRUE

diff --git a/os/hal/platforms/STM32F4xx/platform.mk b/os/hal/platforms/STM32F4xx/platform.mk
index 5194488b8..5422ab5e6 100644
--- a/os/hal/platforms/STM32F4xx/platform.mk
+++ b/os/hal/platforms/STM32F4xx/platform.mk
@@ -2,6 +2,7 @@
 PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F4xx/stm32_dma.c \

               ${CHIBIOS}/os/hal/platforms/STM32F4xx/hal_lld.c \

               ${CHIBIOS}/os/hal/platforms/STM32F4xx/adc_lld.c \

+              ${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \

               ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \

               ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \

               ${CHIBIOS}/os/hal/platforms/STM32/i2c_lld.c \

diff --git a/os/hal/platforms/STM32F4xx/stm32_rcc.h b/os/hal/platforms/STM32F4xx/stm32_rcc.h
index 9ccb4a960..367318e04 100644
--- a/os/hal/platforms/STM32F4xx/stm32_rcc.h
+++ b/os/hal/platforms/STM32F4xx/stm32_rcc.h
@@ -396,7 +396,6 @@
  */

 /**

  * @brief   Enables the PWR interface clock.

- * @note    The @p lp parameter is ignored in this family.

  *

  * @param[in] lp        low power enable flag

  *

@@ -406,7 +405,6 @@
 

 /**

  * @brief   Disables PWR interface clock.

- * @note    The @p lp parameter is ignored in this family.

  *

  * @param[in] lp        low power enable flag

  *

@@ -422,6 +420,62 @@
 #define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)

 /** @} */

 

+

+/**

+ * @name    CAN peripherals specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the CAN1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CAN1EN, lp)

+

+/**

+ * @brief   Disables the CAN1 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CAN1EN, lp)

+

+/**

+ * @brief   Resets the CAN1 peripheral.

+ *

+ * @api

+ */

+#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CAN1RST)

+

+/**

+ * @brief   Enables the CAN2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableCAN2(lp) rccEnableAPB1(RCC_APB1ENR_CAN2EN, lp)

+

+/**

+ * @brief   Disables the CAN2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableCAN2(lp) rccDisableAPB1(RCC_APB1ENR_CAN2EN, lp)

+

+/**

+ * @brief   Resets the CAN2 peripheral.

+ *

+ * @api

+ */

+#define rccResetCAN2() rccResetAPB1(RCC_APB1RSTR_CAN2RST)

+/** @} */

+

 /**

  * @name    ETH peripheral specific RCC operations

  * @{

diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h
index e7c27ceb8..e41f922b6 100644
--- a/os/hal/platforms/STM32L1xx/hal_lld.h
+++ b/os/hal/platforms/STM32L1xx/hal_lld.h
@@ -186,6 +186,7 @@
 /* CAN attributes.*/

 #define STM32_HAS_CAN1          FALSE

 #define STM32_HAS_CAN2          FALSE

+#define STM32_CAN_MAX_FILTERS   0

 

 /* DAC attributes.*/

 #define STM32_HAS_DAC           TRUE